1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * Low-Level PCI Access for i386 machines. |
4 | * |
5 | * (c) 1999 Martin Mares <mj@ucw.cz> |
6 | */ |
7 | |
8 | #include <linux/errno.h> |
9 | #include <linux/init.h> |
10 | #include <linux/ioport.h> |
11 | #include <linux/spinlock.h> |
12 | |
13 | #undef DEBUG |
14 | |
15 | #ifdef DEBUG |
16 | #define DBG(fmt, ...) printk(fmt, ##__VA_ARGS__) |
17 | #else |
18 | #define DBG(fmt, ...) \ |
19 | do { \ |
20 | if (0) \ |
21 | printk(fmt, ##__VA_ARGS__); \ |
22 | } while (0) |
23 | #endif |
24 | |
25 | #define PCI_PROBE_BIOS 0x0001 |
26 | #define PCI_PROBE_CONF1 0x0002 |
27 | #define PCI_PROBE_CONF2 0x0004 |
28 | #define PCI_PROBE_MMCONF 0x0008 |
29 | #define PCI_PROBE_MASK 0x000f |
30 | #define PCI_PROBE_NOEARLY 0x0010 |
31 | |
32 | #define PCI_NO_CHECKS 0x0400 |
33 | #define PCI_USE_PIRQ_MASK 0x0800 |
34 | #define PCI_ASSIGN_ROMS 0x1000 |
35 | #define PCI_BIOS_IRQ_SCAN 0x2000 |
36 | #define PCI_ASSIGN_ALL_BUSSES 0x4000 |
37 | #define PCI_CAN_SKIP_ISA_ALIGN 0x8000 |
38 | #define PCI_USE__CRS 0x10000 |
39 | #define PCI_CHECK_ENABLE_AMD_MMCONF 0x20000 |
40 | #define PCI_HAS_IO_ECS 0x40000 |
41 | #define PCI_NOASSIGN_ROMS 0x80000 |
42 | #define PCI_ROOT_NO_CRS 0x100000 |
43 | #define PCI_NOASSIGN_BARS 0x200000 |
44 | #define PCI_BIG_ROOT_WINDOW 0x400000 |
45 | #define PCI_USE_E820 0x800000 |
46 | #define PCI_NO_E820 0x1000000 |
47 | |
48 | extern unsigned int pci_probe; |
49 | extern unsigned long pirq_table_addr; |
50 | |
51 | enum pci_bf_sort_state { |
52 | pci_bf_sort_default, |
53 | pci_force_nobf, |
54 | pci_force_bf, |
55 | pci_dmi_bf, |
56 | }; |
57 | |
58 | /* pci-i386.c */ |
59 | |
60 | void pcibios_resource_survey(void); |
61 | void pcibios_set_cache_line_size(void); |
62 | |
63 | /* pci-pc.c */ |
64 | |
65 | extern int pcibios_last_bus; |
66 | extern struct pci_ops pci_root_ops; |
67 | |
68 | void pcibios_scan_specific_bus(int busn); |
69 | |
70 | /* pci-irq.c */ |
71 | |
72 | struct pci_dev; |
73 | |
74 | struct irq_info { |
75 | u8 bus, devfn; /* Bus, device and function */ |
76 | struct { |
77 | u8 link; /* IRQ line ID, chipset dependent, |
78 | 0 = not routed */ |
79 | u16 bitmap; /* Available IRQs */ |
80 | } __attribute__((packed)) irq[4]; |
81 | u8 slot; /* Slot number, 0=onboard */ |
82 | u8 rfu; |
83 | } __attribute__((packed)); |
84 | |
85 | struct irq_routing_table { |
86 | u32 signature; /* PIRQ_SIGNATURE should be here */ |
87 | u16 version; /* PIRQ_VERSION */ |
88 | u16 size; /* Table size in bytes */ |
89 | u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */ |
90 | u16 exclusive_irqs; /* IRQs devoted exclusively to |
91 | PCI usage */ |
92 | u16 rtr_vendor, rtr_device; /* Vendor and device ID of |
93 | interrupt router */ |
94 | u32 miniport_data; /* Crap */ |
95 | u8 rfu[11]; |
96 | u8 checksum; /* Modulo 256 checksum must give 0 */ |
97 | struct irq_info slots[]; |
98 | } __attribute__((packed)); |
99 | |
100 | struct irt_routing_table { |
101 | u32 signature; /* IRT_SIGNATURE should be here */ |
102 | u8 size; /* Number of entries provided */ |
103 | u8 used; /* Number of entries actually used */ |
104 | u16 exclusive_irqs; /* IRQs devoted exclusively to |
105 | PCI usage */ |
106 | struct irq_info slots[]; |
107 | } __attribute__((packed)); |
108 | |
109 | extern unsigned int pcibios_irq_mask; |
110 | |
111 | extern raw_spinlock_t pci_config_lock; |
112 | |
113 | extern int (*pcibios_enable_irq)(struct pci_dev *dev); |
114 | extern void (*pcibios_disable_irq)(struct pci_dev *dev); |
115 | |
116 | extern bool mp_should_keep_irq(struct device *dev); |
117 | |
118 | struct pci_raw_ops { |
119 | int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn, |
120 | int reg, int len, u32 *val); |
121 | int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn, |
122 | int reg, int len, u32 val); |
123 | }; |
124 | |
125 | extern const struct pci_raw_ops *raw_pci_ops; |
126 | extern const struct pci_raw_ops *raw_pci_ext_ops; |
127 | |
128 | extern const struct pci_raw_ops pci_mmcfg; |
129 | extern const struct pci_raw_ops pci_direct_conf1; |
130 | extern bool port_cf9_safe; |
131 | |
132 | /* arch_initcall level */ |
133 | #ifdef CONFIG_PCI_DIRECT |
134 | extern int pci_direct_probe(void); |
135 | extern void pci_direct_init(int type); |
136 | #else |
137 | static inline int pci_direct_probe(void) { return -1; } |
138 | static inline void pci_direct_init(int type) { } |
139 | #endif |
140 | |
141 | #ifdef CONFIG_PCI_BIOS |
142 | extern void pci_pcbios_init(void); |
143 | #else |
144 | static inline void pci_pcbios_init(void) { } |
145 | #endif |
146 | |
147 | extern void __init dmi_check_pciprobe(void); |
148 | extern void __init dmi_check_skip_isa_align(void); |
149 | |
150 | /* some common used subsys_initcalls */ |
151 | #ifdef CONFIG_PCI |
152 | extern int __init pci_acpi_init(void); |
153 | #else |
154 | static inline int __init pci_acpi_init(void) |
155 | { |
156 | return -EINVAL; |
157 | } |
158 | #endif |
159 | extern void __init pcibios_irq_init(void); |
160 | extern int __init pcibios_init(void); |
161 | extern int pci_legacy_init(void); |
162 | extern void pcibios_fixup_irqs(void); |
163 | |
164 | /* pci-mmconfig.c */ |
165 | |
166 | /* "PCI MMCONFIG %04x [bus %02x-%02x]" */ |
167 | #define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2) |
168 | |
169 | struct pci_mmcfg_region { |
170 | struct list_head list; |
171 | struct resource res; |
172 | u64 address; |
173 | char __iomem *virt; |
174 | u16 segment; |
175 | u8 start_bus; |
176 | u8 end_bus; |
177 | char name[PCI_MMCFG_RESOURCE_NAME_LEN]; |
178 | }; |
179 | |
180 | extern int __init pci_mmcfg_arch_init(void); |
181 | extern void __init pci_mmcfg_arch_free(void); |
182 | extern int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg); |
183 | extern void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg); |
184 | extern int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end, |
185 | phys_addr_t addr); |
186 | extern int pci_mmconfig_delete(u16 seg, u8 start, u8 end); |
187 | extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus); |
188 | extern struct pci_mmcfg_region *__init pci_mmconfig_add(int segment, int start, |
189 | int end, u64 addr); |
190 | |
191 | extern struct list_head pci_mmcfg_list; |
192 | |
193 | #define PCI_MMCFG_BUS_OFFSET(bus) ((bus) << 20) |
194 | |
195 | /* |
196 | * On AMD Fam10h CPUs, all PCI MMIO configuration space accesses must use |
197 | * %eax. No other source or target registers may be used. The following |
198 | * mmio_config_* accessors enforce this. See "BIOS and Kernel Developer's |
199 | * Guide (BKDG) For AMD Family 10h Processors", rev. 3.48, sec 2.11.1, |
200 | * "MMIO Configuration Coding Requirements". |
201 | */ |
202 | static inline unsigned char mmio_config_readb(void __iomem *pos) |
203 | { |
204 | u8 val; |
205 | asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos)); |
206 | return val; |
207 | } |
208 | |
209 | static inline unsigned short mmio_config_readw(void __iomem *pos) |
210 | { |
211 | u16 val; |
212 | asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos)); |
213 | return val; |
214 | } |
215 | |
216 | static inline unsigned int mmio_config_readl(void __iomem *pos) |
217 | { |
218 | u32 val; |
219 | asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos)); |
220 | return val; |
221 | } |
222 | |
223 | static inline void mmio_config_writeb(void __iomem *pos, u8 val) |
224 | { |
225 | asm volatile("movb %%al,(%1)" : : "a" (val), "r" (pos) : "memory" ); |
226 | } |
227 | |
228 | static inline void mmio_config_writew(void __iomem *pos, u16 val) |
229 | { |
230 | asm volatile("movw %%ax,(%1)" : : "a" (val), "r" (pos) : "memory" ); |
231 | } |
232 | |
233 | static inline void mmio_config_writel(void __iomem *pos, u32 val) |
234 | { |
235 | asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) : "memory" ); |
236 | } |
237 | |
238 | #ifdef CONFIG_PCI |
239 | # ifdef CONFIG_ACPI |
240 | # define x86_default_pci_init pci_acpi_init |
241 | # else |
242 | # define x86_default_pci_init pci_legacy_init |
243 | # endif |
244 | # define x86_default_pci_init_irq pcibios_irq_init |
245 | # define x86_default_pci_fixup_irqs pcibios_fixup_irqs |
246 | #else |
247 | # define x86_default_pci_init NULL |
248 | # define x86_default_pci_init_irq NULL |
249 | # define x86_default_pci_fixup_irqs NULL |
250 | #endif |
251 | |
252 | #if defined(CONFIG_PCI) && defined(CONFIG_ACPI) |
253 | extern bool pci_use_e820; |
254 | #else |
255 | #define pci_use_e820 false |
256 | #endif |
257 | |