1 | /* SPDX-License-Identifier: MIT */ |
2 | /****************************************************************************** |
3 | * xen.h |
4 | * |
5 | * Guest OS interface to Xen. |
6 | * |
7 | * Copyright (c) 2004, K A Fraser |
8 | */ |
9 | |
10 | #ifndef __XEN_PUBLIC_XEN_H__ |
11 | #define __XEN_PUBLIC_XEN_H__ |
12 | |
13 | #include <asm/xen/interface.h> |
14 | |
15 | /* |
16 | * XEN "SYSTEM CALLS" (a.k.a. HYPERCALLS). |
17 | */ |
18 | |
19 | /* |
20 | * x86_32: EAX = vector; EBX, ECX, EDX, ESI, EDI = args 1, 2, 3, 4, 5. |
21 | * EAX = return value |
22 | * (argument registers may be clobbered on return) |
23 | * x86_64: RAX = vector; RDI, RSI, RDX, R10, R8, R9 = args 1, 2, 3, 4, 5, 6. |
24 | * RAX = return value |
25 | * (argument registers not clobbered on return; RCX, R11 are) |
26 | */ |
27 | #define __HYPERVISOR_set_trap_table 0 |
28 | #define __HYPERVISOR_mmu_update 1 |
29 | #define __HYPERVISOR_set_gdt 2 |
30 | #define __HYPERVISOR_stack_switch 3 |
31 | #define __HYPERVISOR_set_callbacks 4 |
32 | #define __HYPERVISOR_fpu_taskswitch 5 |
33 | #define __HYPERVISOR_sched_op_compat 6 |
34 | #define __HYPERVISOR_platform_op 7 |
35 | #define __HYPERVISOR_set_debugreg 8 |
36 | #define __HYPERVISOR_get_debugreg 9 |
37 | #define __HYPERVISOR_update_descriptor 10 |
38 | #define __HYPERVISOR_memory_op 12 |
39 | #define __HYPERVISOR_multicall 13 |
40 | #define __HYPERVISOR_update_va_mapping 14 |
41 | #define __HYPERVISOR_set_timer_op 15 |
42 | #define __HYPERVISOR_event_channel_op_compat 16 |
43 | #define __HYPERVISOR_xen_version 17 |
44 | #define __HYPERVISOR_console_io 18 |
45 | #define __HYPERVISOR_physdev_op_compat 19 |
46 | #define __HYPERVISOR_grant_table_op 20 |
47 | #define __HYPERVISOR_vm_assist 21 |
48 | #define __HYPERVISOR_update_va_mapping_otherdomain 22 |
49 | #define __HYPERVISOR_iret 23 /* x86 only */ |
50 | #define __HYPERVISOR_vcpu_op 24 |
51 | #define __HYPERVISOR_set_segment_base 25 /* x86/64 only */ |
52 | #define __HYPERVISOR_mmuext_op 26 |
53 | #define __HYPERVISOR_xsm_op 27 |
54 | #define __HYPERVISOR_nmi_op 28 |
55 | #define __HYPERVISOR_sched_op 29 |
56 | #define __HYPERVISOR_callback_op 30 |
57 | #define __HYPERVISOR_xenoprof_op 31 |
58 | #define __HYPERVISOR_event_channel_op 32 |
59 | #define __HYPERVISOR_physdev_op 33 |
60 | #define __HYPERVISOR_hvm_op 34 |
61 | #define __HYPERVISOR_sysctl 35 |
62 | #define __HYPERVISOR_domctl 36 |
63 | #define __HYPERVISOR_kexec_op 37 |
64 | #define __HYPERVISOR_tmem_op 38 |
65 | #define __HYPERVISOR_xc_reserved_op 39 /* reserved for XenClient */ |
66 | #define __HYPERVISOR_xenpmu_op 40 |
67 | #define __HYPERVISOR_dm_op 41 |
68 | |
69 | /* Architecture-specific hypercall definitions. */ |
70 | #define __HYPERVISOR_arch_0 48 |
71 | #define __HYPERVISOR_arch_1 49 |
72 | #define __HYPERVISOR_arch_2 50 |
73 | #define __HYPERVISOR_arch_3 51 |
74 | #define __HYPERVISOR_arch_4 52 |
75 | #define __HYPERVISOR_arch_5 53 |
76 | #define __HYPERVISOR_arch_6 54 |
77 | #define __HYPERVISOR_arch_7 55 |
78 | |
79 | /* |
80 | * VIRTUAL INTERRUPTS |
81 | * |
82 | * Virtual interrupts that a guest OS may receive from Xen. |
83 | * In the side comments, 'V.' denotes a per-VCPU VIRQ while 'G.' denotes a |
84 | * global VIRQ. The former can be bound once per VCPU and cannot be re-bound. |
85 | * The latter can be allocated only once per guest: they must initially be |
86 | * allocated to VCPU0 but can subsequently be re-bound. |
87 | */ |
88 | #define VIRQ_TIMER 0 /* V. Timebase update, and/or requested timeout. */ |
89 | #define VIRQ_DEBUG 1 /* V. Request guest to dump debug info. */ |
90 | #define VIRQ_CONSOLE 2 /* G. (DOM0) Bytes received on emergency console. */ |
91 | #define VIRQ_DOM_EXC 3 /* G. (DOM0) Exceptional event for some domain. */ |
92 | #define VIRQ_TBUF 4 /* G. (DOM0) Trace buffer has records available. */ |
93 | #define VIRQ_DEBUGGER 6 /* G. (DOM0) A domain has paused for debugging. */ |
94 | #define VIRQ_XENOPROF 7 /* V. XenOprofile interrupt: new sample available */ |
95 | #define VIRQ_CON_RING 8 /* G. (DOM0) Bytes received on console */ |
96 | #define VIRQ_PCPU_STATE 9 /* G. (DOM0) PCPU state changed */ |
97 | #define VIRQ_MEM_EVENT 10 /* G. (DOM0) A memory event has occured */ |
98 | #define VIRQ_XC_RESERVED 11 /* G. Reserved for XenClient */ |
99 | #define VIRQ_ENOMEM 12 /* G. (DOM0) Low on heap memory */ |
100 | #define VIRQ_XENPMU 13 /* PMC interrupt */ |
101 | |
102 | /* Architecture-specific VIRQ definitions. */ |
103 | #define VIRQ_ARCH_0 16 |
104 | #define VIRQ_ARCH_1 17 |
105 | #define VIRQ_ARCH_2 18 |
106 | #define VIRQ_ARCH_3 19 |
107 | #define VIRQ_ARCH_4 20 |
108 | #define VIRQ_ARCH_5 21 |
109 | #define VIRQ_ARCH_6 22 |
110 | #define VIRQ_ARCH_7 23 |
111 | |
112 | #define NR_VIRQS 24 |
113 | |
114 | /* |
115 | * enum neg_errnoval HYPERVISOR_mmu_update(const struct mmu_update reqs[], |
116 | * unsigned count, unsigned *done_out, |
117 | * unsigned foreigndom) |
118 | * @reqs is an array of mmu_update_t structures ((ptr, val) pairs). |
119 | * @count is the length of the above array. |
120 | * @pdone is an output parameter indicating number of completed operations |
121 | * @foreigndom[15:0]: FD, the expected owner of data pages referenced in this |
122 | * hypercall invocation. Can be DOMID_SELF. |
123 | * @foreigndom[31:16]: PFD, the expected owner of pagetable pages referenced |
124 | * in this hypercall invocation. The value of this field |
125 | * (x) encodes the PFD as follows: |
126 | * x == 0 => PFD == DOMID_SELF |
127 | * x != 0 => PFD == x - 1 |
128 | * |
129 | * Sub-commands: ptr[1:0] specifies the appropriate MMU_* command. |
130 | * ------------- |
131 | * ptr[1:0] == MMU_NORMAL_PT_UPDATE: |
132 | * Updates an entry in a page table belonging to PFD. If updating an L1 table, |
133 | * and the new table entry is valid/present, the mapped frame must belong to |
134 | * FD. If attempting to map an I/O page then the caller assumes the privilege |
135 | * of the FD. |
136 | * FD == DOMID_IO: Permit /only/ I/O mappings, at the priv level of the caller. |
137 | * FD == DOMID_XEN: Map restricted areas of Xen's heap space. |
138 | * ptr[:2] -- Machine address of the page-table entry to modify. |
139 | * val -- Value to write. |
140 | * |
141 | * There also certain implicit requirements when using this hypercall. The |
142 | * pages that make up a pagetable must be mapped read-only in the guest. |
143 | * This prevents uncontrolled guest updates to the pagetable. Xen strictly |
144 | * enforces this, and will disallow any pagetable update which will end up |
145 | * mapping pagetable page RW, and will disallow using any writable page as a |
146 | * pagetable. In practice it means that when constructing a page table for a |
147 | * process, thread, etc, we MUST be very dilligient in following these rules: |
148 | * 1). Start with top-level page (PGD or in Xen language: L4). Fill out |
149 | * the entries. |
150 | * 2). Keep on going, filling out the upper (PUD or L3), and middle (PMD |
151 | * or L2). |
152 | * 3). Start filling out the PTE table (L1) with the PTE entries. Once |
153 | * done, make sure to set each of those entries to RO (so writeable bit |
154 | * is unset). Once that has been completed, set the PMD (L2) for this |
155 | * PTE table as RO. |
156 | * 4). When completed with all of the PMD (L2) entries, and all of them have |
157 | * been set to RO, make sure to set RO the PUD (L3). Do the same |
158 | * operation on PGD (L4) pagetable entries that have a PUD (L3) entry. |
159 | * 5). Now before you can use those pages (so setting the cr3), you MUST also |
160 | * pin them so that the hypervisor can verify the entries. This is done |
161 | * via the HYPERVISOR_mmuext_op(MMUEXT_PIN_L4_TABLE, guest physical frame |
162 | * number of the PGD (L4)). And this point the HYPERVISOR_mmuext_op( |
163 | * MMUEXT_NEW_BASEPTR, guest physical frame number of the PGD (L4)) can be |
164 | * issued. |
165 | * For 32-bit guests, the L4 is not used (as there is less pagetables), so |
166 | * instead use L3. |
167 | * At this point the pagetables can be modified using the MMU_NORMAL_PT_UPDATE |
168 | * hypercall. Also if so desired the OS can also try to write to the PTE |
169 | * and be trapped by the hypervisor (as the PTE entry is RO). |
170 | * |
171 | * To deallocate the pages, the operations are the reverse of the steps |
172 | * mentioned above. The argument is MMUEXT_UNPIN_TABLE for all levels and the |
173 | * pagetable MUST not be in use (meaning that the cr3 is not set to it). |
174 | * |
175 | * ptr[1:0] == MMU_MACHPHYS_UPDATE: |
176 | * Updates an entry in the machine->pseudo-physical mapping table. |
177 | * ptr[:2] -- Machine address within the frame whose mapping to modify. |
178 | * The frame must belong to the FD, if one is specified. |
179 | * val -- Value to write into the mapping entry. |
180 | * |
181 | * ptr[1:0] == MMU_PT_UPDATE_PRESERVE_AD: |
182 | * As MMU_NORMAL_PT_UPDATE above, but A/D bits currently in the PTE are ORed |
183 | * with those in @val. |
184 | * |
185 | * @val is usually the machine frame number along with some attributes. |
186 | * The attributes by default follow the architecture defined bits. Meaning that |
187 | * if this is a X86_64 machine and four page table layout is used, the layout |
188 | * of val is: |
189 | * - 63 if set means No execute (NX) |
190 | * - 46-13 the machine frame number |
191 | * - 12 available for guest |
192 | * - 11 available for guest |
193 | * - 10 available for guest |
194 | * - 9 available for guest |
195 | * - 8 global |
196 | * - 7 PAT (PSE is disabled, must use hypercall to make 4MB or 2MB pages) |
197 | * - 6 dirty |
198 | * - 5 accessed |
199 | * - 4 page cached disabled |
200 | * - 3 page write through |
201 | * - 2 userspace accessible |
202 | * - 1 writeable |
203 | * - 0 present |
204 | * |
205 | * The one bits that does not fit with the default layout is the PAGE_PSE |
206 | * also called PAGE_PAT). The MMUEXT_[UN]MARK_SUPER arguments to the |
207 | * HYPERVISOR_mmuext_op serve as mechanism to set a pagetable to be 4MB |
208 | * (or 2MB) instead of using the PAGE_PSE bit. |
209 | * |
210 | * The reason that the PAGE_PSE (bit 7) is not being utilized is due to Xen |
211 | * using it as the Page Attribute Table (PAT) bit - for details on it please |
212 | * refer to Intel SDM 10.12. The PAT allows to set the caching attributes of |
213 | * pages instead of using MTRRs. |
214 | * |
215 | * The PAT MSR is as follows (it is a 64-bit value, each entry is 8 bits): |
216 | * PAT4 PAT0 |
217 | * +-----+-----+----+----+----+-----+----+----+ |
218 | * | UC | UC- | WC | WB | UC | UC- | WC | WB | <= Linux |
219 | * +-----+-----+----+----+----+-----+----+----+ |
220 | * | UC | UC- | WT | WB | UC | UC- | WT | WB | <= BIOS (default when machine boots) |
221 | * +-----+-----+----+----+----+-----+----+----+ |
222 | * | rsv | rsv | WP | WC | UC | UC- | WT | WB | <= Xen |
223 | * +-----+-----+----+----+----+-----+----+----+ |
224 | * |
225 | * The lookup of this index table translates to looking up |
226 | * Bit 7, Bit 4, and Bit 3 of val entry: |
227 | * |
228 | * PAT/PSE (bit 7) ... PCD (bit 4) .. PWT (bit 3). |
229 | * |
230 | * If all bits are off, then we are using PAT0. If bit 3 turned on, |
231 | * then we are using PAT1, if bit 3 and bit 4, then PAT2.. |
232 | * |
233 | * As you can see, the Linux PAT1 translates to PAT4 under Xen. Which means |
234 | * that if a guest that follows Linux's PAT setup and would like to set Write |
235 | * Combined on pages it MUST use PAT4 entry. Meaning that Bit 7 (PAGE_PAT) is |
236 | * set. For example, under Linux it only uses PAT0, PAT1, and PAT2 for the |
237 | * caching as: |
238 | * |
239 | * WB = none (so PAT0) |
240 | * WC = PWT (bit 3 on) |
241 | * UC = PWT | PCD (bit 3 and 4 are on). |
242 | * |
243 | * To make it work with Xen, it needs to translate the WC bit as so: |
244 | * |
245 | * PWT (so bit 3 on) --> PAT (so bit 7 is on) and clear bit 3 |
246 | * |
247 | * And to translate back it would: |
248 | * |
249 | * PAT (bit 7 on) --> PWT (bit 3 on) and clear bit 7. |
250 | */ |
251 | #define MMU_NORMAL_PT_UPDATE 0 /* checked '*ptr = val'. ptr is MA. */ |
252 | #define MMU_MACHPHYS_UPDATE 1 /* ptr = MA of frame to modify entry for */ |
253 | #define MMU_PT_UPDATE_PRESERVE_AD 2 /* atomically: *ptr = val | (*ptr&(A|D)) */ |
254 | #define MMU_PT_UPDATE_NO_TRANSLATE 3 /* checked '*ptr = val'. ptr is MA. */ |
255 | |
256 | /* |
257 | * MMU EXTENDED OPERATIONS |
258 | * |
259 | * enum neg_errnoval HYPERVISOR_mmuext_op(mmuext_op_t uops[], |
260 | * unsigned int count, |
261 | * unsigned int *pdone, |
262 | * unsigned int foreigndom) |
263 | */ |
264 | /* HYPERVISOR_mmuext_op() accepts a list of mmuext_op structures. |
265 | * A foreigndom (FD) can be specified (or DOMID_SELF for none). |
266 | * Where the FD has some effect, it is described below. |
267 | * |
268 | * cmd: MMUEXT_(UN)PIN_*_TABLE |
269 | * mfn: Machine frame number to be (un)pinned as a p.t. page. |
270 | * The frame must belong to the FD, if one is specified. |
271 | * |
272 | * cmd: MMUEXT_NEW_BASEPTR |
273 | * mfn: Machine frame number of new page-table base to install in MMU. |
274 | * |
275 | * cmd: MMUEXT_NEW_USER_BASEPTR [x86/64 only] |
276 | * mfn: Machine frame number of new page-table base to install in MMU |
277 | * when in user space. |
278 | * |
279 | * cmd: MMUEXT_TLB_FLUSH_LOCAL |
280 | * No additional arguments. Flushes local TLB. |
281 | * |
282 | * cmd: MMUEXT_INVLPG_LOCAL |
283 | * linear_addr: Linear address to be flushed from the local TLB. |
284 | * |
285 | * cmd: MMUEXT_TLB_FLUSH_MULTI |
286 | * vcpumask: Pointer to bitmap of VCPUs to be flushed. |
287 | * |
288 | * cmd: MMUEXT_INVLPG_MULTI |
289 | * linear_addr: Linear address to be flushed. |
290 | * vcpumask: Pointer to bitmap of VCPUs to be flushed. |
291 | * |
292 | * cmd: MMUEXT_TLB_FLUSH_ALL |
293 | * No additional arguments. Flushes all VCPUs' TLBs. |
294 | * |
295 | * cmd: MMUEXT_INVLPG_ALL |
296 | * linear_addr: Linear address to be flushed from all VCPUs' TLBs. |
297 | * |
298 | * cmd: MMUEXT_FLUSH_CACHE |
299 | * No additional arguments. Writes back and flushes cache contents. |
300 | * |
301 | * cmd: MMUEXT_FLUSH_CACHE_GLOBAL |
302 | * No additional arguments. Writes back and flushes cache contents |
303 | * on all CPUs in the system. |
304 | * |
305 | * cmd: MMUEXT_SET_LDT |
306 | * linear_addr: Linear address of LDT base (NB. must be page-aligned). |
307 | * nr_ents: Number of entries in LDT. |
308 | * |
309 | * cmd: MMUEXT_CLEAR_PAGE |
310 | * mfn: Machine frame number to be cleared. |
311 | * |
312 | * cmd: MMUEXT_COPY_PAGE |
313 | * mfn: Machine frame number of the destination page. |
314 | * src_mfn: Machine frame number of the source page. |
315 | * |
316 | * cmd: MMUEXT_[UN]MARK_SUPER |
317 | * mfn: Machine frame number of head of superpage to be [un]marked. |
318 | */ |
319 | #define MMUEXT_PIN_L1_TABLE 0 |
320 | #define MMUEXT_PIN_L2_TABLE 1 |
321 | #define MMUEXT_PIN_L3_TABLE 2 |
322 | #define MMUEXT_PIN_L4_TABLE 3 |
323 | #define MMUEXT_UNPIN_TABLE 4 |
324 | #define MMUEXT_NEW_BASEPTR 5 |
325 | #define MMUEXT_TLB_FLUSH_LOCAL 6 |
326 | #define MMUEXT_INVLPG_LOCAL 7 |
327 | #define MMUEXT_TLB_FLUSH_MULTI 8 |
328 | #define MMUEXT_INVLPG_MULTI 9 |
329 | #define MMUEXT_TLB_FLUSH_ALL 10 |
330 | #define MMUEXT_INVLPG_ALL 11 |
331 | #define MMUEXT_FLUSH_CACHE 12 |
332 | #define MMUEXT_SET_LDT 13 |
333 | #define MMUEXT_NEW_USER_BASEPTR 15 |
334 | #define MMUEXT_CLEAR_PAGE 16 |
335 | #define MMUEXT_COPY_PAGE 17 |
336 | #define MMUEXT_FLUSH_CACHE_GLOBAL 18 |
337 | #define MMUEXT_MARK_SUPER 19 |
338 | #define MMUEXT_UNMARK_SUPER 20 |
339 | |
340 | #ifndef __ASSEMBLY__ |
341 | struct mmuext_op { |
342 | unsigned int cmd; |
343 | union { |
344 | /* [UN]PIN_TABLE, NEW_BASEPTR, NEW_USER_BASEPTR |
345 | * CLEAR_PAGE, COPY_PAGE, [UN]MARK_SUPER */ |
346 | xen_pfn_t mfn; |
347 | /* INVLPG_LOCAL, INVLPG_ALL, SET_LDT */ |
348 | unsigned long linear_addr; |
349 | } arg1; |
350 | union { |
351 | /* SET_LDT */ |
352 | unsigned int nr_ents; |
353 | /* TLB_FLUSH_MULTI, INVLPG_MULTI */ |
354 | void *vcpumask; |
355 | /* COPY_PAGE */ |
356 | xen_pfn_t src_mfn; |
357 | } arg2; |
358 | }; |
359 | DEFINE_GUEST_HANDLE_STRUCT(mmuext_op); |
360 | #endif |
361 | |
362 | /* These are passed as 'flags' to update_va_mapping. They can be ORed. */ |
363 | /* When specifying UVMF_MULTI, also OR in a pointer to a CPU bitmap. */ |
364 | /* UVMF_LOCAL is merely UVMF_MULTI with a NULL bitmap pointer. */ |
365 | #define UVMF_NONE (0UL<<0) /* No flushing at all. */ |
366 | #define UVMF_TLB_FLUSH (1UL<<0) /* Flush entire TLB(s). */ |
367 | #define UVMF_INVLPG (2UL<<0) /* Flush only one entry. */ |
368 | #define UVMF_FLUSHTYPE_MASK (3UL<<0) |
369 | #define UVMF_MULTI (0UL<<2) /* Flush subset of TLBs. */ |
370 | #define UVMF_LOCAL (0UL<<2) /* Flush local TLB. */ |
371 | #define UVMF_ALL (1UL<<2) /* Flush all TLBs. */ |
372 | |
373 | /* |
374 | * Commands to HYPERVISOR_console_io(). |
375 | */ |
376 | #define CONSOLEIO_write 0 |
377 | #define CONSOLEIO_read 1 |
378 | |
379 | /* |
380 | * Commands to HYPERVISOR_vm_assist(). |
381 | */ |
382 | #define VMASST_CMD_enable 0 |
383 | #define VMASST_CMD_disable 1 |
384 | |
385 | /* x86/32 guests: simulate full 4GB segment limits. */ |
386 | #define VMASST_TYPE_4gb_segments 0 |
387 | |
388 | /* x86/32 guests: trap (vector 15) whenever above vmassist is used. */ |
389 | #define VMASST_TYPE_4gb_segments_notify 1 |
390 | |
391 | /* |
392 | * x86 guests: support writes to bottom-level PTEs. |
393 | * NB1. Page-directory entries cannot be written. |
394 | * NB2. Guest must continue to remove all writable mappings of PTEs. |
395 | */ |
396 | #define VMASST_TYPE_writable_pagetables 2 |
397 | |
398 | /* x86/PAE guests: support PDPTs above 4GB. */ |
399 | #define VMASST_TYPE_pae_extended_cr3 3 |
400 | |
401 | /* |
402 | * x86 guests: Sane behaviour for virtual iopl |
403 | * - virtual iopl updated from do_iret() hypercalls. |
404 | * - virtual iopl reported in bounce frames. |
405 | * - guest kernels assumed to be level 0 for the purpose of iopl checks. |
406 | */ |
407 | #define VMASST_TYPE_architectural_iopl 4 |
408 | |
409 | /* |
410 | * All guests: activate update indicator in vcpu_runstate_info |
411 | * Enable setting the XEN_RUNSTATE_UPDATE flag in guest memory mapped |
412 | * vcpu_runstate_info during updates of the runstate information. |
413 | */ |
414 | #define VMASST_TYPE_runstate_update_flag 5 |
415 | |
416 | #define MAX_VMASST_TYPE 5 |
417 | |
418 | #ifndef __ASSEMBLY__ |
419 | |
420 | typedef uint16_t domid_t; |
421 | |
422 | /* Domain ids >= DOMID_FIRST_RESERVED cannot be used for ordinary domains. */ |
423 | #define DOMID_FIRST_RESERVED (0x7FF0U) |
424 | |
425 | /* DOMID_SELF is used in certain contexts to refer to oneself. */ |
426 | #define DOMID_SELF (0x7FF0U) |
427 | |
428 | /* |
429 | * DOMID_IO is used to restrict page-table updates to mapping I/O memory. |
430 | * Although no Foreign Domain need be specified to map I/O pages, DOMID_IO |
431 | * is useful to ensure that no mappings to the OS's own heap are accidentally |
432 | * installed. (e.g., in Linux this could cause havoc as reference counts |
433 | * aren't adjusted on the I/O-mapping code path). |
434 | * This only makes sense in MMUEXT_SET_FOREIGNDOM, but in that context can |
435 | * be specified by any calling domain. |
436 | */ |
437 | #define DOMID_IO (0x7FF1U) |
438 | |
439 | /* |
440 | * DOMID_XEN is used to allow privileged domains to map restricted parts of |
441 | * Xen's heap space (e.g., the machine_to_phys table). |
442 | * This only makes sense in MMUEXT_SET_FOREIGNDOM, and is only permitted if |
443 | * the caller is privileged. |
444 | */ |
445 | #define DOMID_XEN (0x7FF2U) |
446 | |
447 | /* DOMID_COW is used as the owner of sharable pages */ |
448 | #define DOMID_COW (0x7FF3U) |
449 | |
450 | /* DOMID_INVALID is used to identify pages with unknown owner. */ |
451 | #define DOMID_INVALID (0x7FF4U) |
452 | |
453 | /* Idle domain. */ |
454 | #define DOMID_IDLE (0x7FFFU) |
455 | |
456 | /* |
457 | * Send an array of these to HYPERVISOR_mmu_update(). |
458 | * NB. The fields are natural pointer/address size for this architecture. |
459 | */ |
460 | struct mmu_update { |
461 | uint64_t ptr; /* Machine address of PTE. */ |
462 | uint64_t val; /* New contents of PTE. */ |
463 | }; |
464 | DEFINE_GUEST_HANDLE_STRUCT(mmu_update); |
465 | |
466 | /* |
467 | * Send an array of these to HYPERVISOR_multicall(). |
468 | * NB. The fields are logically the natural register size for this |
469 | * architecture. In cases where xen_ulong_t is larger than this then |
470 | * any unused bits in the upper portion must be zero. |
471 | */ |
472 | struct multicall_entry { |
473 | xen_ulong_t op; |
474 | xen_long_t result; |
475 | xen_ulong_t args[6]; |
476 | }; |
477 | DEFINE_GUEST_HANDLE_STRUCT(multicall_entry); |
478 | |
479 | struct vcpu_time_info { |
480 | /* |
481 | * Updates to the following values are preceded and followed |
482 | * by an increment of 'version'. The guest can therefore |
483 | * detect updates by looking for changes to 'version'. If the |
484 | * least-significant bit of the version number is set then an |
485 | * update is in progress and the guest must wait to read a |
486 | * consistent set of values. The correct way to interact with |
487 | * the version number is similar to Linux's seqlock: see the |
488 | * implementations of read_seqbegin/read_seqretry. |
489 | */ |
490 | uint32_t version; |
491 | uint32_t pad0; |
492 | uint64_t tsc_timestamp; /* TSC at last update of time vals. */ |
493 | uint64_t system_time; /* Time, in nanosecs, since boot. */ |
494 | /* |
495 | * Current system time: |
496 | * system_time + ((tsc - tsc_timestamp) << tsc_shift) * tsc_to_system_mul |
497 | * CPU frequency (Hz): |
498 | * ((10^9 << 32) / tsc_to_system_mul) >> tsc_shift |
499 | */ |
500 | uint32_t tsc_to_system_mul; |
501 | int8_t tsc_shift; |
502 | int8_t pad1[3]; |
503 | }; /* 32 bytes */ |
504 | |
505 | struct vcpu_info { |
506 | /* |
507 | * 'evtchn_upcall_pending' is written non-zero by Xen to indicate |
508 | * a pending notification for a particular VCPU. It is then cleared |
509 | * by the guest OS /before/ checking for pending work, thus avoiding |
510 | * a set-and-check race. Note that the mask is only accessed by Xen |
511 | * on the CPU that is currently hosting the VCPU. This means that the |
512 | * pending and mask flags can be updated by the guest without special |
513 | * synchronisation (i.e., no need for the x86 LOCK prefix). |
514 | * This may seem suboptimal because if the pending flag is set by |
515 | * a different CPU then an IPI may be scheduled even when the mask |
516 | * is set. However, note: |
517 | * 1. The task of 'interrupt holdoff' is covered by the per-event- |
518 | * channel mask bits. A 'noisy' event that is continually being |
519 | * triggered can be masked at source at this very precise |
520 | * granularity. |
521 | * 2. The main purpose of the per-VCPU mask is therefore to restrict |
522 | * reentrant execution: whether for concurrency control, or to |
523 | * prevent unbounded stack usage. Whatever the purpose, we expect |
524 | * that the mask will be asserted only for short periods at a time, |
525 | * and so the likelihood of a 'spurious' IPI is suitably small. |
526 | * The mask is read before making an event upcall to the guest: a |
527 | * non-zero mask therefore guarantees that the VCPU will not receive |
528 | * an upcall activation. The mask is cleared when the VCPU requests |
529 | * to block: this avoids wakeup-waiting races. |
530 | */ |
531 | uint8_t evtchn_upcall_pending; |
532 | uint8_t evtchn_upcall_mask; |
533 | xen_ulong_t evtchn_pending_sel; |
534 | struct arch_vcpu_info arch; |
535 | struct pvclock_vcpu_time_info time; |
536 | }; /* 64 bytes (x86) */ |
537 | |
538 | /* |
539 | * Xen/kernel shared data -- pointer provided in start_info. |
540 | * NB. We expect that this struct is smaller than a page. |
541 | */ |
542 | struct shared_info { |
543 | struct vcpu_info vcpu_info[MAX_VIRT_CPUS]; |
544 | |
545 | /* |
546 | * A domain can create "event channels" on which it can send and receive |
547 | * asynchronous event notifications. There are three classes of event that |
548 | * are delivered by this mechanism: |
549 | * 1. Bi-directional inter- and intra-domain connections. Domains must |
550 | * arrange out-of-band to set up a connection (usually by allocating |
551 | * an unbound 'listener' port and avertising that via a storage service |
552 | * such as xenstore). |
553 | * 2. Physical interrupts. A domain with suitable hardware-access |
554 | * privileges can bind an event-channel port to a physical interrupt |
555 | * source. |
556 | * 3. Virtual interrupts ('events'). A domain can bind an event-channel |
557 | * port to a virtual interrupt source, such as the virtual-timer |
558 | * device or the emergency console. |
559 | * |
560 | * Event channels are addressed by a "port index". Each channel is |
561 | * associated with two bits of information: |
562 | * 1. PENDING -- notifies the domain that there is a pending notification |
563 | * to be processed. This bit is cleared by the guest. |
564 | * 2. MASK -- if this bit is clear then a 0->1 transition of PENDING |
565 | * will cause an asynchronous upcall to be scheduled. This bit is only |
566 | * updated by the guest. It is read-only within Xen. If a channel |
567 | * becomes pending while the channel is masked then the 'edge' is lost |
568 | * (i.e., when the channel is unmasked, the guest must manually handle |
569 | * pending notifications as no upcall will be scheduled by Xen). |
570 | * |
571 | * To expedite scanning of pending notifications, any 0->1 pending |
572 | * transition on an unmasked channel causes a corresponding bit in a |
573 | * per-vcpu selector word to be set. Each bit in the selector covers a |
574 | * 'C long' in the PENDING bitfield array. |
575 | */ |
576 | xen_ulong_t evtchn_pending[sizeof(xen_ulong_t) * 8]; |
577 | xen_ulong_t evtchn_mask[sizeof(xen_ulong_t) * 8]; |
578 | |
579 | /* |
580 | * Wallclock time: updated only by control software. Guests should base |
581 | * their gettimeofday() syscall on this wallclock-base value. |
582 | */ |
583 | struct pvclock_wall_clock wc; |
584 | #ifndef CONFIG_X86_32 |
585 | uint32_t wc_sec_hi; |
586 | #endif |
587 | struct arch_shared_info arch; |
588 | |
589 | }; |
590 | |
591 | /* |
592 | * Start-of-day memory layout |
593 | * |
594 | * 1. The domain is started within contiguous virtual-memory region. |
595 | * 2. The contiguous region begins and ends on an aligned 4MB boundary. |
596 | * 3. This the order of bootstrap elements in the initial virtual region: |
597 | * a. relocated kernel image |
598 | * b. initial ram disk [mod_start, mod_len] |
599 | * (may be omitted) |
600 | * c. list of allocated page frames [mfn_list, nr_pages] |
601 | * (unless relocated due to XEN_ELFNOTE_INIT_P2M) |
602 | * d. start_info_t structure [register ESI (x86)] |
603 | * in case of dom0 this page contains the console info, too |
604 | * e. unless dom0: xenstore ring page |
605 | * f. unless dom0: console ring page |
606 | * g. bootstrap page tables [pt_base, CR3 (x86)] |
607 | * h. bootstrap stack [register ESP (x86)] |
608 | * 4. Bootstrap elements are packed together, but each is 4kB-aligned. |
609 | * 5. The list of page frames forms a contiguous 'pseudo-physical' memory |
610 | * layout for the domain. In particular, the bootstrap virtual-memory |
611 | * region is a 1:1 mapping to the first section of the pseudo-physical map. |
612 | * 6. All bootstrap elements are mapped read-writable for the guest OS. The |
613 | * only exception is the bootstrap page table, which is mapped read-only. |
614 | * 7. There is guaranteed to be at least 512kB padding after the final |
615 | * bootstrap element. If necessary, the bootstrap virtual region is |
616 | * extended by an extra 4MB to ensure this. |
617 | */ |
618 | |
619 | #define MAX_GUEST_CMDLINE 1024 |
620 | struct start_info { |
621 | /* THE FOLLOWING ARE FILLED IN BOTH ON INITIAL BOOT AND ON RESUME. */ |
622 | char magic[32]; /* "xen-<version>-<platform>". */ |
623 | unsigned long nr_pages; /* Total pages allocated to this domain. */ |
624 | unsigned long shared_info; /* MACHINE address of shared info struct. */ |
625 | uint32_t flags; /* SIF_xxx flags. */ |
626 | xen_pfn_t store_mfn; /* MACHINE page number of shared page. */ |
627 | uint32_t store_evtchn; /* Event channel for store communication. */ |
628 | union { |
629 | struct { |
630 | xen_pfn_t mfn; /* MACHINE page number of console page. */ |
631 | uint32_t evtchn; /* Event channel for console page. */ |
632 | } domU; |
633 | struct { |
634 | uint32_t info_off; /* Offset of console_info struct. */ |
635 | uint32_t info_size; /* Size of console_info struct from start.*/ |
636 | } dom0; |
637 | } console; |
638 | /* THE FOLLOWING ARE ONLY FILLED IN ON INITIAL BOOT (NOT RESUME). */ |
639 | unsigned long pt_base; /* VIRTUAL address of page directory. */ |
640 | unsigned long nr_pt_frames; /* Number of bootstrap p.t. frames. */ |
641 | unsigned long mfn_list; /* VIRTUAL address of page-frame list. */ |
642 | unsigned long mod_start; /* VIRTUAL address of pre-loaded module. */ |
643 | unsigned long mod_len; /* Size (bytes) of pre-loaded module. */ |
644 | int8_t cmd_line[MAX_GUEST_CMDLINE]; |
645 | /* The pfn range here covers both page table and p->m table frames. */ |
646 | unsigned long first_p2m_pfn;/* 1st pfn forming initial P->M table. */ |
647 | unsigned long nr_p2m_frames;/* # of pfns forming initial P->M table. */ |
648 | }; |
649 | |
650 | /* These flags are passed in the 'flags' field of start_info_t. */ |
651 | #define SIF_PRIVILEGED (1<<0) /* Is the domain privileged? */ |
652 | #define SIF_INITDOMAIN (1<<1) /* Is this the initial control domain? */ |
653 | #define SIF_MULTIBOOT_MOD (1<<2) /* Is mod_start a multiboot module? */ |
654 | #define SIF_MOD_START_PFN (1<<3) /* Is mod_start a PFN? */ |
655 | #define SIF_VIRT_P2M_4TOOLS (1<<4) /* Do Xen tools understand a virt. mapped */ |
656 | /* P->M making the 3 level tree obsolete? */ |
657 | #define SIF_PM_MASK (0xFF<<8) /* reserve 1 byte for xen-pm options */ |
658 | |
659 | /* |
660 | * A multiboot module is a package containing modules very similar to a |
661 | * multiboot module array. The only differences are: |
662 | * - the array of module descriptors is by convention simply at the beginning |
663 | * of the multiboot module, |
664 | * - addresses in the module descriptors are based on the beginning of the |
665 | * multiboot module, |
666 | * - the number of modules is determined by a termination descriptor that has |
667 | * mod_start == 0. |
668 | * |
669 | * This permits to both build it statically and reference it in a configuration |
670 | * file, and let the PV guest easily rebase the addresses to virtual addresses |
671 | * and at the same time count the number of modules. |
672 | */ |
673 | struct xen_multiboot_mod_list { |
674 | /* Address of first byte of the module */ |
675 | uint32_t mod_start; |
676 | /* Address of last byte of the module (inclusive) */ |
677 | uint32_t mod_end; |
678 | /* Address of zero-terminated command line */ |
679 | uint32_t cmdline; |
680 | /* Unused, must be zero */ |
681 | uint32_t pad; |
682 | }; |
683 | /* |
684 | * The console structure in start_info.console.dom0 |
685 | * |
686 | * This structure includes a variety of information required to |
687 | * have a working VGA/VESA console. |
688 | */ |
689 | struct dom0_vga_console_info { |
690 | uint8_t video_type; |
691 | #define XEN_VGATYPE_TEXT_MODE_3 0x03 |
692 | #define XEN_VGATYPE_VESA_LFB 0x23 |
693 | #define XEN_VGATYPE_EFI_LFB 0x70 |
694 | |
695 | union { |
696 | struct { |
697 | /* Font height, in pixels. */ |
698 | uint16_t font_height; |
699 | /* Cursor location (column, row). */ |
700 | uint16_t cursor_x, cursor_y; |
701 | /* Number of rows and columns (dimensions in characters). */ |
702 | uint16_t rows, columns; |
703 | } text_mode_3; |
704 | |
705 | struct { |
706 | /* Width and height, in pixels. */ |
707 | uint16_t width, height; |
708 | /* Bytes per scan line. */ |
709 | uint16_t bytes_per_line; |
710 | /* Bits per pixel. */ |
711 | uint16_t bits_per_pixel; |
712 | /* LFB physical address, and size (in units of 64kB). */ |
713 | uint32_t lfb_base; |
714 | uint32_t lfb_size; |
715 | /* RGB mask offsets and sizes, as defined by VBE 1.2+ */ |
716 | uint8_t red_pos, red_size; |
717 | uint8_t green_pos, green_size; |
718 | uint8_t blue_pos, blue_size; |
719 | uint8_t rsvd_pos, rsvd_size; |
720 | |
721 | /* VESA capabilities (offset 0xa, VESA command 0x4f00). */ |
722 | uint32_t gbl_caps; |
723 | /* Mode attributes (offset 0x0, VESA command 0x4f01). */ |
724 | uint16_t mode_attrs; |
725 | uint16_t pad; |
726 | /* high 32 bits of lfb_base */ |
727 | uint32_t ext_lfb_base; |
728 | } vesa_lfb; |
729 | } u; |
730 | }; |
731 | |
732 | typedef uint64_t cpumap_t; |
733 | |
734 | typedef uint8_t xen_domain_handle_t[16]; |
735 | |
736 | /* Turn a plain number into a C unsigned long constant. */ |
737 | #define __mk_unsigned_long(x) x ## UL |
738 | #define mk_unsigned_long(x) __mk_unsigned_long(x) |
739 | |
740 | #define TMEM_SPEC_VERSION 1 |
741 | |
742 | struct tmem_op { |
743 | uint32_t cmd; |
744 | int32_t pool_id; |
745 | union { |
746 | struct { /* for cmd == TMEM_NEW_POOL */ |
747 | uint64_t uuid[2]; |
748 | uint32_t flags; |
749 | } new; |
750 | struct { |
751 | uint64_t oid[3]; |
752 | uint32_t index; |
753 | uint32_t tmem_offset; |
754 | uint32_t pfn_offset; |
755 | uint32_t len; |
756 | GUEST_HANDLE(void) gmfn; /* guest machine page frame */ |
757 | } gen; |
758 | } u; |
759 | }; |
760 | |
761 | DEFINE_GUEST_HANDLE(u64); |
762 | |
763 | #else /* __ASSEMBLY__ */ |
764 | |
765 | /* In assembly code we cannot use C numeric constant suffixes. */ |
766 | #define mk_unsigned_long(x) x |
767 | |
768 | #endif /* !__ASSEMBLY__ */ |
769 | |
770 | #endif /* __XEN_PUBLIC_XEN_H__ */ |
771 | |