1/* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 2002-2023 Free Software Foundation, Inc.
3
4This file is part of GCC.
5
6GCC is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 3, or (at your option)
9any later version.
10
11GCC is distributed in the hope that it will be useful,
12but WITHOUT ANY WARRANTY; without even the implied warranty of
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14GNU General Public License for more details.
15
16You should have received a copy of the GNU General Public License
17along with GCC; see the file COPYING3. If not see
18<http://www.gnu.org/licenses/>. */
19
20/* The x86_64 ABI specifies both XF and TF modes.
21 XFmode is __float80 is IEEE extended; TFmode is __float128
22 is IEEE quad. */
23
24FRACTIONAL_FLOAT_MODE (XF, 80, 12, ieee_extended_intel_96_format);
25FLOAT_MODE (TF, 16, ieee_quad_format);
26FLOAT_MODE (HF, 2, ieee_half_format);
27FLOAT_MODE (BF, 2, 0);
28ADJUST_FLOAT_FORMAT (BF, &arm_bfloat_half_format);
29
30/* In ILP32 mode, XFmode has size 12 and alignment 4.
31 In LP64 mode, XFmode has size and alignment 16. */
32ADJUST_FLOAT_FORMAT (XF, (TARGET_128BIT_LONG_DOUBLE
33 ? &ieee_extended_intel_128_format
34 : TARGET_96_ROUND_53_LONG_DOUBLE
35 ? &ieee_extended_intel_96_round_53_format
36 : &ieee_extended_intel_96_format));
37ADJUST_BYTESIZE (XF, TARGET_128BIT_LONG_DOUBLE ? 16 : 12);
38ADJUST_ALIGNMENT (XF, TARGET_128BIT_LONG_DOUBLE ? 16 : 4);
39
40/* Add any extra modes needed to represent the condition code.
41
42 For the i386, we need separate modes when floating-point
43 equality comparisons are being done.
44
45 Add CCNO to indicate comparisons against zero that require
46 Overflow flag to be unset. Sign bit test is used instead and
47 thus can be used to form "a&b>0" type of tests.
48
49 Add CCGC to indicate comparisons against zero that allow
50 unspecified garbage in the Carry flag. This mode is used
51 by inc/dec instructions.
52
53 Add CCGOC to indicate comparisons against zero that allow
54 unspecified garbage in the Carry and Overflow flag. This
55 mode is used to simulate comparisons of (a-b) and (a+b)
56 against zero using sub/cmp/add operations.
57
58 Add CCGZ to indicate comparisons that allow unspecified garbage
59 in the Zero flag. This mode is used in double-word comparisons.
60
61 Add CCA to indicate that only the Above flag is valid.
62 Add CCC to indicate that only the Carry flag is valid.
63 Add CCO to indicate that only the Overflow flag is valid.
64 Add CCP to indicate that only the Parity flag is valid.
65 Add CCS to indicate that only the Sign flag is valid.
66 Add CCZ to indicate that only the Zero flag is valid. */
67
68CC_MODE (CCGC);
69CC_MODE (CCGOC);
70CC_MODE (CCNO);
71CC_MODE (CCGZ);
72CC_MODE (CCA);
73CC_MODE (CCC);
74CC_MODE (CCO);
75CC_MODE (CCP);
76CC_MODE (CCS);
77CC_MODE (CCZ);
78
79CC_MODE (CCFP);
80
81/* Vector modes. Note that VEC_CONCAT patterns require vector
82 sizes twice as big as implemented in hardware. */
83VECTOR_MODES (INT, 4); /* V4QI V2HI */
84VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */
85VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */
86VECTOR_MODES (INT, 32); /* V32QI V16HI V8SI V4DI */
87VECTOR_MODES (INT, 64); /* V64QI V32HI V16SI V8DI */
88VECTOR_MODES (INT, 128); /* V128QI V64HI V32SI V16DI */
89VECTOR_MODES (FLOAT, 8); /* V4HF V2SF */
90VECTOR_MODES (FLOAT, 16); /* V8HF V4SF V2DF */
91VECTOR_MODES (FLOAT, 32); /* V16HF V8SF V4DF V2TF */
92VECTOR_MODES (FLOAT, 64); /* V32HF V16SF V8DF V4TF */
93VECTOR_MODES (FLOAT, 128); /* V64HF V32SF V16DF V8TF */
94VECTOR_MODES (FLOAT, 256); /* V128HF V64SF V32DF V16TF */
95VECTOR_MODE (FLOAT, HF, 2); /* V2HF */
96VECTOR_MODE (FLOAT, BF, 2); /* V2BF */
97VECTOR_MODE (FLOAT, HF, 6); /* V6HF */
98VECTOR_MODE (INT, TI, 1); /* V1TI */
99VECTOR_MODE (INT, DI, 1); /* V1DI */
100VECTOR_MODE (INT, SI, 1); /* V1SI */
101VECTOR_MODE (INT, QI, 2); /* V2QI */
102VECTOR_MODE (INT, QI, 12); /* V12QI */
103VECTOR_MODE (INT, QI, 14); /* V14QI */
104VECTOR_MODE (INT, HI, 6); /* V6HI */
105VECTOR_MODE (INT, SI, 64); /* V64SI */
106
107INT_MODE (OI, 32);
108INT_MODE (XI, 64);
109
110/* Modes needs a consecutive register pair.
111 Note that Using PARTIAL_INT_MODE but not INT_MODE is to avoid mode promotion
112 issues. */
113PARTIAL_INT_MODE (HI, 16, P2QI);
114PARTIAL_INT_MODE (SI, 32, P2HI);
115
116/* Mode used for signed overflow checking of TImode. For the overflow
117 checking we actually need just 1 or 2 bits beyond TImode precision.
118 Use 160 bits to have a multiple of 32. */
119PARTIAL_INT_MODE (OI, 160, POI);
120
121/* The symbol Pmode stands for one of the above machine modes (usually SImode).
122 The tm.h file specifies which one. It is not a distinct mode. */
123

source code of gcc/config/i386/i386-modes.def