1/* Convert tree expression to rtl instructions, for GNU compiler.
2 Copyright (C) 1988-2017 Free Software Foundation, Inc.
3
4This file is part of GCC.
5
6GCC is free software; you can redistribute it and/or modify it under
7the terms of the GNU General Public License as published by the Free
8Software Foundation; either version 3, or (at your option) any later
9version.
10
11GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12WARRANTY; without even the implied warranty of MERCHANTABILITY or
13FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14for more details.
15
16You should have received a copy of the GNU General Public License
17along with GCC; see the file COPYING3. If not see
18<http://www.gnu.org/licenses/>. */
19
20#include "config.h"
21#include "system.h"
22#include "coretypes.h"
23#include "backend.h"
24#include "target.h"
25#include "rtl.h"
26#include "tree.h"
27#include "gimple.h"
28#include "predict.h"
29#include "memmodel.h"
30#include "tm_p.h"
31#include "ssa.h"
32#include "expmed.h"
33#include "optabs.h"
34#include "regs.h"
35#include "emit-rtl.h"
36#include "recog.h"
37#include "cgraph.h"
38#include "diagnostic.h"
39#include "alias.h"
40#include "fold-const.h"
41#include "stor-layout.h"
42#include "attribs.h"
43#include "varasm.h"
44#include "except.h"
45#include "insn-attr.h"
46#include "dojump.h"
47#include "explow.h"
48#include "calls.h"
49#include "stmt.h"
50/* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
51#include "expr.h"
52#include "optabs-tree.h"
53#include "libfuncs.h"
54#include "reload.h"
55#include "langhooks.h"
56#include "common/common-target.h"
57#include "tree-ssa-live.h"
58#include "tree-outof-ssa.h"
59#include "tree-ssa-address.h"
60#include "builtins.h"
61#include "tree-chkp.h"
62#include "rtl-chkp.h"
63#include "ccmp.h"
64
65
66/* If this is nonzero, we do not bother generating VOLATILE
67 around volatile memory references, and we are willing to
68 output indirect addresses. If cse is to follow, we reject
69 indirect addresses so a useful potential cse is generated;
70 if it is used only once, instruction combination will produce
71 the same indirect address eventually. */
72int cse_not_expected;
73
74static bool block_move_libcall_safe_for_call_parm (void);
75static bool emit_block_move_via_movmem (rtx, rtx, rtx, unsigned, unsigned, HOST_WIDE_INT,
76 unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT,
77 unsigned HOST_WIDE_INT);
78static void emit_block_move_via_loop (rtx, rtx, rtx, unsigned);
79static void clear_by_pieces (rtx, unsigned HOST_WIDE_INT, unsigned int);
80static rtx_insn *compress_float_constant (rtx, rtx);
81static rtx get_subtarget (rtx);
82static void store_constructor_field (rtx, unsigned HOST_WIDE_INT,
83 HOST_WIDE_INT, unsigned HOST_WIDE_INT,
84 unsigned HOST_WIDE_INT, machine_mode,
85 tree, int, alias_set_type, bool);
86static void store_constructor (tree, rtx, int, HOST_WIDE_INT, bool);
87static rtx store_field (rtx, HOST_WIDE_INT, HOST_WIDE_INT,
88 unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT,
89 machine_mode, tree, alias_set_type, bool, bool);
90
91static unsigned HOST_WIDE_INT highest_pow2_factor_for_target (const_tree, const_tree);
92
93static int is_aligning_offset (const_tree, const_tree);
94static rtx reduce_to_bit_field_precision (rtx, rtx, tree);
95static rtx do_store_flag (sepops, rtx, machine_mode);
96#ifdef PUSH_ROUNDING
97static void emit_single_push_insn (machine_mode, rtx, tree);
98#endif
99static void do_tablejump (rtx, machine_mode, rtx, rtx, rtx,
100 profile_probability);
101static rtx const_vector_from_tree (tree);
102static rtx const_scalar_mask_from_tree (scalar_int_mode, tree);
103static tree tree_expr_size (const_tree);
104static HOST_WIDE_INT int_expr_size (tree);
105static void convert_mode_scalar (rtx, rtx, int);
106
107
108/* This is run to set up which modes can be used
109 directly in memory and to initialize the block move optab. It is run
110 at the beginning of compilation and when the target is reinitialized. */
111
112void
113init_expr_target (void)
114{
115 rtx pat;
116 int num_clobbers;
117 rtx mem, mem1;
118 rtx reg;
119
120 /* Try indexing by frame ptr and try by stack ptr.
121 It is known that on the Convex the stack ptr isn't a valid index.
122 With luck, one or the other is valid on any machine. */
123 mem = gen_rtx_MEM (word_mode, stack_pointer_rtx);
124 mem1 = gen_rtx_MEM (word_mode, frame_pointer_rtx);
125
126 /* A scratch register we can modify in-place below to avoid
127 useless RTL allocations. */
128 reg = gen_rtx_REG (word_mode, LAST_VIRTUAL_REGISTER + 1);
129
130 rtx_insn *insn = as_a<rtx_insn *> (rtx_alloc (INSN));
131 pat = gen_rtx_SET (NULL_RTX, NULL_RTX);
132 PATTERN (insn) = pat;
133
134 for (machine_mode mode = VOIDmode; (int) mode < NUM_MACHINE_MODES;
135 mode = (machine_mode) ((int) mode + 1))
136 {
137 int regno;
138
139 direct_load[(int) mode] = direct_store[(int) mode] = 0;
140 PUT_MODE (mem, mode);
141 PUT_MODE (mem1, mode);
142
143 /* See if there is some register that can be used in this mode and
144 directly loaded or stored from memory. */
145
146 if (mode != VOIDmode && mode != BLKmode)
147 for (regno = 0; regno < FIRST_PSEUDO_REGISTER
148 && (direct_load[(int) mode] == 0 || direct_store[(int) mode] == 0);
149 regno++)
150 {
151 if (!targetm.hard_regno_mode_ok (regno, mode))
152 continue;
153
154 set_mode_and_regno (reg, mode, regno);
155
156 SET_SRC (pat) = mem;
157 SET_DEST (pat) = reg;
158 if (recog (pat, insn, &num_clobbers) >= 0)
159 direct_load[(int) mode] = 1;
160
161 SET_SRC (pat) = mem1;
162 SET_DEST (pat) = reg;
163 if (recog (pat, insn, &num_clobbers) >= 0)
164 direct_load[(int) mode] = 1;
165
166 SET_SRC (pat) = reg;
167 SET_DEST (pat) = mem;
168 if (recog (pat, insn, &num_clobbers) >= 0)
169 direct_store[(int) mode] = 1;
170
171 SET_SRC (pat) = reg;
172 SET_DEST (pat) = mem1;
173 if (recog (pat, insn, &num_clobbers) >= 0)
174 direct_store[(int) mode] = 1;
175 }
176 }
177
178 mem = gen_rtx_MEM (VOIDmode, gen_raw_REG (Pmode, LAST_VIRTUAL_REGISTER + 1));
179
180 opt_scalar_float_mode mode_iter;
181 FOR_EACH_MODE_IN_CLASS (mode_iter, MODE_FLOAT)
182 {
183 scalar_float_mode mode = mode_iter.require ();
184 scalar_float_mode srcmode;
185 FOR_EACH_MODE_UNTIL (srcmode, mode)
186 {
187 enum insn_code ic;
188
189 ic = can_extend_p (mode, srcmode, 0);
190 if (ic == CODE_FOR_nothing)
191 continue;
192
193 PUT_MODE (mem, srcmode);
194
195 if (insn_operand_matches (ic, 1, mem))
196 float_extend_from_mem[mode][srcmode] = true;
197 }
198 }
199}
200
201/* This is run at the start of compiling a function. */
202
203void
204init_expr (void)
205{
206 memset (&crtl->expr, 0, sizeof (crtl->expr));
207}
208
209/* Copy data from FROM to TO, where the machine modes are not the same.
210 Both modes may be integer, or both may be floating, or both may be
211 fixed-point.
212 UNSIGNEDP should be nonzero if FROM is an unsigned type.
213 This causes zero-extension instead of sign-extension. */
214
215void
216convert_move (rtx to, rtx from, int unsignedp)
217{
218 machine_mode to_mode = GET_MODE (to);
219 machine_mode from_mode = GET_MODE (from);
220
221 gcc_assert (to_mode != BLKmode);
222 gcc_assert (from_mode != BLKmode);
223
224 /* If the source and destination are already the same, then there's
225 nothing to do. */
226 if (to == from)
227 return;
228
229 /* If FROM is a SUBREG that indicates that we have already done at least
230 the required extension, strip it. We don't handle such SUBREGs as
231 TO here. */
232
233 scalar_int_mode to_int_mode;
234 if (GET_CODE (from) == SUBREG
235 && SUBREG_PROMOTED_VAR_P (from)
236 && is_a <scalar_int_mode> (to_mode, &to_int_mode)
237 && (GET_MODE_PRECISION (subreg_promoted_mode (from))
238 >= GET_MODE_PRECISION (to_int_mode))
239 && SUBREG_CHECK_PROMOTED_SIGN (from, unsignedp))
240 from = gen_lowpart (to_int_mode, from), from_mode = to_int_mode;
241
242 gcc_assert (GET_CODE (to) != SUBREG || !SUBREG_PROMOTED_VAR_P (to));
243
244 if (to_mode == from_mode
245 || (from_mode == VOIDmode && CONSTANT_P (from)))
246 {
247 emit_move_insn (to, from);
248 return;
249 }
250
251 if (VECTOR_MODE_P (to_mode) || VECTOR_MODE_P (from_mode))
252 {
253 gcc_assert (GET_MODE_BITSIZE (from_mode) == GET_MODE_BITSIZE (to_mode));
254
255 if (VECTOR_MODE_P (to_mode))
256 from = simplify_gen_subreg (to_mode, from, GET_MODE (from), 0);
257 else
258 to = simplify_gen_subreg (from_mode, to, GET_MODE (to), 0);
259
260 emit_move_insn (to, from);
261 return;
262 }
263
264 if (GET_CODE (to) == CONCAT && GET_CODE (from) == CONCAT)
265 {
266 convert_move (XEXP (to, 0), XEXP (from, 0), unsignedp);
267 convert_move (XEXP (to, 1), XEXP (from, 1), unsignedp);
268 return;
269 }
270
271 convert_mode_scalar (to, from, unsignedp);
272}
273
274/* Like convert_move, but deals only with scalar modes. */
275
276static void
277convert_mode_scalar (rtx to, rtx from, int unsignedp)
278{
279 /* Both modes should be scalar types. */
280 scalar_mode from_mode = as_a <scalar_mode> (GET_MODE (from));
281 scalar_mode to_mode = as_a <scalar_mode> (GET_MODE (to));
282 bool to_real = SCALAR_FLOAT_MODE_P (to_mode);
283 bool from_real = SCALAR_FLOAT_MODE_P (from_mode);
284 enum insn_code code;
285 rtx libcall;
286
287 gcc_assert (to_real == from_real);
288
289 /* rtx code for making an equivalent value. */
290 enum rtx_code equiv_code = (unsignedp < 0 ? UNKNOWN
291 : (unsignedp ? ZERO_EXTEND : SIGN_EXTEND));
292
293 if (to_real)
294 {
295 rtx value;
296 rtx_insn *insns;
297 convert_optab tab;
298
299 gcc_assert ((GET_MODE_PRECISION (from_mode)
300 != GET_MODE_PRECISION (to_mode))
301 || (DECIMAL_FLOAT_MODE_P (from_mode)
302 != DECIMAL_FLOAT_MODE_P (to_mode)));
303
304 if (GET_MODE_PRECISION (from_mode) == GET_MODE_PRECISION (to_mode))
305 /* Conversion between decimal float and binary float, same size. */
306 tab = DECIMAL_FLOAT_MODE_P (from_mode) ? trunc_optab : sext_optab;
307 else if (GET_MODE_PRECISION (from_mode) < GET_MODE_PRECISION (to_mode))
308 tab = sext_optab;
309 else
310 tab = trunc_optab;
311
312 /* Try converting directly if the insn is supported. */
313
314 code = convert_optab_handler (tab, to_mode, from_mode);
315 if (code != CODE_FOR_nothing)
316 {
317 emit_unop_insn (code, to, from,
318 tab == sext_optab ? FLOAT_EXTEND : FLOAT_TRUNCATE);
319 return;
320 }
321
322 /* Otherwise use a libcall. */
323 libcall = convert_optab_libfunc (tab, to_mode, from_mode);
324
325 /* Is this conversion implemented yet? */
326 gcc_assert (libcall);
327
328 start_sequence ();
329 value = emit_library_call_value (libcall, NULL_RTX, LCT_CONST, to_mode,
330 from, from_mode);
331 insns = get_insns ();
332 end_sequence ();
333 emit_libcall_block (insns, to, value,
334 tab == trunc_optab ? gen_rtx_FLOAT_TRUNCATE (to_mode,
335 from)
336 : gen_rtx_FLOAT_EXTEND (to_mode, from));
337 return;
338 }
339
340 /* Handle pointer conversion. */ /* SPEE 900220. */
341 /* If the target has a converter from FROM_MODE to TO_MODE, use it. */
342 {
343 convert_optab ctab;
344
345 if (GET_MODE_PRECISION (from_mode) > GET_MODE_PRECISION (to_mode))
346 ctab = trunc_optab;
347 else if (unsignedp)
348 ctab = zext_optab;
349 else
350 ctab = sext_optab;
351
352 if (convert_optab_handler (ctab, to_mode, from_mode)
353 != CODE_FOR_nothing)
354 {
355 emit_unop_insn (convert_optab_handler (ctab, to_mode, from_mode),
356 to, from, UNKNOWN);
357 return;
358 }
359 }
360
361 /* Targets are expected to provide conversion insns between PxImode and
362 xImode for all MODE_PARTIAL_INT modes they use, but no others. */
363 if (GET_MODE_CLASS (to_mode) == MODE_PARTIAL_INT)
364 {
365 scalar_int_mode full_mode
366 = smallest_int_mode_for_size (GET_MODE_BITSIZE (to_mode));
367
368 gcc_assert (convert_optab_handler (trunc_optab, to_mode, full_mode)
369 != CODE_FOR_nothing);
370
371 if (full_mode != from_mode)
372 from = convert_to_mode (full_mode, from, unsignedp);
373 emit_unop_insn (convert_optab_handler (trunc_optab, to_mode, full_mode),
374 to, from, UNKNOWN);
375 return;
376 }
377 if (GET_MODE_CLASS (from_mode) == MODE_PARTIAL_INT)
378 {
379 rtx new_from;
380 scalar_int_mode full_mode
381 = smallest_int_mode_for_size (GET_MODE_BITSIZE (from_mode));
382 convert_optab ctab = unsignedp ? zext_optab : sext_optab;
383 enum insn_code icode;
384
385 icode = convert_optab_handler (ctab, full_mode, from_mode);
386 gcc_assert (icode != CODE_FOR_nothing);
387
388 if (to_mode == full_mode)
389 {
390 emit_unop_insn (icode, to, from, UNKNOWN);
391 return;
392 }
393
394 new_from = gen_reg_rtx (full_mode);
395 emit_unop_insn (icode, new_from, from, UNKNOWN);
396
397 /* else proceed to integer conversions below. */
398 from_mode = full_mode;
399 from = new_from;
400 }
401
402 /* Make sure both are fixed-point modes or both are not. */
403 gcc_assert (ALL_SCALAR_FIXED_POINT_MODE_P (from_mode) ==
404 ALL_SCALAR_FIXED_POINT_MODE_P (to_mode));
405 if (ALL_SCALAR_FIXED_POINT_MODE_P (from_mode))
406 {
407 /* If we widen from_mode to to_mode and they are in the same class,
408 we won't saturate the result.
409 Otherwise, always saturate the result to play safe. */
410 if (GET_MODE_CLASS (from_mode) == GET_MODE_CLASS (to_mode)
411 && GET_MODE_SIZE (from_mode) < GET_MODE_SIZE (to_mode))
412 expand_fixed_convert (to, from, 0, 0);
413 else
414 expand_fixed_convert (to, from, 0, 1);
415 return;
416 }
417
418 /* Now both modes are integers. */
419
420 /* Handle expanding beyond a word. */
421 if (GET_MODE_PRECISION (from_mode) < GET_MODE_PRECISION (to_mode)
422 && GET_MODE_PRECISION (to_mode) > BITS_PER_WORD)
423 {
424 rtx_insn *insns;
425 rtx lowpart;
426 rtx fill_value;
427 rtx lowfrom;
428 int i;
429 scalar_mode lowpart_mode;
430 int nwords = CEIL (GET_MODE_SIZE (to_mode), UNITS_PER_WORD);
431
432 /* Try converting directly if the insn is supported. */
433 if ((code = can_extend_p (to_mode, from_mode, unsignedp))
434 != CODE_FOR_nothing)
435 {
436 /* If FROM is a SUBREG, put it into a register. Do this
437 so that we always generate the same set of insns for
438 better cse'ing; if an intermediate assignment occurred,
439 we won't be doing the operation directly on the SUBREG. */
440 if (optimize > 0 && GET_CODE (from) == SUBREG)
441 from = force_reg (from_mode, from);
442 emit_unop_insn (code, to, from, equiv_code);
443 return;
444 }
445 /* Next, try converting via full word. */
446 else if (GET_MODE_PRECISION (from_mode) < BITS_PER_WORD
447 && ((code = can_extend_p (to_mode, word_mode, unsignedp))
448 != CODE_FOR_nothing))
449 {
450 rtx word_to = gen_reg_rtx (word_mode);
451 if (REG_P (to))
452 {
453 if (reg_overlap_mentioned_p (to, from))
454 from = force_reg (from_mode, from);
455 emit_clobber (to);
456 }
457 convert_move (word_to, from, unsignedp);
458 emit_unop_insn (code, to, word_to, equiv_code);
459 return;
460 }
461
462 /* No special multiword conversion insn; do it by hand. */
463 start_sequence ();
464
465 /* Since we will turn this into a no conflict block, we must ensure
466 the source does not overlap the target so force it into an isolated
467 register when maybe so. Likewise for any MEM input, since the
468 conversion sequence might require several references to it and we
469 must ensure we're getting the same value every time. */
470
471 if (MEM_P (from) || reg_overlap_mentioned_p (to, from))
472 from = force_reg (from_mode, from);
473
474 /* Get a copy of FROM widened to a word, if necessary. */
475 if (GET_MODE_PRECISION (from_mode) < BITS_PER_WORD)
476 lowpart_mode = word_mode;
477 else
478 lowpart_mode = from_mode;
479
480 lowfrom = convert_to_mode (lowpart_mode, from, unsignedp);
481
482 lowpart = gen_lowpart (lowpart_mode, to);
483 emit_move_insn (lowpart, lowfrom);
484
485 /* Compute the value to put in each remaining word. */
486 if (unsignedp)
487 fill_value = const0_rtx;
488 else
489 fill_value = emit_store_flag_force (gen_reg_rtx (word_mode),
490 LT, lowfrom, const0_rtx,
491 lowpart_mode, 0, -1);
492
493 /* Fill the remaining words. */
494 for (i = GET_MODE_SIZE (lowpart_mode) / UNITS_PER_WORD; i < nwords; i++)
495 {
496 int index = (WORDS_BIG_ENDIAN ? nwords - i - 1 : i);
497 rtx subword = operand_subword (to, index, 1, to_mode);
498
499 gcc_assert (subword);
500
501 if (fill_value != subword)
502 emit_move_insn (subword, fill_value);
503 }
504
505 insns = get_insns ();
506 end_sequence ();
507
508 emit_insn (insns);
509 return;
510 }
511
512 /* Truncating multi-word to a word or less. */
513 if (GET_MODE_PRECISION (from_mode) > BITS_PER_WORD
514 && GET_MODE_PRECISION (to_mode) <= BITS_PER_WORD)
515 {
516 if (!((MEM_P (from)
517 && ! MEM_VOLATILE_P (from)
518 && direct_load[(int) to_mode]
519 && ! mode_dependent_address_p (XEXP (from, 0),
520 MEM_ADDR_SPACE (from)))
521 || REG_P (from)
522 || GET_CODE (from) == SUBREG))
523 from = force_reg (from_mode, from);
524 convert_move (to, gen_lowpart (word_mode, from), 0);
525 return;
526 }
527
528 /* Now follow all the conversions between integers
529 no more than a word long. */
530
531 /* For truncation, usually we can just refer to FROM in a narrower mode. */
532 if (GET_MODE_BITSIZE (to_mode) < GET_MODE_BITSIZE (from_mode)
533 && TRULY_NOOP_TRUNCATION_MODES_P (to_mode, from_mode))
534 {
535 if (!((MEM_P (from)
536 && ! MEM_VOLATILE_P (from)
537 && direct_load[(int) to_mode]
538 && ! mode_dependent_address_p (XEXP (from, 0),
539 MEM_ADDR_SPACE (from)))
540 || REG_P (from)
541 || GET_CODE (from) == SUBREG))
542 from = force_reg (from_mode, from);
543 if (REG_P (from) && REGNO (from) < FIRST_PSEUDO_REGISTER
544 && !targetm.hard_regno_mode_ok (REGNO (from), to_mode))
545 from = copy_to_reg (from);
546 emit_move_insn (to, gen_lowpart (to_mode, from));
547 return;
548 }
549
550 /* Handle extension. */
551 if (GET_MODE_PRECISION (to_mode) > GET_MODE_PRECISION (from_mode))
552 {
553 /* Convert directly if that works. */
554 if ((code = can_extend_p (to_mode, from_mode, unsignedp))
555 != CODE_FOR_nothing)
556 {
557 emit_unop_insn (code, to, from, equiv_code);
558 return;
559 }
560 else
561 {
562 scalar_mode intermediate;
563 rtx tmp;
564 int shift_amount;
565
566 /* Search for a mode to convert via. */
567 opt_scalar_mode intermediate_iter;
568 FOR_EACH_MODE_FROM (intermediate_iter, from_mode)
569 {
570 scalar_mode intermediate = intermediate_iter.require ();
571 if (((can_extend_p (to_mode, intermediate, unsignedp)
572 != CODE_FOR_nothing)
573 || (GET_MODE_SIZE (to_mode) < GET_MODE_SIZE (intermediate)
574 && TRULY_NOOP_TRUNCATION_MODES_P (to_mode,
575 intermediate)))
576 && (can_extend_p (intermediate, from_mode, unsignedp)
577 != CODE_FOR_nothing))
578 {
579 convert_move (to, convert_to_mode (intermediate, from,
580 unsignedp), unsignedp);
581 return;
582 }
583 }
584
585 /* No suitable intermediate mode.
586 Generate what we need with shifts. */
587 shift_amount = (GET_MODE_PRECISION (to_mode)
588 - GET_MODE_PRECISION (from_mode));
589 from = gen_lowpart (to_mode, force_reg (from_mode, from));
590 tmp = expand_shift (LSHIFT_EXPR, to_mode, from, shift_amount,
591 to, unsignedp);
592 tmp = expand_shift (RSHIFT_EXPR, to_mode, tmp, shift_amount,
593 to, unsignedp);
594 if (tmp != to)
595 emit_move_insn (to, tmp);
596 return;
597 }
598 }
599
600 /* Support special truncate insns for certain modes. */
601 if (convert_optab_handler (trunc_optab, to_mode,
602 from_mode) != CODE_FOR_nothing)
603 {
604 emit_unop_insn (convert_optab_handler (trunc_optab, to_mode, from_mode),
605 to, from, UNKNOWN);
606 return;
607 }
608
609 /* Handle truncation of volatile memrefs, and so on;
610 the things that couldn't be truncated directly,
611 and for which there was no special instruction.
612
613 ??? Code above formerly short-circuited this, for most integer
614 mode pairs, with a force_reg in from_mode followed by a recursive
615 call to this routine. Appears always to have been wrong. */
616 if (GET_MODE_PRECISION (to_mode) < GET_MODE_PRECISION (from_mode))
617 {
618 rtx temp = force_reg (to_mode, gen_lowpart (to_mode, from));
619 emit_move_insn (to, temp);
620 return;
621 }
622
623 /* Mode combination is not recognized. */
624 gcc_unreachable ();
625}
626
627/* Return an rtx for a value that would result
628 from converting X to mode MODE.
629 Both X and MODE may be floating, or both integer.
630 UNSIGNEDP is nonzero if X is an unsigned value.
631 This can be done by referring to a part of X in place
632 or by copying to a new temporary with conversion. */
633
634rtx
635convert_to_mode (machine_mode mode, rtx x, int unsignedp)
636{
637 return convert_modes (mode, VOIDmode, x, unsignedp);
638}
639
640/* Return an rtx for a value that would result
641 from converting X from mode OLDMODE to mode MODE.
642 Both modes may be floating, or both integer.
643 UNSIGNEDP is nonzero if X is an unsigned value.
644
645 This can be done by referring to a part of X in place
646 or by copying to a new temporary with conversion.
647
648 You can give VOIDmode for OLDMODE, if you are sure X has a nonvoid mode. */
649
650rtx
651convert_modes (machine_mode mode, machine_mode oldmode, rtx x, int unsignedp)
652{
653 rtx temp;
654 scalar_int_mode int_mode;
655
656 /* If FROM is a SUBREG that indicates that we have already done at least
657 the required extension, strip it. */
658
659 if (GET_CODE (x) == SUBREG
660 && SUBREG_PROMOTED_VAR_P (x)
661 && is_a <scalar_int_mode> (mode, &int_mode)
662 && (GET_MODE_PRECISION (subreg_promoted_mode (x))
663 >= GET_MODE_PRECISION (int_mode))
664 && SUBREG_CHECK_PROMOTED_SIGN (x, unsignedp))
665 x = gen_lowpart (int_mode, SUBREG_REG (x));
666
667 if (GET_MODE (x) != VOIDmode)
668 oldmode = GET_MODE (x);
669
670 if (mode == oldmode)
671 return x;
672
673 if (CONST_SCALAR_INT_P (x)
674 && is_int_mode (mode, &int_mode))
675 {
676 /* If the caller did not tell us the old mode, then there is not
677 much to do with respect to canonicalization. We have to
678 assume that all the bits are significant. */
679 if (GET_MODE_CLASS (oldmode) != MODE_INT)
680 oldmode = MAX_MODE_INT;
681 wide_int w = wide_int::from (rtx_mode_t (x, oldmode),
682 GET_MODE_PRECISION (int_mode),
683 unsignedp ? UNSIGNED : SIGNED);
684 return immed_wide_int_const (w, int_mode);
685 }
686
687 /* We can do this with a gen_lowpart if both desired and current modes
688 are integer, and this is either a constant integer, a register, or a
689 non-volatile MEM. */
690 scalar_int_mode int_oldmode;
691 if (is_int_mode (mode, &int_mode)
692 && is_int_mode (oldmode, &int_oldmode)
693 && GET_MODE_PRECISION (int_mode) <= GET_MODE_PRECISION (int_oldmode)
694 && ((MEM_P (x) && !MEM_VOLATILE_P (x) && direct_load[(int) int_mode])
695 || (REG_P (x)
696 && (!HARD_REGISTER_P (x)
697 || targetm.hard_regno_mode_ok (REGNO (x), int_mode))
698 && TRULY_NOOP_TRUNCATION_MODES_P (int_mode, GET_MODE (x)))))
699 return gen_lowpart (int_mode, x);
700
701 /* Converting from integer constant into mode is always equivalent to an
702 subreg operation. */
703 if (VECTOR_MODE_P (mode) && GET_MODE (x) == VOIDmode)
704 {
705 gcc_assert (GET_MODE_BITSIZE (mode) == GET_MODE_BITSIZE (oldmode));
706 return simplify_gen_subreg (mode, x, oldmode, 0);
707 }
708
709 temp = gen_reg_rtx (mode);
710 convert_move (temp, x, unsignedp);
711 return temp;
712}
713
714/* Return the largest alignment we can use for doing a move (or store)
715 of MAX_PIECES. ALIGN is the largest alignment we could use. */
716
717static unsigned int
718alignment_for_piecewise_move (unsigned int max_pieces, unsigned int align)
719{
720 scalar_int_mode tmode
721 = int_mode_for_size (max_pieces * BITS_PER_UNIT, 1).require ();
722
723 if (align >= GET_MODE_ALIGNMENT (tmode))
724 align = GET_MODE_ALIGNMENT (tmode);
725 else
726 {
727 scalar_int_mode xmode = NARROWEST_INT_MODE;
728 opt_scalar_int_mode mode_iter;
729 FOR_EACH_MODE_IN_CLASS (mode_iter, MODE_INT)
730 {
731 tmode = mode_iter.require ();
732 if (GET_MODE_SIZE (tmode) > max_pieces
733 || targetm.slow_unaligned_access (tmode, align))
734 break;
735 xmode = tmode;
736 }
737
738 align = MAX (align, GET_MODE_ALIGNMENT (xmode));
739 }
740
741 return align;
742}
743
744/* Return the widest integer mode that is narrower than SIZE bytes. */
745
746static scalar_int_mode
747widest_int_mode_for_size (unsigned int size)
748{
749 scalar_int_mode result = NARROWEST_INT_MODE;
750
751 gcc_checking_assert (size > 1);
752
753 opt_scalar_int_mode tmode;
754 FOR_EACH_MODE_IN_CLASS (tmode, MODE_INT)
755 if (GET_MODE_SIZE (tmode.require ()) < size)
756 result = tmode.require ();
757
758 return result;
759}
760
761/* Determine whether an operation OP on LEN bytes with alignment ALIGN can
762 and should be performed piecewise. */
763
764static bool
765can_do_by_pieces (unsigned HOST_WIDE_INT len, unsigned int align,
766 enum by_pieces_operation op)
767{
768 return targetm.use_by_pieces_infrastructure_p (len, align, op,
769 optimize_insn_for_speed_p ());
770}
771
772/* Determine whether the LEN bytes can be moved by using several move
773 instructions. Return nonzero if a call to move_by_pieces should
774 succeed. */
775
776bool
777can_move_by_pieces (unsigned HOST_WIDE_INT len, unsigned int align)
778{
779 return can_do_by_pieces (len, align, MOVE_BY_PIECES);
780}
781
782/* Return number of insns required to perform operation OP by pieces
783 for L bytes. ALIGN (in bits) is maximum alignment we can assume. */
784
785unsigned HOST_WIDE_INT
786by_pieces_ninsns (unsigned HOST_WIDE_INT l, unsigned int align,
787 unsigned int max_size, by_pieces_operation op)
788{
789 unsigned HOST_WIDE_INT n_insns = 0;
790
791 align = alignment_for_piecewise_move (MOVE_MAX_PIECES, align);
792
793 while (max_size > 1 && l > 0)
794 {
795 scalar_int_mode mode = widest_int_mode_for_size (max_size);
796 enum insn_code icode;
797
798 unsigned int modesize = GET_MODE_SIZE (mode);
799
800 icode = optab_handler (mov_optab, mode);
801 if (icode != CODE_FOR_nothing && align >= GET_MODE_ALIGNMENT (mode))
802 {
803 unsigned HOST_WIDE_INT n_pieces = l / modesize;
804 l %= modesize;
805 switch (op)
806 {
807 default:
808 n_insns += n_pieces;
809 break;
810
811 case COMPARE_BY_PIECES:
812 int batch = targetm.compare_by_pieces_branch_ratio (mode);
813 int batch_ops = 4 * batch - 1;
814 unsigned HOST_WIDE_INT full = n_pieces / batch;
815 n_insns += full * batch_ops;
816 if (n_pieces % batch != 0)
817 n_insns++;
818 break;
819
820 }
821 }
822 max_size = modesize;
823 }
824
825 gcc_assert (!l);
826 return n_insns;
827}
828
829/* Used when performing piecewise block operations, holds information
830 about one of the memory objects involved. The member functions
831 can be used to generate code for loading from the object and
832 updating the address when iterating. */
833
834class pieces_addr
835{
836 /* The object being referenced, a MEM. Can be NULL_RTX to indicate
837 stack pushes. */
838 rtx m_obj;
839 /* The address of the object. Can differ from that seen in the
840 MEM rtx if we copied the address to a register. */
841 rtx m_addr;
842 /* Nonzero if the address on the object has an autoincrement already,
843 signifies whether that was an increment or decrement. */
844 signed char m_addr_inc;
845 /* Nonzero if we intend to use autoinc without the address already
846 having autoinc form. We will insert add insns around each memory
847 reference, expecting later passes to form autoinc addressing modes.
848 The only supported options are predecrement and postincrement. */
849 signed char m_explicit_inc;
850 /* True if we have either of the two possible cases of using
851 autoincrement. */
852 bool m_auto;
853 /* True if this is an address to be used for load operations rather
854 than stores. */
855 bool m_is_load;
856
857 /* Optionally, a function to obtain constants for any given offset into
858 the objects, and data associated with it. */
859 by_pieces_constfn m_constfn;
860 void *m_cfndata;
861public:
862 pieces_addr (rtx, bool, by_pieces_constfn, void *);
863 rtx adjust (scalar_int_mode, HOST_WIDE_INT);
864 void increment_address (HOST_WIDE_INT);
865 void maybe_predec (HOST_WIDE_INT);
866 void maybe_postinc (HOST_WIDE_INT);
867 void decide_autoinc (machine_mode, bool, HOST_WIDE_INT);
868 int get_addr_inc ()
869 {
870 return m_addr_inc;
871 }
872};
873
874/* Initialize a pieces_addr structure from an object OBJ. IS_LOAD is
875 true if the operation to be performed on this object is a load
876 rather than a store. For stores, OBJ can be NULL, in which case we
877 assume the operation is a stack push. For loads, the optional
878 CONSTFN and its associated CFNDATA can be used in place of the
879 memory load. */
880
881pieces_addr::pieces_addr (rtx obj, bool is_load, by_pieces_constfn constfn,
882 void *cfndata)
883 : m_obj (obj), m_is_load (is_load), m_constfn (constfn), m_cfndata (cfndata)
884{
885 m_addr_inc = 0;
886 m_auto = false;
887 if (obj)
888 {
889 rtx addr = XEXP (obj, 0);
890 rtx_code code = GET_CODE (addr);
891 m_addr = addr;
892 bool dec = code == PRE_DEC || code == POST_DEC;
893 bool inc = code == PRE_INC || code == POST_INC;
894 m_auto = inc || dec;
895 if (m_auto)
896 m_addr_inc = dec ? -1 : 1;
897
898 /* While we have always looked for these codes here, the code
899 implementing the memory operation has never handled them.
900 Support could be added later if necessary or beneficial. */
901 gcc_assert (code != PRE_INC && code != POST_DEC);
902 }
903 else
904 {
905 m_addr = NULL_RTX;
906 if (!is_load)
907 {
908 m_auto = true;
909 if (STACK_GROWS_DOWNWARD)
910 m_addr_inc = -1;
911 else
912 m_addr_inc = 1;
913 }
914 else
915 gcc_assert (constfn != NULL);
916 }
917 m_explicit_inc = 0;
918 if (constfn)
919 gcc_assert (is_load);
920}
921
922/* Decide whether to use autoinc for an address involved in a memory op.
923 MODE is the mode of the accesses, REVERSE is true if we've decided to
924 perform the operation starting from the end, and LEN is the length of
925 the operation. Don't override an earlier decision to set m_auto. */
926
927void
928pieces_addr::decide_autoinc (machine_mode ARG_UNUSED (mode), bool reverse,
929 HOST_WIDE_INT len)
930{
931 if (m_auto || m_obj == NULL_RTX)
932 return;
933
934 bool use_predec = (m_is_load
935 ? USE_LOAD_PRE_DECREMENT (mode)
936 : USE_STORE_PRE_DECREMENT (mode));
937 bool use_postinc = (m_is_load
938 ? USE_LOAD_POST_INCREMENT (mode)
939 : USE_STORE_POST_INCREMENT (mode));
940 machine_mode addr_mode = get_address_mode (m_obj);
941
942 if (use_predec && reverse)
943 {
944 m_addr = copy_to_mode_reg (addr_mode,
945 plus_constant (addr_mode,
946 m_addr, len));
947 m_auto = true;
948 m_explicit_inc = -1;
949 }
950 else if (use_postinc && !reverse)
951 {
952 m_addr = copy_to_mode_reg (addr_mode, m_addr);
953 m_auto = true;
954 m_explicit_inc = 1;
955 }
956 else if (CONSTANT_P (m_addr))
957 m_addr = copy_to_mode_reg (addr_mode, m_addr);
958}
959
960/* Adjust the address to refer to the data at OFFSET in MODE. If we
961 are using autoincrement for this address, we don't add the offset,
962 but we still modify the MEM's properties. */
963
964rtx
965pieces_addr::adjust (scalar_int_mode mode, HOST_WIDE_INT offset)
966{
967 if (m_constfn)
968 return m_constfn (m_cfndata, offset, mode);
969 if (m_obj == NULL_RTX)
970 return NULL_RTX;
971 if (m_auto)
972 return adjust_automodify_address (m_obj, mode, m_addr, offset);
973 else
974 return adjust_address (m_obj, mode, offset);
975}
976
977/* Emit an add instruction to increment the address by SIZE. */
978
979void
980pieces_addr::increment_address (HOST_WIDE_INT size)
981{
982 rtx amount = gen_int_mode (size, GET_MODE (m_addr));
983 emit_insn (gen_add2_insn (m_addr, amount));
984}
985
986/* If we are supposed to decrement the address after each access, emit code
987 to do so now. Increment by SIZE (which has should have the correct sign
988 already). */
989
990void
991pieces_addr::maybe_predec (HOST_WIDE_INT size)
992{
993 if (m_explicit_inc >= 0)
994 return;
995 gcc_assert (HAVE_PRE_DECREMENT);
996 increment_address (size);
997}
998
999/* If we are supposed to decrement the address after each access, emit code
1000 to do so now. Increment by SIZE. */
1001
1002void
1003pieces_addr::maybe_postinc (HOST_WIDE_INT size)
1004{
1005 if (m_explicit_inc <= 0)
1006 return;
1007 gcc_assert (HAVE_POST_INCREMENT);
1008 increment_address (size);
1009}
1010
1011/* This structure is used by do_op_by_pieces to describe the operation
1012 to be performed. */
1013
1014class op_by_pieces_d
1015{
1016 protected:
1017 pieces_addr m_to, m_from;
1018 unsigned HOST_WIDE_INT m_len;
1019 HOST_WIDE_INT m_offset;
1020 unsigned int m_align;
1021 unsigned int m_max_size;
1022 bool m_reverse;
1023
1024 /* Virtual functions, overriden by derived classes for the specific
1025 operation. */
1026 virtual void generate (rtx, rtx, machine_mode) = 0;
1027 virtual bool prepare_mode (machine_mode, unsigned int) = 0;
1028 virtual void finish_mode (machine_mode)
1029 {
1030 }
1031
1032 public:
1033 op_by_pieces_d (rtx, bool, rtx, bool, by_pieces_constfn, void *,
1034 unsigned HOST_WIDE_INT, unsigned int);
1035 void run ();
1036};
1037
1038/* The constructor for an op_by_pieces_d structure. We require two
1039 objects named TO and FROM, which are identified as loads or stores
1040 by TO_LOAD and FROM_LOAD. If FROM is a load, the optional FROM_CFN
1041 and its associated FROM_CFN_DATA can be used to replace loads with
1042 constant values. LEN describes the length of the operation. */
1043
1044op_by_pieces_d::op_by_pieces_d (rtx to, bool to_load,
1045 rtx from, bool from_load,
1046 by_pieces_constfn from_cfn,
1047 void *from_cfn_data,
1048 unsigned HOST_WIDE_INT len,
1049 unsigned int align)
1050 : m_to (to, to_load, NULL, NULL),
1051 m_from (from, from_load, from_cfn, from_cfn_data),
1052 m_len (len), m_max_size (MOVE_MAX_PIECES + 1)
1053{
1054 int toi = m_to.get_addr_inc ();
1055 int fromi = m_from.get_addr_inc ();
1056 if (toi >= 0 && fromi >= 0)
1057 m_reverse = false;
1058 else if (toi <= 0 && fromi <= 0)
1059 m_reverse = true;
1060 else
1061 gcc_unreachable ();
1062
1063 m_offset = m_reverse ? len : 0;
1064 align = MIN (to ? MEM_ALIGN (to) : align,
1065 from ? MEM_ALIGN (from) : align);
1066
1067 /* If copying requires more than two move insns,
1068 copy addresses to registers (to make displacements shorter)
1069 and use post-increment if available. */
1070 if (by_pieces_ninsns (len, align, m_max_size, MOVE_BY_PIECES) > 2)
1071 {
1072 /* Find the mode of the largest comparison. */
1073 scalar_int_mode mode = widest_int_mode_for_size (m_max_size);
1074
1075 m_from.decide_autoinc (mode, m_reverse, len);
1076 m_to.decide_autoinc (mode, m_reverse, len);
1077 }
1078
1079 align = alignment_for_piecewise_move (MOVE_MAX_PIECES, align);
1080 m_align = align;
1081}
1082
1083/* This function contains the main loop used for expanding a block
1084 operation. First move what we can in the largest integer mode,
1085 then go to successively smaller modes. For every access, call
1086 GENFUN with the two operands and the EXTRA_DATA. */
1087
1088void
1089op_by_pieces_d::run ()
1090{
1091 while (m_max_size > 1 && m_len > 0)
1092 {
1093 scalar_int_mode mode = widest_int_mode_for_size (m_max_size);
1094
1095 if (prepare_mode (mode, m_align))
1096 {
1097 unsigned int size = GET_MODE_SIZE (mode);
1098 rtx to1 = NULL_RTX, from1;
1099
1100 while (m_len >= size)
1101 {
1102 if (m_reverse)
1103 m_offset -= size;
1104
1105 to1 = m_to.adjust (mode, m_offset);
1106 from1 = m_from.adjust (mode, m_offset);
1107
1108 m_to.maybe_predec (-(HOST_WIDE_INT)size);
1109 m_from.maybe_predec (-(HOST_WIDE_INT)size);
1110
1111 generate (to1, from1, mode);
1112
1113 m_to.maybe_postinc (size);
1114 m_from.maybe_postinc (size);
1115
1116 if (!m_reverse)
1117 m_offset += size;
1118
1119 m_len -= size;
1120 }
1121
1122 finish_mode (mode);
1123 }
1124
1125 m_max_size = GET_MODE_SIZE (mode);
1126 }
1127
1128 /* The code above should have handled everything. */
1129 gcc_assert (!m_len);
1130}
1131
1132/* Derived class from op_by_pieces_d, providing support for block move
1133 operations. */
1134
1135class move_by_pieces_d : public op_by_pieces_d
1136{
1137 insn_gen_fn m_gen_fun;
1138 void generate (rtx, rtx, machine_mode);
1139 bool prepare_mode (machine_mode, unsigned int);
1140
1141 public:
1142 move_by_pieces_d (rtx to, rtx from, unsigned HOST_WIDE_INT len,
1143 unsigned int align)
1144 : op_by_pieces_d (to, false, from, true, NULL, NULL, len, align)
1145 {
1146 }
1147 rtx finish_endp (int);
1148};
1149
1150/* Return true if MODE can be used for a set of copies, given an
1151 alignment ALIGN. Prepare whatever data is necessary for later
1152 calls to generate. */
1153
1154bool
1155move_by_pieces_d::prepare_mode (machine_mode mode, unsigned int align)
1156{
1157 insn_code icode = optab_handler (mov_optab, mode);
1158 m_gen_fun = GEN_FCN (icode);
1159 return icode != CODE_FOR_nothing && align >= GET_MODE_ALIGNMENT (mode);
1160}
1161
1162/* A callback used when iterating for a compare_by_pieces_operation.
1163 OP0 and OP1 are the values that have been loaded and should be
1164 compared in MODE. If OP0 is NULL, this means we should generate a
1165 push; otherwise EXTRA_DATA holds a pointer to a pointer to the insn
1166 gen function that should be used to generate the mode. */
1167
1168void
1169move_by_pieces_d::generate (rtx op0, rtx op1,
1170 machine_mode mode ATTRIBUTE_UNUSED)
1171{
1172#ifdef PUSH_ROUNDING
1173 if (op0 == NULL_RTX)
1174 {
1175 emit_single_push_insn (mode, op1, NULL);
1176 return;
1177 }
1178#endif
1179 emit_insn (m_gen_fun (op0, op1));
1180}
1181
1182/* Perform the final adjustment at the end of a string to obtain the
1183 correct return value for the block operation. If ENDP is 1 return
1184 memory at the end ala mempcpy, and if ENDP is 2 return memory the
1185 end minus one byte ala stpcpy. */
1186
1187rtx
1188move_by_pieces_d::finish_endp (int endp)
1189{
1190 gcc_assert (!m_reverse);
1191 if (endp == 2)
1192 {
1193 m_to.maybe_postinc (-1);
1194 --m_offset;
1195 }
1196 return m_to.adjust (QImode, m_offset);
1197}
1198
1199/* Generate several move instructions to copy LEN bytes from block FROM to
1200 block TO. (These are MEM rtx's with BLKmode).
1201
1202 If PUSH_ROUNDING is defined and TO is NULL, emit_single_push_insn is
1203 used to push FROM to the stack.
1204
1205 ALIGN is maximum stack alignment we can assume.
1206
1207 If ENDP is 0 return to, if ENDP is 1 return memory at the end ala
1208 mempcpy, and if ENDP is 2 return memory the end minus one byte ala
1209 stpcpy. */
1210
1211rtx
1212move_by_pieces (rtx to, rtx from, unsigned HOST_WIDE_INT len,
1213 unsigned int align, int endp)
1214{
1215#ifndef PUSH_ROUNDING
1216 if (to == NULL)
1217 gcc_unreachable ();
1218#endif
1219
1220 move_by_pieces_d data (to, from, len, align);
1221
1222 data.run ();
1223
1224 if (endp)
1225 return data.finish_endp (endp);
1226 else
1227 return to;
1228}
1229
1230/* Derived class from op_by_pieces_d, providing support for block move
1231 operations. */
1232
1233class store_by_pieces_d : public op_by_pieces_d
1234{
1235 insn_gen_fn m_gen_fun;
1236 void generate (rtx, rtx, machine_mode);
1237 bool prepare_mode (machine_mode, unsigned int);
1238
1239 public:
1240 store_by_pieces_d (rtx to, by_pieces_constfn cfn, void *cfn_data,
1241 unsigned HOST_WIDE_INT len, unsigned int align)
1242 : op_by_pieces_d (to, false, NULL_RTX, true, cfn, cfn_data, len, align)
1243 {
1244 }
1245 rtx finish_endp (int);
1246};
1247
1248/* Return true if MODE can be used for a set of stores, given an
1249 alignment ALIGN. Prepare whatever data is necessary for later
1250 calls to generate. */
1251
1252bool
1253store_by_pieces_d::prepare_mode (machine_mode mode, unsigned int align)
1254{
1255 insn_code icode = optab_handler (mov_optab, mode);
1256 m_gen_fun = GEN_FCN (icode);
1257 return icode != CODE_FOR_nothing && align >= GET_MODE_ALIGNMENT (mode);
1258}
1259
1260/* A callback used when iterating for a store_by_pieces_operation.
1261 OP0 and OP1 are the values that have been loaded and should be
1262 compared in MODE. If OP0 is NULL, this means we should generate a
1263 push; otherwise EXTRA_DATA holds a pointer to a pointer to the insn
1264 gen function that should be used to generate the mode. */
1265
1266void
1267store_by_pieces_d::generate (rtx op0, rtx op1, machine_mode)
1268{
1269 emit_insn (m_gen_fun (op0, op1));
1270}
1271
1272/* Perform the final adjustment at the end of a string to obtain the
1273 correct return value for the block operation. If ENDP is 1 return
1274 memory at the end ala mempcpy, and if ENDP is 2 return memory the
1275 end minus one byte ala stpcpy. */
1276
1277rtx
1278store_by_pieces_d::finish_endp (int endp)
1279{
1280 gcc_assert (!m_reverse);
1281 if (endp == 2)
1282 {
1283 m_to.maybe_postinc (-1);
1284 --m_offset;
1285 }
1286 return m_to.adjust (QImode, m_offset);
1287}
1288
1289/* Determine whether the LEN bytes generated by CONSTFUN can be
1290 stored to memory using several move instructions. CONSTFUNDATA is
1291 a pointer which will be passed as argument in every CONSTFUN call.
1292 ALIGN is maximum alignment we can assume. MEMSETP is true if this is
1293 a memset operation and false if it's a copy of a constant string.
1294 Return nonzero if a call to store_by_pieces should succeed. */
1295
1296int
1297can_store_by_pieces (unsigned HOST_WIDE_INT len,
1298 rtx (*constfun) (void *, HOST_WIDE_INT, scalar_int_mode),
1299 void *constfundata, unsigned int align, bool memsetp)
1300{
1301 unsigned HOST_WIDE_INT l;
1302 unsigned int max_size;
1303 HOST_WIDE_INT offset = 0;
1304 enum insn_code icode;
1305 int reverse;
1306 /* cst is set but not used if LEGITIMATE_CONSTANT doesn't use it. */
1307 rtx cst ATTRIBUTE_UNUSED;
1308
1309 if (len == 0)
1310 return 1;
1311
1312 if (!targetm.use_by_pieces_infrastructure_p (len, align,
1313 memsetp
1314 ? SET_BY_PIECES
1315 : STORE_BY_PIECES,
1316 optimize_insn_for_speed_p ()))
1317 return 0;
1318
1319 align = alignment_for_piecewise_move (STORE_MAX_PIECES, align);
1320
1321 /* We would first store what we can in the largest integer mode, then go to
1322 successively smaller modes. */
1323
1324 for (reverse = 0;
1325 reverse <= (HAVE_PRE_DECREMENT || HAVE_POST_DECREMENT);
1326 reverse++)
1327 {
1328 l = len;
1329 max_size = STORE_MAX_PIECES + 1;
1330 while (max_size > 1 && l > 0)
1331 {
1332 scalar_int_mode mode = widest_int_mode_for_size (max_size);
1333
1334 icode = optab_handler (mov_optab, mode);
1335 if (icode != CODE_FOR_nothing
1336 && align >= GET_MODE_ALIGNMENT (mode))
1337 {
1338 unsigned int size = GET_MODE_SIZE (mode);
1339
1340 while (l >= size)
1341 {
1342 if (reverse)
1343 offset -= size;
1344
1345 cst = (*constfun) (constfundata, offset, mode);
1346 if (!targetm.legitimate_constant_p (mode, cst))
1347 return 0;
1348
1349 if (!reverse)
1350 offset += size;
1351
1352 l -= size;
1353 }
1354 }
1355
1356 max_size = GET_MODE_SIZE (mode);
1357 }
1358
1359 /* The code above should have handled everything. */
1360 gcc_assert (!l);
1361 }
1362
1363 return 1;
1364}
1365
1366/* Generate several move instructions to store LEN bytes generated by
1367 CONSTFUN to block TO. (A MEM rtx with BLKmode). CONSTFUNDATA is a
1368 pointer which will be passed as argument in every CONSTFUN call.
1369 ALIGN is maximum alignment we can assume. MEMSETP is true if this is
1370 a memset operation and false if it's a copy of a constant string.
1371 If ENDP is 0 return to, if ENDP is 1 return memory at the end ala
1372 mempcpy, and if ENDP is 2 return memory the end minus one byte ala
1373 stpcpy. */
1374
1375rtx
1376store_by_pieces (rtx to, unsigned HOST_WIDE_INT len,
1377 rtx (*constfun) (void *, HOST_WIDE_INT, scalar_int_mode),
1378 void *constfundata, unsigned int align, bool memsetp, int endp)
1379{
1380 if (len == 0)
1381 {
1382 gcc_assert (endp != 2);
1383 return to;
1384 }
1385
1386 gcc_assert (targetm.use_by_pieces_infrastructure_p
1387 (len, align,
1388 memsetp ? SET_BY_PIECES : STORE_BY_PIECES,
1389 optimize_insn_for_speed_p ()));
1390
1391 store_by_pieces_d data (to, constfun, constfundata, len, align);
1392 data.run ();
1393
1394 if (endp)
1395 return data.finish_endp (endp);
1396 else
1397 return to;
1398}
1399
1400/* Callback routine for clear_by_pieces.
1401 Return const0_rtx unconditionally. */
1402
1403static rtx
1404clear_by_pieces_1 (void *, HOST_WIDE_INT, scalar_int_mode)
1405{
1406 return const0_rtx;
1407}
1408
1409/* Generate several move instructions to clear LEN bytes of block TO. (A MEM
1410 rtx with BLKmode). ALIGN is maximum alignment we can assume. */
1411
1412static void
1413clear_by_pieces (rtx to, unsigned HOST_WIDE_INT len, unsigned int align)
1414{
1415 if (len == 0)
1416 return;
1417
1418 store_by_pieces_d data (to, clear_by_pieces_1, NULL, len, align);
1419 data.run ();
1420}
1421
1422/* Context used by compare_by_pieces_genfn. It stores the fail label
1423 to jump to in case of miscomparison, and for branch ratios greater than 1,
1424 it stores an accumulator and the current and maximum counts before
1425 emitting another branch. */
1426
1427class compare_by_pieces_d : public op_by_pieces_d
1428{
1429 rtx_code_label *m_fail_label;
1430 rtx m_accumulator;
1431 int m_count, m_batch;
1432
1433 void generate (rtx, rtx, machine_mode);
1434 bool prepare_mode (machine_mode, unsigned int);
1435 void finish_mode (machine_mode);
1436 public:
1437 compare_by_pieces_d (rtx op0, rtx op1, by_pieces_constfn op1_cfn,
1438 void *op1_cfn_data, HOST_WIDE_INT len, int align,
1439 rtx_code_label *fail_label)
1440 : op_by_pieces_d (op0, true, op1, true, op1_cfn, op1_cfn_data, len, align)
1441 {
1442 m_fail_label = fail_label;
1443 }
1444};
1445
1446/* A callback used when iterating for a compare_by_pieces_operation.
1447 OP0 and OP1 are the values that have been loaded and should be
1448 compared in MODE. DATA holds a pointer to the compare_by_pieces_data
1449 context structure. */
1450
1451void
1452compare_by_pieces_d::generate (rtx op0, rtx op1, machine_mode mode)
1453{
1454 if (m_batch > 1)
1455 {
1456 rtx temp = expand_binop (mode, sub_optab, op0, op1, NULL_RTX,
1457 true, OPTAB_LIB_WIDEN);
1458 if (m_count != 0)
1459 temp = expand_binop (mode, ior_optab, m_accumulator, temp, temp,
1460 true, OPTAB_LIB_WIDEN);
1461 m_accumulator = temp;
1462
1463 if (++m_count < m_batch)
1464 return;
1465
1466 m_count = 0;
1467 op0 = m_accumulator;
1468 op1 = const0_rtx;
1469 m_accumulator = NULL_RTX;
1470 }
1471 do_compare_rtx_and_jump (op0, op1, NE, true, mode, NULL_RTX, NULL,
1472 m_fail_label, profile_probability::uninitialized ());
1473}
1474
1475/* Return true if MODE can be used for a set of moves and comparisons,
1476 given an alignment ALIGN. Prepare whatever data is necessary for
1477 later calls to generate. */
1478
1479bool
1480compare_by_pieces_d::prepare_mode (machine_mode mode, unsigned int align)
1481{
1482 insn_code icode = optab_handler (mov_optab, mode);
1483 if (icode == CODE_FOR_nothing
1484 || align < GET_MODE_ALIGNMENT (mode)
1485 || !can_compare_p (EQ, mode, ccp_jump))
1486 return false;
1487 m_batch = targetm.compare_by_pieces_branch_ratio (mode);
1488 if (m_batch < 0)
1489 return false;
1490 m_accumulator = NULL_RTX;
1491 m_count = 0;
1492 return true;
1493}
1494
1495/* Called after expanding a series of comparisons in MODE. If we have
1496 accumulated results for which we haven't emitted a branch yet, do
1497 so now. */
1498
1499void
1500compare_by_pieces_d::finish_mode (machine_mode mode)
1501{
1502 if (m_accumulator != NULL_RTX)
1503 do_compare_rtx_and_jump (m_accumulator, const0_rtx, NE, true, mode,
1504 NULL_RTX, NULL, m_fail_label,
1505 profile_probability::uninitialized ());
1506}
1507
1508/* Generate several move instructions to compare LEN bytes from blocks
1509 ARG0 and ARG1. (These are MEM rtx's with BLKmode).
1510
1511 If PUSH_ROUNDING is defined and TO is NULL, emit_single_push_insn is
1512 used to push FROM to the stack.
1513
1514 ALIGN is maximum stack alignment we can assume.
1515
1516 Optionally, the caller can pass a constfn and associated data in A1_CFN
1517 and A1_CFN_DATA. describing that the second operand being compared is a
1518 known constant and how to obtain its data. */
1519
1520static rtx
1521compare_by_pieces (rtx arg0, rtx arg1, unsigned HOST_WIDE_INT len,
1522 rtx target, unsigned int align,
1523 by_pieces_constfn a1_cfn, void *a1_cfn_data)
1524{
1525 rtx_code_label *fail_label = gen_label_rtx ();
1526 rtx_code_label *end_label = gen_label_rtx ();
1527
1528 if (target == NULL_RTX
1529 || !REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
1530 target = gen_reg_rtx (TYPE_MODE (integer_type_node));
1531
1532 compare_by_pieces_d data (arg0, arg1, a1_cfn, a1_cfn_data, len, align,
1533 fail_label);
1534
1535 data.run ();
1536
1537 emit_move_insn (target, const0_rtx);
1538 emit_jump (end_label);
1539 emit_barrier ();
1540 emit_label (fail_label);
1541 emit_move_insn (target, const1_rtx);
1542 emit_label (end_label);
1543
1544 return target;
1545}
1546
1547/* Emit code to move a block Y to a block X. This may be done with
1548 string-move instructions, with multiple scalar move instructions,
1549 or with a library call.
1550
1551 Both X and Y must be MEM rtx's (perhaps inside VOLATILE) with mode BLKmode.
1552 SIZE is an rtx that says how long they are.
1553 ALIGN is the maximum alignment we can assume they have.
1554 METHOD describes what kind of copy this is, and what mechanisms may be used.
1555 MIN_SIZE is the minimal size of block to move
1556 MAX_SIZE is the maximal size of block to move, if it can not be represented
1557 in unsigned HOST_WIDE_INT, than it is mask of all ones.
1558
1559 Return the address of the new block, if memcpy is called and returns it,
1560 0 otherwise. */
1561
1562rtx
1563emit_block_move_hints (rtx x, rtx y, rtx size, enum block_op_methods method,
1564 unsigned int expected_align, HOST_WIDE_INT expected_size,
1565 unsigned HOST_WIDE_INT min_size,
1566 unsigned HOST_WIDE_INT max_size,
1567 unsigned HOST_WIDE_INT probable_max_size)
1568{
1569 bool may_use_call;
1570 rtx retval = 0;
1571 unsigned int align;
1572
1573 gcc_assert (size);
1574 if (CONST_INT_P (size) && INTVAL (size) == 0)
1575 return 0;
1576
1577 switch (method)
1578 {
1579 case BLOCK_OP_NORMAL:
1580 case BLOCK_OP_TAILCALL:
1581 may_use_call = true;
1582 break;
1583
1584 case BLOCK_OP_CALL_PARM:
1585 may_use_call = block_move_libcall_safe_for_call_parm ();
1586
1587 /* Make inhibit_defer_pop nonzero around the library call
1588 to force it to pop the arguments right away. */
1589 NO_DEFER_POP;
1590 break;
1591
1592 case BLOCK_OP_NO_LIBCALL:
1593 may_use_call = false;
1594 break;
1595
1596 default:
1597 gcc_unreachable ();
1598 }
1599
1600 gcc_assert (MEM_P (x) && MEM_P (y));
1601 align = MIN (MEM_ALIGN (x), MEM_ALIGN (y));
1602 gcc_assert (align >= BITS_PER_UNIT);
1603
1604 /* Make sure we've got BLKmode addresses; store_one_arg can decide that
1605 block copy is more efficient for other large modes, e.g. DCmode. */
1606 x = adjust_address (x, BLKmode, 0);
1607 y = adjust_address (y, BLKmode, 0);
1608
1609 /* Set MEM_SIZE as appropriate for this block copy. The main place this
1610 can be incorrect is coming from __builtin_memcpy. */
1611 if (CONST_INT_P (size))
1612 {
1613 x = shallow_copy_rtx (x);
1614 y = shallow_copy_rtx (y);
1615 set_mem_size (x, INTVAL (size));
1616 set_mem_size (y, INTVAL (size));
1617 }
1618
1619 if (CONST_INT_P (size) && can_move_by_pieces (INTVAL (size), align))
1620 move_by_pieces (x, y, INTVAL (size), align, 0);
1621 else if (emit_block_move_via_movmem (x, y, size, align,
1622 expected_align, expected_size,
1623 min_size, max_size, probable_max_size))
1624 ;
1625 else if (may_use_call
1626 && ADDR_SPACE_GENERIC_P (MEM_ADDR_SPACE (x))
1627 && ADDR_SPACE_GENERIC_P (MEM_ADDR_SPACE (y)))
1628 {
1629 /* Since x and y are passed to a libcall, mark the corresponding
1630 tree EXPR as addressable. */
1631 tree y_expr = MEM_EXPR (y);
1632 tree x_expr = MEM_EXPR (x);
1633 if (y_expr)
1634 mark_addressable (y_expr);
1635 if (x_expr)
1636 mark_addressable (x_expr);
1637 retval = emit_block_copy_via_libcall (x, y, size,
1638 method == BLOCK_OP_TAILCALL);
1639 }
1640
1641 else
1642 emit_block_move_via_loop (x, y, size, align);
1643
1644 if (method == BLOCK_OP_CALL_PARM)
1645 OK_DEFER_POP;
1646
1647 return retval;
1648}
1649
1650rtx
1651emit_block_move (rtx x, rtx y, rtx size, enum block_op_methods method)
1652{
1653 unsigned HOST_WIDE_INT max, min = 0;
1654 if (GET_CODE (size) == CONST_INT)
1655 min = max = UINTVAL (size);
1656 else
1657 max = GET_MODE_MASK (GET_MODE (size));
1658 return emit_block_move_hints (x, y, size, method, 0, -1,
1659 min, max, max);
1660}
1661
1662/* A subroutine of emit_block_move. Returns true if calling the
1663 block move libcall will not clobber any parameters which may have
1664 already been placed on the stack. */
1665
1666static bool
1667block_move_libcall_safe_for_call_parm (void)
1668{
1669#if defined (REG_PARM_STACK_SPACE)
1670 tree fn;
1671#endif
1672
1673 /* If arguments are pushed on the stack, then they're safe. */
1674 if (PUSH_ARGS)
1675 return true;
1676
1677 /* If registers go on the stack anyway, any argument is sure to clobber
1678 an outgoing argument. */
1679#if defined (REG_PARM_STACK_SPACE)
1680 fn = builtin_decl_implicit (BUILT_IN_MEMCPY);
1681 /* Avoid set but not used warning if *REG_PARM_STACK_SPACE doesn't
1682 depend on its argument. */
1683 (void) fn;
1684 if (OUTGOING_REG_PARM_STACK_SPACE ((!fn ? NULL_TREE : TREE_TYPE (fn)))
1685 && REG_PARM_STACK_SPACE (fn) != 0)
1686 return false;
1687#endif
1688
1689 /* If any argument goes in memory, then it might clobber an outgoing
1690 argument. */
1691 {
1692 CUMULATIVE_ARGS args_so_far_v;
1693 cumulative_args_t args_so_far;
1694 tree fn, arg;
1695
1696 fn = builtin_decl_implicit (BUILT_IN_MEMCPY);
1697 INIT_CUMULATIVE_ARGS (args_so_far_v, TREE_TYPE (fn), NULL_RTX, 0, 3);
1698 args_so_far = pack_cumulative_args (&args_so_far_v);
1699
1700 arg = TYPE_ARG_TYPES (TREE_TYPE (fn));
1701 for ( ; arg != void_list_node ; arg = TREE_CHAIN (arg))
1702 {
1703 machine_mode mode = TYPE_MODE (TREE_VALUE (arg));
1704 rtx tmp = targetm.calls.function_arg (args_so_far, mode,
1705 NULL_TREE, true);
1706 if (!tmp || !REG_P (tmp))
1707 return false;
1708 if (targetm.calls.arg_partial_bytes (args_so_far, mode, NULL, 1))
1709 return false;
1710 targetm.calls.function_arg_advance (args_so_far, mode,
1711 NULL_TREE, true);
1712 }
1713 }
1714 return true;
1715}
1716
1717/* A subroutine of emit_block_move. Expand a movmem pattern;
1718 return true if successful. */
1719
1720static bool
1721emit_block_move_via_movmem (rtx x, rtx y, rtx size, unsigned int align,
1722 unsigned int expected_align, HOST_WIDE_INT expected_size,
1723 unsigned HOST_WIDE_INT min_size,
1724 unsigned HOST_WIDE_INT max_size,
1725 unsigned HOST_WIDE_INT probable_max_size)
1726{
1727 int save_volatile_ok = volatile_ok;
1728
1729 if (expected_align < align)
1730 expected_align = align;
1731 if (expected_size != -1)
1732 {
1733 if ((unsigned HOST_WIDE_INT)expected_size > probable_max_size)
1734 expected_size = probable_max_size;
1735 if ((unsigned HOST_WIDE_INT)expected_size < min_size)
1736 expected_size = min_size;
1737 }
1738
1739 /* Since this is a move insn, we don't care about volatility. */
1740 volatile_ok = 1;
1741
1742 /* Try the most limited insn first, because there's no point
1743 including more than one in the machine description unless
1744 the more limited one has some advantage. */
1745
1746 opt_scalar_int_mode mode_iter;
1747 FOR_EACH_MODE_IN_CLASS (mode_iter, MODE_INT)
1748 {
1749 scalar_int_mode mode = mode_iter.require ();
1750 enum insn_code code = direct_optab_handler (movmem_optab, mode);
1751
1752 if (code != CODE_FOR_nothing
1753 /* We don't need MODE to be narrower than BITS_PER_HOST_WIDE_INT
1754 here because if SIZE is less than the mode mask, as it is
1755 returned by the macro, it will definitely be less than the
1756 actual mode mask. Since SIZE is within the Pmode address
1757 space, we limit MODE to Pmode. */
1758 && ((CONST_INT_P (size)
1759 && ((unsigned HOST_WIDE_INT) INTVAL (size)
1760 <= (GET_MODE_MASK (mode) >> 1)))
1761 || max_size <= (GET_MODE_MASK (mode) >> 1)
1762 || GET_MODE_BITSIZE (mode) >= GET_MODE_BITSIZE (Pmode)))
1763 {
1764 struct expand_operand ops[9];
1765 unsigned int nops;
1766
1767 /* ??? When called via emit_block_move_for_call, it'd be
1768 nice if there were some way to inform the backend, so
1769 that it doesn't fail the expansion because it thinks
1770 emitting the libcall would be more efficient. */
1771 nops = insn_data[(int) code].n_generator_args;
1772 gcc_assert (nops == 4 || nops == 6 || nops == 8 || nops == 9);
1773
1774 create_fixed_operand (&ops[0], x);
1775 create_fixed_operand (&ops[1], y);
1776 /* The check above guarantees that this size conversion is valid. */
1777 create_convert_operand_to (&ops[2], size, mode, true);
1778 create_integer_operand (&ops[3], align / BITS_PER_UNIT);
1779 if (nops >= 6)
1780 {
1781 create_integer_operand (&ops[4], expected_align / BITS_PER_UNIT);
1782 create_integer_operand (&ops[5], expected_size);
1783 }
1784 if (nops >= 8)
1785 {
1786 create_integer_operand (&ops[6], min_size);
1787 /* If we can not represent the maximal size,
1788 make parameter NULL. */
1789 if ((HOST_WIDE_INT) max_size != -1)
1790 create_integer_operand (&ops[7], max_size);
1791 else
1792 create_fixed_operand (&ops[7], NULL);
1793 }
1794 if (nops == 9)
1795 {
1796 /* If we can not represent the maximal size,
1797 make parameter NULL. */
1798 if ((HOST_WIDE_INT) probable_max_size != -1)
1799 create_integer_operand (&ops[8], probable_max_size);
1800 else
1801 create_fixed_operand (&ops[8], NULL);
1802 }
1803 if (maybe_expand_insn (code, nops, ops))
1804 {
1805 volatile_ok = save_volatile_ok;
1806 return true;
1807 }
1808 }
1809 }
1810
1811 volatile_ok = save_volatile_ok;
1812 return false;
1813}
1814
1815/* A subroutine of emit_block_move. Copy the data via an explicit
1816 loop. This is used only when libcalls are forbidden. */
1817/* ??? It'd be nice to copy in hunks larger than QImode. */
1818
1819static void
1820emit_block_move_via_loop (rtx x, rtx y, rtx size,
1821 unsigned int align ATTRIBUTE_UNUSED)
1822{
1823 rtx_code_label *cmp_label, *top_label;
1824 rtx iter, x_addr, y_addr, tmp;
1825 machine_mode x_addr_mode = get_address_mode (x);
1826 machine_mode y_addr_mode = get_address_mode (y);
1827 machine_mode iter_mode;
1828
1829 iter_mode = GET_MODE (size);
1830 if (iter_mode == VOIDmode)
1831 iter_mode = word_mode;
1832
1833 top_label = gen_label_rtx ();
1834 cmp_label = gen_label_rtx ();
1835 iter = gen_reg_rtx (iter_mode);
1836
1837 emit_move_insn (iter, const0_rtx);
1838
1839 x_addr = force_operand (XEXP (x, 0), NULL_RTX);
1840 y_addr = force_operand (XEXP (y, 0), NULL_RTX);
1841 do_pending_stack_adjust ();
1842
1843 emit_jump (cmp_label);
1844 emit_label (top_label);
1845
1846 tmp = convert_modes (x_addr_mode, iter_mode, iter, true);
1847 x_addr = simplify_gen_binary (PLUS, x_addr_mode, x_addr, tmp);
1848
1849 if (x_addr_mode != y_addr_mode)
1850 tmp = convert_modes (y_addr_mode, iter_mode, iter, true);
1851 y_addr = simplify_gen_binary (PLUS, y_addr_mode, y_addr, tmp);
1852
1853 x = change_address (x, QImode, x_addr);
1854 y = change_address (y, QImode, y_addr);
1855
1856 emit_move_insn (x, y);
1857
1858 tmp = expand_simple_binop (iter_mode, PLUS, iter, const1_rtx, iter,
1859 true, OPTAB_LIB_WIDEN);
1860 if (tmp != iter)
1861 emit_move_insn (iter, tmp);
1862
1863 emit_label (cmp_label);
1864
1865 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
1866 true, top_label,
1867 profile_probability::guessed_always ()
1868 .apply_scale (9, 10));
1869}
1870
1871/* Expand a call to memcpy or memmove or memcmp, and return the result.
1872 TAILCALL is true if this is a tail call. */
1873
1874rtx
1875emit_block_op_via_libcall (enum built_in_function fncode, rtx dst, rtx src,
1876 rtx size, bool tailcall)
1877{
1878 rtx dst_addr, src_addr;
1879 tree call_expr, dst_tree, src_tree, size_tree;
1880 machine_mode size_mode;
1881
1882 dst_addr = copy_addr_to_reg (XEXP (dst, 0));
1883 dst_addr = convert_memory_address (ptr_mode, dst_addr);
1884 dst_tree = make_tree (ptr_type_node, dst_addr);
1885
1886 src_addr = copy_addr_to_reg (XEXP (src, 0));
1887 src_addr = convert_memory_address (ptr_mode, src_addr);
1888 src_tree = make_tree (ptr_type_node, src_addr);
1889
1890 size_mode = TYPE_MODE (sizetype);
1891 size = convert_to_mode (size_mode, size, 1);
1892 size = copy_to_mode_reg (size_mode, size);
1893 size_tree = make_tree (sizetype, size);
1894
1895 /* It is incorrect to use the libcall calling conventions for calls to
1896 memcpy/memmove/memcmp because they can be provided by the user. */
1897 tree fn = builtin_decl_implicit (fncode);
1898 call_expr = build_call_expr (fn, 3, dst_tree, src_tree, size_tree);
1899 CALL_EXPR_TAILCALL (call_expr) = tailcall;
1900
1901 return expand_call (call_expr, NULL_RTX, false);
1902}
1903
1904/* Try to expand cmpstrn or cmpmem operation ICODE with the given operands.
1905 ARG3_TYPE is the type of ARG3_RTX. Return the result rtx on success,
1906 otherwise return null. */
1907
1908rtx
1909expand_cmpstrn_or_cmpmem (insn_code icode, rtx target, rtx arg1_rtx,
1910 rtx arg2_rtx, tree arg3_type, rtx arg3_rtx,
1911 HOST_WIDE_INT align)
1912{
1913 machine_mode insn_mode = insn_data[icode].operand[0].mode;
1914
1915 if (target && (!REG_P (target) || HARD_REGISTER_P (target)))
1916 target = NULL_RTX;
1917
1918 struct expand_operand ops[5];
1919 create_output_operand (&ops[0], target, insn_mode);
1920 create_fixed_operand (&ops[1], arg1_rtx);
1921 create_fixed_operand (&ops[2], arg2_rtx);
1922 create_convert_operand_from (&ops[3], arg3_rtx, TYPE_MODE (arg3_type),
1923 TYPE_UNSIGNED (arg3_type));
1924 create_integer_operand (&ops[4], align);
1925 if (maybe_expand_insn (icode, 5, ops))
1926 return ops[0].value;
1927 return NULL_RTX;
1928}
1929
1930/* Expand a block compare between X and Y with length LEN using the
1931 cmpmem optab, placing the result in TARGET. LEN_TYPE is the type
1932 of the expression that was used to calculate the length. ALIGN
1933 gives the known minimum common alignment. */
1934
1935static rtx
1936emit_block_cmp_via_cmpmem (rtx x, rtx y, rtx len, tree len_type, rtx target,
1937 unsigned align)
1938{
1939 /* Note: The cmpstrnsi pattern, if it exists, is not suitable for
1940 implementing memcmp because it will stop if it encounters two
1941 zero bytes. */
1942 insn_code icode = direct_optab_handler (cmpmem_optab, SImode);
1943
1944 if (icode == CODE_FOR_nothing)
1945 return NULL_RTX;
1946
1947 return expand_cmpstrn_or_cmpmem (icode, target, x, y, len_type, len, align);
1948}
1949
1950/* Emit code to compare a block Y to a block X. This may be done with
1951 string-compare instructions, with multiple scalar instructions,
1952 or with a library call.
1953
1954 Both X and Y must be MEM rtx's. LEN is an rtx that says how long
1955 they are. LEN_TYPE is the type of the expression that was used to
1956 calculate it.
1957
1958 If EQUALITY_ONLY is true, it means we don't have to return the tri-state
1959 value of a normal memcmp call, instead we can just compare for equality.
1960 If FORCE_LIBCALL is true, we should emit a call to memcmp rather than
1961 returning NULL_RTX.
1962
1963 Optionally, the caller can pass a constfn and associated data in Y_CFN
1964 and Y_CFN_DATA. describing that the second operand being compared is a
1965 known constant and how to obtain its data.
1966 Return the result of the comparison, or NULL_RTX if we failed to
1967 perform the operation. */
1968
1969rtx
1970emit_block_cmp_hints (rtx x, rtx y, rtx len, tree len_type, rtx target,
1971 bool equality_only, by_pieces_constfn y_cfn,
1972 void *y_cfndata)
1973{
1974 rtx result = 0;
1975
1976 if (CONST_INT_P (len) && INTVAL (len) == 0)
1977 return const0_rtx;
1978
1979 gcc_assert (MEM_P (x) && MEM_P (y));
1980 unsigned int align = MIN (MEM_ALIGN (x), MEM_ALIGN (y));
1981 gcc_assert (align >= BITS_PER_UNIT);
1982
1983 x = adjust_address (x, BLKmode, 0);
1984 y = adjust_address (y, BLKmode, 0);
1985
1986 if (equality_only
1987 && CONST_INT_P (len)
1988 && can_do_by_pieces (INTVAL (len), align, COMPARE_BY_PIECES))
1989 result = compare_by_pieces (x, y, INTVAL (len), target, align,
1990 y_cfn, y_cfndata);
1991 else
1992 result = emit_block_cmp_via_cmpmem (x, y, len, len_type, target, align);
1993
1994 return result;
1995}
1996
1997/* Copy all or part of a value X into registers starting at REGNO.
1998 The number of registers to be filled is NREGS. */
1999
2000void
2001move_block_to_reg (int regno, rtx x, int nregs, machine_mode mode)
2002{
2003 if (nregs == 0)
2004 return;
2005
2006 if (CONSTANT_P (x) && !targetm.legitimate_constant_p (mode, x))
2007 x = validize_mem (force_const_mem (mode, x));
2008
2009 /* See if the machine can do this with a load multiple insn. */
2010 if (targetm.have_load_multiple ())
2011 {
2012 rtx_insn *last = get_last_insn ();
2013 rtx first = gen_rtx_REG (word_mode, regno);
2014 if (rtx_insn *pat = targetm.gen_load_multiple (first, x,
2015 GEN_INT (nregs)))
2016 {
2017 emit_insn (pat);
2018 return;
2019 }
2020 else
2021 delete_insns_since (last);
2022 }
2023
2024 for (int i = 0; i < nregs; i++)
2025 emit_move_insn (gen_rtx_REG (word_mode, regno + i),
2026 operand_subword_force (x, i, mode));
2027}
2028
2029/* Copy all or part of a BLKmode value X out of registers starting at REGNO.
2030 The number of registers to be filled is NREGS. */
2031
2032void
2033move_block_from_reg (int regno, rtx x, int nregs)
2034{
2035 if (nregs == 0)
2036 return;
2037
2038 /* See if the machine can do this with a store multiple insn. */
2039 if (targetm.have_store_multiple ())
2040 {
2041 rtx_insn *last = get_last_insn ();
2042 rtx first = gen_rtx_REG (word_mode, regno);
2043 if (rtx_insn *pat = targetm.gen_store_multiple (x, first,
2044 GEN_INT (nregs)))
2045 {
2046 emit_insn (pat);
2047 return;
2048 }
2049 else
2050 delete_insns_since (last);
2051 }
2052
2053 for (int i = 0; i < nregs; i++)
2054 {
2055 rtx tem = operand_subword (x, i, 1, BLKmode);
2056
2057 gcc_assert (tem);
2058
2059 emit_move_insn (tem, gen_rtx_REG (word_mode, regno + i));
2060 }
2061}
2062
2063/* Generate a PARALLEL rtx for a new non-consecutive group of registers from
2064 ORIG, where ORIG is a non-consecutive group of registers represented by
2065 a PARALLEL. The clone is identical to the original except in that the
2066 original set of registers is replaced by a new set of pseudo registers.
2067 The new set has the same modes as the original set. */
2068
2069rtx
2070gen_group_rtx (rtx orig)
2071{
2072 int i, length;
2073 rtx *tmps;
2074
2075 gcc_assert (GET_CODE (orig) == PARALLEL);
2076
2077 length = XVECLEN (orig, 0);
2078 tmps = XALLOCAVEC (rtx, length);
2079
2080 /* Skip a NULL entry in first slot. */
2081 i = XEXP (XVECEXP (orig, 0, 0), 0) ? 0 : 1;
2082
2083 if (i)
2084 tmps[0] = 0;
2085
2086 for (; i < length; i++)
2087 {
2088 machine_mode mode = GET_MODE (XEXP (XVECEXP (orig, 0, i), 0));
2089 rtx offset = XEXP (XVECEXP (orig, 0, i), 1);
2090
2091 tmps[i] = gen_rtx_EXPR_LIST (VOIDmode, gen_reg_rtx (mode), offset);
2092 }
2093
2094 return gen_rtx_PARALLEL (GET_MODE (orig), gen_rtvec_v (length, tmps));
2095}
2096
2097/* A subroutine of emit_group_load. Arguments as for emit_group_load,
2098 except that values are placed in TMPS[i], and must later be moved
2099 into corresponding XEXP (XVECEXP (DST, 0, i), 0) element. */
2100
2101static void
2102emit_group_load_1 (rtx *tmps, rtx dst, rtx orig_src, tree type, int ssize)
2103{
2104 rtx src;
2105 int start, i;
2106 machine_mode m = GET_MODE (orig_src);
2107
2108 gcc_assert (GET_CODE (dst) == PARALLEL);
2109
2110 if (m != VOIDmode
2111 && !SCALAR_INT_MODE_P (m)
2112 && !MEM_P (orig_src)
2113 && GET_CODE (orig_src) != CONCAT)
2114 {
2115 scalar_int_mode imode;
2116 if (int_mode_for_mode (GET_MODE (orig_src)).exists (&imode))
2117 {
2118 src = gen_reg_rtx (imode);
2119 emit_move_insn (gen_lowpart (GET_MODE (orig_src), src), orig_src);
2120 }
2121 else
2122 {
2123 src = assign_stack_temp (GET_MODE (orig_src), ssize);
2124 emit_move_insn (src, orig_src);
2125 }
2126 emit_group_load_1 (tmps, dst, src, type, ssize);
2127 return;
2128 }
2129
2130 /* Check for a NULL entry, used to indicate that the parameter goes
2131 both on the stack and in registers. */
2132 if (XEXP (XVECEXP (dst, 0, 0), 0))
2133 start = 0;
2134 else
2135 start = 1;
2136
2137 /* Process the pieces. */
2138 for (i = start; i < XVECLEN (dst, 0); i++)
2139 {
2140 machine_mode mode = GET_MODE (XEXP (XVECEXP (dst, 0, i), 0));
2141 HOST_WIDE_INT bytepos = INTVAL (XEXP (XVECEXP (dst, 0, i), 1));
2142 unsigned int bytelen = GET_MODE_SIZE (mode);
2143 int shift = 0;
2144
2145 /* Handle trailing fragments that run over the size of the struct. */
2146 if (ssize >= 0 && bytepos + (HOST_WIDE_INT) bytelen > ssize)
2147 {
2148 /* Arrange to shift the fragment to where it belongs.
2149 extract_bit_field loads to the lsb of the reg. */
2150 if (
2151#ifdef BLOCK_REG_PADDING
2152 BLOCK_REG_PADDING (GET_MODE (orig_src), type, i == start)
2153 == (BYTES_BIG_ENDIAN ? PAD_UPWARD : PAD_DOWNWARD)
2154#else
2155 BYTES_BIG_ENDIAN
2156#endif
2157 )
2158 shift = (bytelen - (ssize - bytepos)) * BITS_PER_UNIT;
2159 bytelen = ssize - bytepos;
2160 gcc_assert (bytelen > 0);
2161 }
2162
2163 /* If we won't be loading directly from memory, protect the real source
2164 from strange tricks we might play; but make sure that the source can
2165 be loaded directly into the destination. */
2166 src = orig_src;
2167 if (!MEM_P (orig_src)
2168 && (!CONSTANT_P (orig_src)
2169 || (GET_MODE (orig_src) != mode
2170 && GET_MODE (orig_src) != VOIDmode)))
2171 {
2172 if (GET_MODE (orig_src) == VOIDmode)
2173 src = gen_reg_rtx (mode);
2174 else
2175 src = gen_reg_rtx (GET_MODE (orig_src));
2176
2177 emit_move_insn (src, orig_src);
2178 }
2179
2180 /* Optimize the access just a bit. */
2181 if (MEM_P (src)
2182 && (! targetm.slow_unaligned_access (mode, MEM_ALIGN (src))
2183 || MEM_ALIGN (src) >= GET_MODE_ALIGNMENT (mode))
2184 && bytepos * BITS_PER_UNIT % GET_MODE_ALIGNMENT (mode) == 0
2185 && bytelen == GET_MODE_SIZE (mode))
2186 {
2187 tmps[i] = gen_reg_rtx (mode);
2188 emit_move_insn (tmps[i], adjust_address (src, mode, bytepos));
2189 }
2190 else if (COMPLEX_MODE_P (mode)
2191 && GET_MODE (src) == mode
2192 && bytelen == GET_MODE_SIZE (mode))
2193 /* Let emit_move_complex do the bulk of the work. */
2194 tmps[i] = src;
2195 else if (GET_CODE (src) == CONCAT)
2196 {
2197 unsigned int slen = GET_MODE_SIZE (GET_MODE (src));
2198 unsigned int slen0 = GET_MODE_SIZE (GET_MODE (XEXP (src, 0)));
2199 unsigned int elt = bytepos / slen0;
2200 unsigned int subpos = bytepos % slen0;
2201
2202 if (subpos + bytelen <= slen0)
2203 {
2204 /* The following assumes that the concatenated objects all
2205 have the same size. In this case, a simple calculation
2206 can be used to determine the object and the bit field
2207 to be extracted. */
2208 tmps[i] = XEXP (src, elt);
2209 if (subpos != 0
2210 || subpos + bytelen != slen0
2211 || (!CONSTANT_P (tmps[i])
2212 && (!REG_P (tmps[i]) || GET_MODE (tmps[i]) != mode)))
2213 tmps[i] = extract_bit_field (tmps[i], bytelen * BITS_PER_UNIT,
2214 subpos * BITS_PER_UNIT,
2215 1, NULL_RTX, mode, mode, false,
2216 NULL);
2217 }
2218 else
2219 {
2220 rtx mem;
2221
2222 gcc_assert (!bytepos);
2223 mem = assign_stack_temp (GET_MODE (src), slen);
2224 emit_move_insn (mem, src);
2225 tmps[i] = extract_bit_field (mem, bytelen * BITS_PER_UNIT,
2226 0, 1, NULL_RTX, mode, mode, false,
2227 NULL);
2228 }
2229 }
2230 /* FIXME: A SIMD parallel will eventually lead to a subreg of a
2231 SIMD register, which is currently broken. While we get GCC
2232 to emit proper RTL for these cases, let's dump to memory. */
2233 else if (VECTOR_MODE_P (GET_MODE (dst))
2234 && REG_P (src))
2235 {
2236 int slen = GET_MODE_SIZE (GET_MODE (src));
2237 rtx mem;
2238
2239 mem = assign_stack_temp (GET_MODE (src), slen);
2240 emit_move_insn (mem, src);
2241 tmps[i] = adjust_address (mem, mode, (int) bytepos);
2242 }
2243 else if (CONSTANT_P (src) && GET_MODE (dst) != BLKmode
2244 && XVECLEN (dst, 0) > 1)
2245 tmps[i] = simplify_gen_subreg (mode, src, GET_MODE (dst), bytepos);
2246 else if (CONSTANT_P (src))
2247 {
2248 HOST_WIDE_INT len = (HOST_WIDE_INT) bytelen;
2249
2250 if (len == ssize)
2251 tmps[i] = src;
2252 else
2253 {
2254 rtx first, second;
2255
2256 /* TODO: const_wide_int can have sizes other than this... */
2257 gcc_assert (2 * len == ssize);
2258 split_double (src, &first, &second);
2259 if (i)
2260 tmps[i] = second;
2261 else
2262 tmps[i] = first;
2263 }
2264 }
2265 else if (REG_P (src) && GET_MODE (src) == mode)
2266 tmps[i] = src;
2267 else
2268 tmps[i] = extract_bit_field (src, bytelen * BITS_PER_UNIT,
2269 bytepos * BITS_PER_UNIT, 1, NULL_RTX,
2270 mode, mode, false, NULL);
2271
2272 if (shift)
2273 tmps[i] = expand_shift (LSHIFT_EXPR, mode, tmps[i],
2274 shift, tmps[i], 0);
2275 }
2276}
2277
2278/* Emit code to move a block SRC of type TYPE to a block DST,
2279 where DST is non-consecutive registers represented by a PARALLEL.
2280 SSIZE represents the total size of block ORIG_SRC in bytes, or -1
2281 if not known. */
2282
2283void
2284emit_group_load (rtx dst, rtx src, tree type, int ssize)
2285{
2286 rtx *tmps;
2287 int i;
2288
2289 tmps = XALLOCAVEC (rtx, XVECLEN (dst, 0));
2290 emit_group_load_1 (tmps, dst, src, type, ssize);
2291
2292 /* Copy the extracted pieces into the proper (probable) hard regs. */
2293 for (i = 0; i < XVECLEN (dst, 0); i++)
2294 {
2295 rtx d = XEXP (XVECEXP (dst, 0, i), 0);
2296 if (d == NULL)
2297 continue;
2298 emit_move_insn (d, tmps[i]);
2299 }
2300}
2301
2302/* Similar, but load SRC into new pseudos in a format that looks like
2303 PARALLEL. This can later be fed to emit_group_move to get things
2304 in the right place. */
2305
2306rtx
2307emit_group_load_into_temps (rtx parallel, rtx src, tree type, int ssize)
2308{
2309 rtvec vec;
2310 int i;
2311
2312 vec = rtvec_alloc (XVECLEN (parallel, 0));
2313 emit_group_load_1 (&RTVEC_ELT (vec, 0), parallel, src, type, ssize);
2314
2315 /* Convert the vector to look just like the original PARALLEL, except
2316 with the computed values. */
2317 for (i = 0; i < XVECLEN (parallel, 0); i++)
2318 {
2319 rtx e = XVECEXP (parallel, 0, i);
2320 rtx d = XEXP (e, 0);
2321
2322 if (d)
2323 {
2324 d = force_reg (GET_MODE (d), RTVEC_ELT (vec, i));
2325 e = alloc_EXPR_LIST (REG_NOTE_KIND (e), d, XEXP (e, 1));
2326 }
2327 RTVEC_ELT (vec, i) = e;
2328 }
2329
2330 return gen_rtx_PARALLEL (GET_MODE (parallel), vec);
2331}
2332
2333/* Emit code to move a block SRC to block DST, where SRC and DST are
2334 non-consecutive groups of registers, each represented by a PARALLEL. */
2335
2336void
2337emit_group_move (rtx dst, rtx src)
2338{
2339 int i;
2340
2341 gcc_assert (GET_CODE (src) == PARALLEL
2342 && GET_CODE (dst) == PARALLEL
2343 && XVECLEN (src, 0) == XVECLEN (dst, 0));
2344
2345 /* Skip first entry if NULL. */
2346 for (i = XEXP (XVECEXP (src, 0, 0), 0) ? 0 : 1; i < XVECLEN (src, 0); i++)
2347 emit_move_insn (XEXP (XVECEXP (dst, 0, i), 0),
2348 XEXP (XVECEXP (src, 0, i), 0));
2349}
2350
2351/* Move a group of registers represented by a PARALLEL into pseudos. */
2352
2353rtx
2354emit_group_move_into_temps (rtx src)
2355{
2356 rtvec vec = rtvec_alloc (XVECLEN (src, 0));
2357 int i;
2358
2359 for (i = 0; i < XVECLEN (src, 0); i++)
2360 {
2361 rtx e = XVECEXP (src, 0, i);
2362 rtx d = XEXP (e, 0);
2363
2364 if (d)
2365 e = alloc_EXPR_LIST (REG_NOTE_KIND (e), copy_to_reg (d), XEXP (e, 1));
2366 RTVEC_ELT (vec, i) = e;
2367 }
2368
2369 return gen_rtx_PARALLEL (GET_MODE (src), vec);
2370}
2371
2372/* Emit code to move a block SRC to a block ORIG_DST of type TYPE,
2373 where SRC is non-consecutive registers represented by a PARALLEL.
2374 SSIZE represents the total size of block ORIG_DST, or -1 if not
2375 known. */
2376
2377void
2378emit_group_store (rtx orig_dst, rtx src, tree type ATTRIBUTE_UNUSED, int ssize)
2379{
2380 rtx *tmps, dst;
2381 int start, finish, i;
2382 machine_mode m = GET_MODE (orig_dst);
2383
2384 gcc_assert (GET_CODE (src) == PARALLEL);
2385
2386 if (!SCALAR_INT_MODE_P (m)
2387 && !MEM_P (orig_dst) && GET_CODE (orig_dst) != CONCAT)
2388 {
2389 scalar_int_mode imode;
2390 if (int_mode_for_mode (GET_MODE (orig_dst)).exists (&imode))
2391 {
2392 dst = gen_reg_rtx (imode);
2393 emit_group_store (dst, src, type, ssize);
2394 dst = gen_lowpart (GET_MODE (orig_dst), dst);
2395 }
2396 else
2397 {
2398 dst = assign_stack_temp (GET_MODE (orig_dst), ssize);
2399 emit_group_store (dst, src, type, ssize);
2400 }
2401 emit_move_insn (orig_dst, dst);
2402 return;
2403 }
2404
2405 /* Check for a NULL entry, used to indicate that the parameter goes
2406 both on the stack and in registers. */
2407 if (XEXP (XVECEXP (src, 0, 0), 0))
2408 start = 0;
2409 else
2410 start = 1;
2411 finish = XVECLEN (src, 0);
2412
2413 tmps = XALLOCAVEC (rtx, finish);
2414
2415 /* Copy the (probable) hard regs into pseudos. */
2416 for (i = start; i < finish; i++)
2417 {
2418 rtx reg = XEXP (XVECEXP (src, 0, i), 0);
2419 if (!REG_P (reg) || REGNO (reg) < FIRST_PSEUDO_REGISTER)
2420 {
2421 tmps[i] = gen_reg_rtx (GET_MODE (reg));
2422 emit_move_insn (tmps[i], reg);
2423 }
2424 else
2425 tmps[i] = reg;
2426 }
2427
2428 /* If we won't be storing directly into memory, protect the real destination
2429 from strange tricks we might play. */
2430 dst = orig_dst;
2431 if (GET_CODE (dst) == PARALLEL)
2432 {
2433 rtx temp;
2434
2435 /* We can get a PARALLEL dst if there is a conditional expression in
2436 a return statement. In that case, the dst and src are the same,
2437 so no action is necessary. */
2438 if (rtx_equal_p (dst, src))
2439 return;
2440
2441 /* It is unclear if we can ever reach here, but we may as well handle
2442 it. Allocate a temporary, and split this into a store/load to/from
2443 the temporary. */
2444 temp = assign_stack_temp (GET_MODE (dst), ssize);
2445 emit_group_store (temp, src, type, ssize);
2446 emit_group_load (dst, temp, type, ssize);
2447 return;
2448 }
2449 else if (!MEM_P (dst) && GET_CODE (dst) != CONCAT)
2450 {
2451 machine_mode outer = GET_MODE (dst);
2452 machine_mode inner;
2453 HOST_WIDE_INT bytepos;
2454 bool done = false;
2455 rtx temp;
2456
2457 if (!REG_P (dst) || REGNO (dst) < FIRST_PSEUDO_REGISTER)
2458 dst = gen_reg_rtx (outer);
2459
2460 /* Make life a bit easier for combine. */
2461 /* If the first element of the vector is the low part
2462 of the destination mode, use a paradoxical subreg to
2463 initialize the destination. */
2464 if (start < finish)
2465 {
2466 inner = GET_MODE (tmps[start]);
2467 bytepos = subreg_lowpart_offset (inner, outer);
2468 if (INTVAL (XEXP (XVECEXP (src, 0, start), 1)) == bytepos)
2469 {
2470 temp = simplify_gen_subreg (outer, tmps[start],
2471 inner, 0);
2472 if (temp)
2473 {
2474 emit_move_insn (dst, temp);
2475 done = true;
2476 start++;
2477 }
2478 }
2479 }
2480
2481 /* If the first element wasn't the low part, try the last. */
2482 if (!done
2483 && start < finish - 1)
2484 {
2485 inner = GET_MODE (tmps[finish - 1]);
2486 bytepos = subreg_lowpart_offset (inner, outer);
2487 if (INTVAL (XEXP (XVECEXP (src, 0, finish - 1), 1)) == bytepos)
2488 {
2489 temp = simplify_gen_subreg (outer, tmps[finish - 1],
2490 inner, 0);
2491 if (temp)
2492 {
2493 emit_move_insn (dst, temp);
2494 done = true;
2495 finish--;
2496 }
2497 }
2498 }
2499
2500 /* Otherwise, simply initialize the result to zero. */
2501 if (!done)
2502 emit_move_insn (dst, CONST0_RTX (outer));
2503 }
2504
2505 /* Process the pieces. */
2506 for (i = start; i < finish; i++)
2507 {
2508 HOST_WIDE_INT bytepos = INTVAL (XEXP (XVECEXP (src, 0, i), 1));
2509 machine_mode mode = GET_MODE (tmps[i]);
2510 unsigned int bytelen = GET_MODE_SIZE (mode);
2511 unsigned int adj_bytelen;
2512 rtx dest = dst;
2513
2514 /* Handle trailing fragments that run over the size of the struct. */
2515 if (ssize >= 0 && bytepos + (HOST_WIDE_INT) bytelen > ssize)
2516 adj_bytelen = ssize - bytepos;
2517 else
2518 adj_bytelen = bytelen;
2519
2520 if (GET_CODE (dst) == CONCAT)
2521 {
2522 if (bytepos + adj_bytelen
2523 <= GET_MODE_SIZE (GET_MODE (XEXP (dst, 0))))
2524 dest = XEXP (dst, 0);
2525 else if (bytepos >= GET_MODE_SIZE (GET_MODE (XEXP (dst, 0))))
2526 {
2527 bytepos -= GET_MODE_SIZE (GET_MODE (XEXP (dst, 0)));
2528 dest = XEXP (dst, 1);
2529 }
2530 else
2531 {
2532 machine_mode dest_mode = GET_MODE (dest);
2533 machine_mode tmp_mode = GET_MODE (tmps[i]);
2534
2535 gcc_assert (bytepos == 0 && XVECLEN (src, 0));
2536
2537 if (GET_MODE_ALIGNMENT (dest_mode)
2538 >= GET_MODE_ALIGNMENT (tmp_mode))
2539 {
2540 dest = assign_stack_temp (dest_mode,
2541 GET_MODE_SIZE (dest_mode));
2542 emit_move_insn (adjust_address (dest,
2543 tmp_mode,
2544 bytepos),
2545 tmps[i]);
2546 dst = dest;
2547 }
2548 else
2549 {
2550 dest = assign_stack_temp (tmp_mode,
2551 GET_MODE_SIZE (tmp_mode));
2552 emit_move_insn (dest, tmps[i]);
2553 dst = adjust_address (dest, dest_mode, bytepos);
2554 }
2555 break;
2556 }
2557 }
2558
2559 /* Handle trailing fragments that run over the size of the struct. */
2560 if (ssize >= 0 && bytepos + (HOST_WIDE_INT) bytelen > ssize)
2561 {
2562 /* store_bit_field always takes its value from the lsb.
2563 Move the fragment to the lsb if it's not already there. */
2564 if (
2565#ifdef BLOCK_REG_PADDING
2566 BLOCK_REG_PADDING (GET_MODE (orig_dst), type, i == start)
2567 == (BYTES_BIG_ENDIAN ? PAD_UPWARD : PAD_DOWNWARD)
2568#else
2569 BYTES_BIG_ENDIAN
2570#endif
2571 )
2572 {
2573 int shift = (bytelen - (ssize - bytepos)) * BITS_PER_UNIT;
2574 tmps[i] = expand_shift (RSHIFT_EXPR, mode, tmps[i],
2575 shift, tmps[i], 0);
2576 }
2577
2578 /* Make sure not to write past the end of the struct. */
2579 store_bit_field (dest,
2580 adj_bytelen * BITS_PER_UNIT, bytepos * BITS_PER_UNIT,
2581 bytepos * BITS_PER_UNIT, ssize * BITS_PER_UNIT - 1,
2582 VOIDmode, tmps[i], false);
2583 }
2584
2585 /* Optimize the access just a bit. */
2586 else if (MEM_P (dest)
2587 && (!targetm.slow_unaligned_access (mode, MEM_ALIGN (dest))
2588 || MEM_ALIGN (dest) >= GET_MODE_ALIGNMENT (mode))
2589 && bytepos * BITS_PER_UNIT % GET_MODE_ALIGNMENT (mode) == 0
2590 && bytelen == GET_MODE_SIZE (mode))
2591 emit_move_insn (adjust_address (dest, mode, bytepos), tmps[i]);
2592
2593 else
2594 store_bit_field (dest, bytelen * BITS_PER_UNIT, bytepos * BITS_PER_UNIT,
2595 0, 0, mode, tmps[i], false);
2596 }
2597
2598 /* Copy from the pseudo into the (probable) hard reg. */
2599 if (orig_dst != dst)
2600 emit_move_insn (orig_dst, dst);
2601}
2602
2603/* Return a form of X that does not use a PARALLEL. TYPE is the type
2604 of the value stored in X. */
2605
2606rtx
2607maybe_emit_group_store (rtx x, tree type)
2608{
2609 machine_mode mode = TYPE_MODE (type);
2610 gcc_checking_assert (GET_MODE (x) == VOIDmode || GET_MODE (x) == mode);
2611 if (GET_CODE (x) == PARALLEL)
2612 {
2613 rtx result = gen_reg_rtx (mode);
2614 emit_group_store (result, x, type, int_size_in_bytes (type));
2615 return result;
2616 }
2617 return x;
2618}
2619
2620/* Copy a BLKmode object of TYPE out of a register SRCREG into TARGET.
2621
2622 This is used on targets that return BLKmode values in registers. */
2623
2624static void
2625copy_blkmode_from_reg (rtx target, rtx srcreg, tree type)
2626{
2627 unsigned HOST_WIDE_INT bytes = int_size_in_bytes (type);
2628 rtx src = NULL, dst = NULL;
2629 unsigned HOST_WIDE_INT bitsize = MIN (TYPE_ALIGN (type), BITS_PER_WORD);
2630 unsigned HOST_WIDE_INT bitpos, xbitpos, padding_correction = 0;
2631 /* No current ABI uses variable-sized modes to pass a BLKmnode type. */
2632 fixed_size_mode mode = as_a <fixed_size_mode> (GET_MODE (srcreg));
2633 fixed_size_mode tmode = as_a <fixed_size_mode> (GET_MODE (target));
2634 fixed_size_mode copy_mode;
2635
2636 /* BLKmode registers created in the back-end shouldn't have survived. */
2637 gcc_assert (mode != BLKmode);
2638
2639 /* If the structure doesn't take up a whole number of words, see whether
2640 SRCREG is padded on the left or on the right. If it's on the left,
2641 set PADDING_CORRECTION to the number of bits to skip.
2642
2643 In most ABIs, the structure will be returned at the least end of
2644 the register, which translates to right padding on little-endian
2645 targets and left padding on big-endian targets. The opposite
2646 holds if the structure is returned at the most significant
2647 end of the register. */
2648 if (bytes % UNITS_PER_WORD != 0
2649 && (targetm.calls.return_in_msb (type)
2650 ? !BYTES_BIG_ENDIAN
2651 : BYTES_BIG_ENDIAN))
2652 padding_correction
2653 = (BITS_PER_WORD - ((bytes % UNITS_PER_WORD) * BITS_PER_UNIT));
2654
2655 /* We can use a single move if we have an exact mode for the size. */
2656 else if (MEM_P (target)
2657 && (!targetm.slow_unaligned_access (mode, MEM_ALIGN (target))
2658 || MEM_ALIGN (target) >= GET_MODE_ALIGNMENT (mode))
2659 && bytes == GET_MODE_SIZE (mode))
2660 {
2661 emit_move_insn (adjust_address (target, mode, 0), srcreg);
2662 return;
2663 }
2664
2665 /* And if we additionally have the same mode for a register. */
2666 else if (REG_P (target)
2667 && GET_MODE (target) == mode
2668 && bytes == GET_MODE_SIZE (mode))
2669 {
2670 emit_move_insn (target, srcreg);
2671 return;
2672 }
2673
2674 /* This code assumes srcreg is at least a full word. If it isn't, copy it
2675 into a new pseudo which is a full word. */
2676 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
2677 {
2678 srcreg = convert_to_mode (word_mode, srcreg, TYPE_UNSIGNED (type));
2679 mode = word_mode;
2680 }
2681
2682 /* Copy the structure BITSIZE bits at a time. If the target lives in
2683 memory, take care of not reading/writing past its end by selecting
2684 a copy mode suited to BITSIZE. This should always be possible given
2685 how it is computed.
2686
2687 If the target lives in register, make sure not to select a copy mode
2688 larger than the mode of the register.
2689
2690 We could probably emit more efficient code for machines which do not use
2691 strict alignment, but it doesn't seem worth the effort at the current
2692 time. */
2693
2694 copy_mode = word_mode;
2695 if (MEM_P (target))
2696 {
2697 opt_scalar_int_mode mem_mode = int_mode_for_size (bitsize, 1);
2698 if (mem_mode.exists ())
2699 copy_mode = mem_mode.require ();
2700 }
2701 else if (REG_P (target) && GET_MODE_BITSIZE (tmode) < BITS_PER_WORD)
2702 copy_mode = tmode;
2703
2704 for (bitpos = 0, xbitpos = padding_correction;
2705 bitpos < bytes * BITS_PER_UNIT;
2706 bitpos += bitsize, xbitpos += bitsize)
2707 {
2708 /* We need a new source operand each time xbitpos is on a
2709 word boundary and when xbitpos == padding_correction
2710 (the first time through). */
2711 if (xbitpos % BITS_PER_WORD == 0 || xbitpos == padding_correction)
2712 src = operand_subword_force (srcreg, xbitpos / BITS_PER_WORD, mode);
2713
2714 /* We need a new destination operand each time bitpos is on
2715 a word boundary. */
2716 if (REG_P (target) && GET_MODE_BITSIZE (tmode) < BITS_PER_WORD)
2717 dst = target;
2718 else if (bitpos % BITS_PER_WORD == 0)
2719 dst = operand_subword (target, bitpos / BITS_PER_WORD, 1, tmode);
2720
2721 /* Use xbitpos for the source extraction (right justified) and
2722 bitpos for the destination store (left justified). */
2723 store_bit_field (dst, bitsize, bitpos % BITS_PER_WORD, 0, 0, copy_mode,
2724 extract_bit_field (src, bitsize,
2725 xbitpos % BITS_PER_WORD, 1,
2726 NULL_RTX, copy_mode, copy_mode,
2727 false, NULL),
2728 false);
2729 }
2730}
2731
2732/* Copy BLKmode value SRC into a register of mode MODE_IN. Return the
2733 register if it contains any data, otherwise return null.
2734
2735 This is used on targets that return BLKmode values in registers. */
2736
2737rtx
2738copy_blkmode_to_reg (machine_mode mode_in, tree src)
2739{
2740 int i, n_regs;
2741 unsigned HOST_WIDE_INT bitpos, xbitpos, padding_correction = 0, bytes;
2742 unsigned int bitsize;
2743 rtx *dst_words, dst, x, src_word = NULL_RTX, dst_word = NULL_RTX;
2744 /* No current ABI uses variable-sized modes to pass a BLKmnode type. */
2745 fixed_size_mode mode = as_a <fixed_size_mode> (mode_in);
2746 fixed_size_mode dst_mode;
2747
2748 gcc_assert (TYPE_MODE (TREE_TYPE (src)) == BLKmode);
2749
2750 x = expand_normal (src);
2751
2752 bytes = arg_int_size_in_bytes (TREE_TYPE (src));
2753 if (bytes == 0)
2754 return NULL_RTX;
2755
2756 /* If the structure doesn't take up a whole number of words, see
2757 whether the register value should be padded on the left or on
2758 the right. Set PADDING_CORRECTION to the number of padding
2759 bits needed on the left side.
2760
2761 In most ABIs, the structure will be returned at the least end of
2762 the register, which translates to right padding on little-endian
2763 targets and left padding on big-endian targets. The opposite
2764 holds if the structure is returned at the most significant
2765 end of the register. */
2766 if (bytes % UNITS_PER_WORD != 0
2767 && (targetm.calls.return_in_msb (TREE_TYPE (src))
2768 ? !BYTES_BIG_ENDIAN
2769 : BYTES_BIG_ENDIAN))
2770 padding_correction = (BITS_PER_WORD - ((bytes % UNITS_PER_WORD)
2771 * BITS_PER_UNIT));
2772
2773 n_regs = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2774 dst_words = XALLOCAVEC (rtx, n_regs);
2775 bitsize = BITS_PER_WORD;
2776 if (targetm.slow_unaligned_access (word_mode, TYPE_ALIGN (TREE_TYPE (src))))
2777 bitsize = MIN (TYPE_ALIGN (TREE_TYPE (src)), BITS_PER_WORD);
2778
2779 /* Copy the structure BITSIZE bits at a time. */
2780 for (bitpos = 0, xbitpos = padding_correction;
2781 bitpos < bytes * BITS_PER_UNIT;
2782 bitpos += bitsize, xbitpos += bitsize)
2783 {
2784 /* We need a new destination pseudo each time xbitpos is
2785 on a word boundary and when xbitpos == padding_correction
2786 (the first time through). */
2787 if (xbitpos % BITS_PER_WORD == 0
2788 || xbitpos == padding_correction)
2789 {
2790 /* Generate an appropriate register. */
2791 dst_word = gen_reg_rtx (word_mode);
2792 dst_words[xbitpos / BITS_PER_WORD] = dst_word;
2793
2794 /* Clear the destination before we move anything into it. */
2795 emit_move_insn (dst_word, CONST0_RTX (word_mode));
2796 }
2797
2798 /* We need a new source operand each time bitpos is on a word
2799 boundary. */
2800 if (bitpos % BITS_PER_WORD == 0)
2801 src_word = operand_subword_force (x, bitpos / BITS_PER_WORD, BLKmode);
2802
2803 /* Use bitpos for the source extraction (left justified) and
2804 xbitpos for the destination store (right justified). */
2805 store_bit_field (dst_word, bitsize, xbitpos % BITS_PER_WORD,
2806 0, 0, word_mode,
2807 extract_bit_field (src_word, bitsize,
2808 bitpos % BITS_PER_WORD, 1,
2809 NULL_RTX, word_mode, word_mode,
2810 false, NULL),
2811 false);
2812 }
2813
2814 if (mode == BLKmode)
2815 {
2816 /* Find the smallest integer mode large enough to hold the
2817 entire structure. */
2818 opt_scalar_int_mode mode_iter;
2819 FOR_EACH_MODE_IN_CLASS (mode_iter, MODE_INT)
2820 if (GET_MODE_SIZE (mode_iter.require ()) >= bytes)
2821 break;
2822
2823 /* A suitable mode should have been found. */
2824 mode = mode_iter.require ();
2825 }
2826
2827 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (word_mode))
2828 dst_mode = word_mode;
2829 else
2830 dst_mode = mode;
2831 dst = gen_reg_rtx (dst_mode);
2832
2833 for (i = 0; i < n_regs; i++)
2834 emit_move_insn (operand_subword (dst, i, 0, dst_mode), dst_words[i]);
2835
2836 if (mode != dst_mode)
2837 dst = gen_lowpart (mode, dst);
2838
2839 return dst;
2840}
2841
2842/* Add a USE expression for REG to the (possibly empty) list pointed
2843 to by CALL_FUSAGE. REG must denote a hard register. */
2844
2845void
2846use_reg_mode (rtx *call_fusage, rtx reg, machine_mode mode)
2847{
2848 gcc_assert (REG_P (reg));
2849
2850 if (!HARD_REGISTER_P (reg))
2851 return;
2852
2853 *call_fusage
2854 = gen_rtx_EXPR_LIST (mode, gen_rtx_USE (VOIDmode, reg), *call_fusage);
2855}
2856
2857/* Add a CLOBBER expression for REG to the (possibly empty) list pointed
2858 to by CALL_FUSAGE. REG must denote a hard register. */
2859
2860void
2861clobber_reg_mode (rtx *call_fusage, rtx reg, machine_mode mode)
2862{
2863 gcc_assert (REG_P (reg) && REGNO (reg) < FIRST_PSEUDO_REGISTER);
2864
2865 *call_fusage
2866 = gen_rtx_EXPR_LIST (mode, gen_rtx_CLOBBER (VOIDmode, reg), *call_fusage);
2867}
2868
2869/* Add USE expressions to *CALL_FUSAGE for each of NREGS consecutive regs,
2870 starting at REGNO. All of these registers must be hard registers. */
2871
2872void
2873use_regs (rtx *call_fusage, int regno, int nregs)
2874{
2875 int i;
2876
2877 gcc_assert (regno + nregs <= FIRST_PSEUDO_REGISTER);
2878
2879 for (i = 0; i < nregs; i++)
2880 use_reg (call_fusage, regno_reg_rtx[regno + i]);
2881}
2882
2883/* Add USE expressions to *CALL_FUSAGE for each REG contained in the
2884 PARALLEL REGS. This is for calls that pass values in multiple
2885 non-contiguous locations. The Irix 6 ABI has examples of this. */
2886
2887void
2888use_group_regs (rtx *call_fusage, rtx regs)
2889{
2890 int i;
2891
2892 for (i = 0; i < XVECLEN (regs, 0); i++)
2893 {
2894 rtx reg = XEXP (XVECEXP (regs, 0, i), 0);
2895
2896 /* A NULL entry means the parameter goes both on the stack and in
2897 registers. This can also be a MEM for targets that pass values
2898 partially on the stack and partially in registers. */
2899 if (reg != 0 && REG_P (reg))
2900 use_reg (call_fusage, reg);
2901 }
2902}
2903
2904/* Return the defining gimple statement for SSA_NAME NAME if it is an
2905 assigment and the code of the expresion on the RHS is CODE. Return
2906 NULL otherwise. */
2907
2908static gimple *
2909get_def_for_expr (tree name, enum tree_code code)
2910{
2911 gimple *def_stmt;
2912
2913 if (TREE_CODE (name) != SSA_NAME)
2914 return NULL;
2915
2916 def_stmt = get_gimple_for_ssa_name (name);
2917 if (!def_stmt
2918 || gimple_assign_rhs_code (def_stmt) != code)
2919 return NULL;
2920
2921 return def_stmt;
2922}
2923
2924/* Return the defining gimple statement for SSA_NAME NAME if it is an
2925 assigment and the class of the expresion on the RHS is CLASS. Return
2926 NULL otherwise. */
2927
2928static gimple *
2929get_def_for_expr_class (tree name, enum tree_code_class tclass)
2930{
2931 gimple *def_stmt;
2932
2933 if (TREE_CODE (name) != SSA_NAME)
2934 return NULL;
2935
2936 def_stmt = get_gimple_for_ssa_name (name);
2937 if (!def_stmt
2938 || TREE_CODE_CLASS (gimple_assign_rhs_code (def_stmt)) != tclass)
2939 return NULL;
2940
2941 return def_stmt;
2942}
2943
2944/* Write zeros through the storage of OBJECT. If OBJECT has BLKmode, SIZE is
2945 its length in bytes. */
2946
2947rtx
2948clear_storage_hints (rtx object, rtx size, enum block_op_methods method,
2949 unsigned int expected_align, HOST_WIDE_INT expected_size,
2950 unsigned HOST_WIDE_INT min_size,
2951 unsigned HOST_WIDE_INT max_size,
2952 unsigned HOST_WIDE_INT probable_max_size)
2953{
2954 machine_mode mode = GET_MODE (object);
2955 unsigned int align;
2956
2957 gcc_assert (method == BLOCK_OP_NORMAL || method == BLOCK_OP_TAILCALL);
2958
2959 /* If OBJECT is not BLKmode and SIZE is the same size as its mode,
2960 just move a zero. Otherwise, do this a piece at a time. */
2961 if (mode != BLKmode
2962 && CONST_INT_P (size)
2963 && INTVAL (size) == (HOST_WIDE_INT) GET_MODE_SIZE (mode))
2964 {
2965 rtx zero = CONST0_RTX (mode);
2966 if (zero != NULL)
2967 {
2968 emit_move_insn (object, zero);
2969 return NULL;
2970 }
2971
2972 if (COMPLEX_MODE_P (mode))
2973 {
2974 zero = CONST0_RTX (GET_MODE_INNER (mode));
2975 if (zero != NULL)
2976 {
2977 write_complex_part (object, zero, 0);
2978 write_complex_part (object, zero, 1);
2979 return NULL;
2980 }
2981 }
2982 }
2983
2984 if (size == const0_rtx)
2985 return NULL;
2986
2987 align = MEM_ALIGN (object);
2988
2989 if (CONST_INT_P (size)
2990 && targetm.use_by_pieces_infrastructure_p (INTVAL (size), align,
2991 CLEAR_BY_PIECES,
2992 optimize_insn_for_speed_p ()))
2993 clear_by_pieces (object, INTVAL (size), align);
2994 else if (set_storage_via_setmem (object, size, const0_rtx, align,
2995 expected_align, expected_size,
2996 min_size, max_size, probable_max_size))
2997 ;
2998 else if (ADDR_SPACE_GENERIC_P (MEM_ADDR_SPACE (object)))
2999 return set_storage_via_libcall (object, size, const0_rtx,
3000 method == BLOCK_OP_TAILCALL);
3001 else
3002 gcc_unreachable ();
3003
3004 return NULL;
3005}
3006
3007rtx
3008clear_storage (rtx object, rtx size, enum block_op_methods method)
3009{
3010 unsigned HOST_WIDE_INT max, min = 0;
3011 if (GET_CODE (size) == CONST_INT)
3012 min = max = UINTVAL (size);
3013 else
3014 max = GET_MODE_MASK (GET_MODE (size));
3015 return clear_storage_hints (object, size, method, 0, -1, min, max, max);
3016}
3017
3018
3019/* A subroutine of clear_storage. Expand a call to memset.
3020 Return the return value of memset, 0 otherwise. */
3021
3022rtx
3023set_storage_via_libcall (rtx object, rtx size, rtx val, bool tailcall)
3024{
3025 tree call_expr, fn, object_tree, size_tree, val_tree;
3026 machine_mode size_mode;
3027
3028 object = copy_addr_to_reg (XEXP (object, 0));
3029 object_tree = make_tree (ptr_type_node, object);
3030
3031 if (!CONST_INT_P (val))
3032 val = convert_to_mode (TYPE_MODE (integer_type_node), val, 1);
3033 val_tree = make_tree (integer_type_node, val);
3034
3035 size_mode = TYPE_MODE (sizetype);
3036 size = convert_to_mode (size_mode, size, 1);
3037 size = copy_to_mode_reg (size_mode, size);
3038 size_tree = make_tree (sizetype, size);
3039
3040 /* It is incorrect to use the libcall calling conventions for calls to
3041 memset because it can be provided by the user. */
3042 fn = builtin_decl_implicit (BUILT_IN_MEMSET);
3043 call_expr = build_call_expr (fn, 3, object_tree, val_tree, size_tree);
3044 CALL_EXPR_TAILCALL (call_expr) = tailcall;
3045
3046 return expand_call (call_expr, NULL_RTX, false);
3047}
3048
3049/* Expand a setmem pattern; return true if successful. */
3050
3051bool
3052set_storage_via_setmem (rtx object, rtx size, rtx val, unsigned int align,
3053 unsigned int expected_align, HOST_WIDE_INT expected_size,
3054 unsigned HOST_WIDE_INT min_size,
3055 unsigned HOST_WIDE_INT max_size,
3056 unsigned HOST_WIDE_INT probable_max_size)
3057{
3058 /* Try the most limited insn first, because there's no point
3059 including more than one in the machine description unless
3060 the more limited one has some advantage. */
3061
3062 if (expected_align < align)
3063 expected_align = align;
3064 if (expected_size != -1)
3065 {
3066 if ((unsigned HOST_WIDE_INT)expected_size > max_size)
3067 expected_size = max_size;
3068 if ((unsigned HOST_WIDE_INT)expected_size < min_size)
3069 expected_size = min_size;
3070 }
3071
3072 opt_scalar_int_mode mode_iter;
3073 FOR_EACH_MODE_IN_CLASS (mode_iter, MODE_INT)
3074 {
3075 scalar_int_mode mode = mode_iter.require ();
3076 enum insn_code code = direct_optab_handler (setmem_optab, mode);
3077
3078 if (code != CODE_FOR_nothing
3079 /* We don't need MODE to be narrower than BITS_PER_HOST_WIDE_INT
3080 here because if SIZE is less than the mode mask, as it is
3081 returned by the macro, it will definitely be less than the
3082 actual mode mask. Since SIZE is within the Pmode address
3083 space, we limit MODE to Pmode. */
3084 && ((CONST_INT_P (size)
3085 && ((unsigned HOST_WIDE_INT) INTVAL (size)
3086 <= (GET_MODE_MASK (mode) >> 1)))
3087 || max_size <= (GET_MODE_MASK (mode) >> 1)
3088 || GET_MODE_BITSIZE (mode) >= GET_MODE_BITSIZE (Pmode)))
3089 {
3090 struct expand_operand ops[9];
3091 unsigned int nops;
3092
3093 nops = insn_data[(int) code].n_generator_args;
3094 gcc_assert (nops == 4 || nops == 6 || nops == 8 || nops == 9);
3095
3096 create_fixed_operand (&ops[0], object);
3097 /* The check above guarantees that this size conversion is valid. */
3098 create_convert_operand_to (&ops[1], size, mode, true);
3099 create_convert_operand_from (&ops[2], val, byte_mode, true);
3100 create_integer_operand (&ops[3], align / BITS_PER_UNIT);
3101 if (nops >= 6)
3102 {
3103 create_integer_operand (&ops[4], expected_align / BITS_PER_UNIT);
3104 create_integer_operand (&ops[5], expected_size);
3105 }
3106 if (nops >= 8)
3107 {
3108 create_integer_operand (&ops[6], min_size);
3109 /* If we can not represent the maximal size,
3110 make parameter NULL. */
3111 if ((HOST_WIDE_INT) max_size != -1)
3112 create_integer_operand (&ops[7], max_size);
3113 else
3114 create_fixed_operand (&ops[7], NULL);
3115 }
3116 if (nops == 9)
3117 {
3118 /* If we can not represent the maximal size,
3119 make parameter NULL. */
3120 if ((HOST_WIDE_INT) probable_max_size != -1)
3121 create_integer_operand (&ops[8], probable_max_size);
3122 else
3123 create_fixed_operand (&ops[8], NULL);
3124 }
3125 if (maybe_expand_insn (code, nops, ops))
3126 return true;
3127 }
3128 }
3129
3130 return false;
3131}
3132
3133
3134/* Write to one of the components of the complex value CPLX. Write VAL to
3135 the real part if IMAG_P is false, and the imaginary part if its true. */
3136
3137void
3138write_complex_part (rtx cplx, rtx val, bool imag_p)
3139{
3140 machine_mode cmode;
3141 scalar_mode imode;
3142 unsigned ibitsize;
3143
3144 if (GET_CODE (cplx) == CONCAT)
3145 {
3146 emit_move_insn (XEXP (cplx, imag_p), val);
3147 return;
3148 }
3149
3150 cmode = GET_MODE (cplx);
3151 imode = GET_MODE_INNER (cmode);
3152 ibitsize = GET_MODE_BITSIZE (imode);
3153
3154 /* For MEMs simplify_gen_subreg may generate an invalid new address
3155 because, e.g., the original address is considered mode-dependent
3156 by the target, which restricts simplify_subreg from invoking
3157 adjust_address_nv. Instead of preparing fallback support for an
3158 invalid address, we call adjust_address_nv directly. */
3159 if (MEM_P (cplx))
3160 {
3161 emit_move_insn (adjust_address_nv (cplx, imode,
3162 imag_p ? GET_MODE_SIZE (imode) : 0),
3163 val);
3164 return;
3165 }
3166
3167 /* If the sub-object is at least word sized, then we know that subregging
3168 will work. This special case is important, since store_bit_field
3169 wants to operate on integer modes, and there's rarely an OImode to
3170 correspond to TCmode. */
3171 if (ibitsize >= BITS_PER_WORD
3172 /* For hard regs we have exact predicates. Assume we can split
3173 the original object if it spans an even number of hard regs.
3174 This special case is important for SCmode on 64-bit platforms
3175 where the natural size of floating-point regs is 32-bit. */
3176 || (REG_P (cplx)
3177 && REGNO (cplx) < FIRST_PSEUDO_REGISTER
3178 && REG_NREGS (cplx) % 2 == 0))
3179 {
3180 rtx part = simplify_gen_subreg (imode, cplx, cmode,
3181 imag_p ? GET_MODE_SIZE (imode) : 0);
3182 if (part)
3183 {
3184 emit_move_insn (part, val);
3185 return;
3186 }
3187 else
3188 /* simplify_gen_subreg may fail for sub-word MEMs. */
3189 gcc_assert (MEM_P (cplx) && ibitsize < BITS_PER_WORD);
3190 }
3191
3192 store_bit_field (cplx, ibitsize, imag_p ? ibitsize : 0, 0, 0, imode, val,
3193 false);
3194}
3195
3196/* Extract one of the components of the complex value CPLX. Extract the
3197 real part if IMAG_P is false, and the imaginary part if it's true. */
3198
3199rtx
3200read_complex_part (rtx cplx, bool imag_p)
3201{
3202 machine_mode cmode;
3203 scalar_mode imode;
3204 unsigned ibitsize;
3205
3206 if (GET_CODE (cplx) == CONCAT)
3207 return XEXP (cplx, imag_p);
3208
3209 cmode = GET_MODE (cplx);
3210 imode = GET_MODE_INNER (cmode);
3211 ibitsize = GET_MODE_BITSIZE (imode);
3212
3213 /* Special case reads from complex constants that got spilled to memory. */
3214 if (MEM_P (cplx) && GET_CODE (XEXP (cplx, 0)) == SYMBOL_REF)
3215 {
3216 tree decl = SYMBOL_REF_DECL (XEXP (cplx, 0));
3217 if (decl && TREE_CODE (decl) == COMPLEX_CST)
3218 {
3219 tree part = imag_p ? TREE_IMAGPART (decl) : TREE_REALPART (decl);
3220 if (CONSTANT_CLASS_P (part))
3221 return expand_expr (part, NULL_RTX, imode, EXPAND_NORMAL);
3222 }
3223 }
3224
3225 /* For MEMs simplify_gen_subreg may generate an invalid new address
3226 because, e.g., the original address is considered mode-dependent
3227 by the target, which restricts simplify_subreg from invoking
3228 adjust_address_nv. Instead of preparing fallback support for an
3229 invalid address, we call adjust_address_nv directly. */
3230 if (MEM_P (cplx))
3231 return adjust_address_nv (cplx, imode,
3232 imag_p ? GET_MODE_SIZE (imode) : 0);
3233
3234 /* If the sub-object is at least word sized, then we know that subregging
3235 will work. This special case is important, since extract_bit_field
3236 wants to operate on integer modes, and there's rarely an OImode to
3237 correspond to TCmode. */
3238 if (ibitsize >= BITS_PER_WORD
3239 /* For hard regs we have exact predicates. Assume we can split
3240 the original object if it spans an even number of hard regs.
3241 This special case is important for SCmode on 64-bit platforms
3242 where the natural size of floating-point regs is 32-bit. */
3243 || (REG_P (cplx)
3244 && REGNO (cplx) < FIRST_PSEUDO_REGISTER
3245 && REG_NREGS (cplx) % 2 == 0))
3246 {
3247 rtx ret = simplify_gen_subreg (imode, cplx, cmode,
3248 imag_p ? GET_MODE_SIZE (imode) : 0);
3249 if (ret)
3250 return ret;
3251 else
3252 /* simplify_gen_subreg may fail for sub-word MEMs. */
3253 gcc_assert (MEM_P (cplx) && ibitsize < BITS_PER_WORD);
3254 }
3255
3256 return extract_bit_field (cplx, ibitsize, imag_p ? ibitsize : 0,
3257 true, NULL_RTX, imode, imode, false, NULL);
3258}
3259
3260/* A subroutine of emit_move_insn_1. Yet another lowpart generator.
3261 NEW_MODE and OLD_MODE are the same size. Return NULL if X cannot be
3262 represented in NEW_MODE. If FORCE is true, this will never happen, as
3263 we'll force-create a SUBREG if needed. */
3264
3265static rtx
3266emit_move_change_mode (machine_mode new_mode,
3267 machine_mode old_mode, rtx x, bool force)
3268{
3269 rtx ret;
3270
3271 if (push_operand (x, GET_MODE (x)))
3272 {
3273 ret = gen_rtx_MEM (new_mode, XEXP (x, 0));
3274 MEM_COPY_ATTRIBUTES (ret, x);
3275 }
3276 else if (MEM_P (x))
3277 {
3278 /* We don't have to worry about changing the address since the
3279 size in bytes is supposed to be the same. */
3280 if (reload_in_progress)
3281 {
3282 /* Copy the MEM to change the mode and move any
3283 substitutions from the old MEM to the new one. */
3284 ret = adjust_address_nv (x, new_mode, 0);
3285 copy_replacements (x, ret);
3286 }
3287 else
3288 ret = adjust_address (x, new_mode, 0);
3289 }
3290 else
3291 {
3292 /* Note that we do want simplify_subreg's behavior of validating
3293 that the new mode is ok for a hard register. If we were to use
3294 simplify_gen_subreg, we would create the subreg, but would
3295 probably run into the target not being able to implement it. */
3296 /* Except, of course, when FORCE is true, when this is exactly what
3297 we want. Which is needed for CCmodes on some targets. */
3298 if (force)
3299 ret = simplify_gen_subreg (new_mode, x, old_mode, 0);
3300 else
3301 ret = simplify_subreg (new_mode, x, old_mode, 0);
3302 }
3303
3304 return ret;
3305}
3306
3307/* A subroutine of emit_move_insn_1. Generate a move from Y into X using
3308 an integer mode of the same size as MODE. Returns the instruction
3309 emitted, or NULL if such a move could not be generated. */
3310
3311static rtx_insn *
3312emit_move_via_integer (machine_mode mode, rtx x, rtx y, bool force)
3313{
3314 scalar_int_mode imode;
3315 enum insn_code code;
3316
3317 /* There must exist a mode of the exact size we require. */
3318 if (!int_mode_for_mode (mode).exists (&imode))
3319 return NULL;
3320
3321 /* The target must support moves in this mode. */
3322 code = optab_handler (mov_optab, imode);
3323 if (code == CODE_FOR_nothing)
3324 return NULL;
3325
3326 x = emit_move_change_mode (imode, mode, x, force);
3327 if (x == NULL_RTX)
3328 return NULL;
3329 y = emit_move_change_mode (imode, mode, y, force);
3330 if (y == NULL_RTX)
3331 return NULL;
3332 return emit_insn (GEN_FCN (code) (x, y));
3333}
3334
3335/* A subroutine of emit_move_insn_1. X is a push_operand in MODE.
3336 Return an equivalent MEM that does not use an auto-increment. */
3337
3338rtx
3339emit_move_resolve_push (machine_mode mode, rtx x)
3340{
3341 enum rtx_code code = GET_CODE (XEXP (x, 0));
3342 HOST_WIDE_INT adjust;
3343 rtx temp;
3344
3345 adjust = GET_MODE_SIZE (mode);
3346#ifdef PUSH_ROUNDING
3347 adjust = PUSH_ROUNDING (adjust);
3348#endif
3349 if (code == PRE_DEC || code == POST_DEC)
3350 adjust = -adjust;
3351 else if (code == PRE_MODIFY || code == POST_MODIFY)
3352 {
3353 rtx expr = XEXP (XEXP (x, 0), 1);
3354 HOST_WIDE_INT val;
3355
3356 gcc_assert (GET_CODE (expr) == PLUS || GET_CODE (expr) == MINUS);
3357 gcc_assert (CONST_INT_P (XEXP (expr, 1)));
3358 val = INTVAL (XEXP (expr, 1));
3359 if (GET_CODE (expr) == MINUS)
3360 val = -val;
3361 gcc_assert (adjust == val || adjust == -val);
3362 adjust = val;
3363 }
3364
3365 /* Do not use anti_adjust_stack, since we don't want to update
3366 stack_pointer_delta. */
3367 temp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
3368 gen_int_mode (adjust, Pmode), stack_pointer_rtx,
3369 0, OPTAB_LIB_WIDEN);
3370 if (temp != stack_pointer_rtx)
3371 emit_move_insn (stack_pointer_rtx, temp);
3372
3373 switch (code)
3374 {
3375 case PRE_INC:
3376 case PRE_DEC:
3377 case PRE_MODIFY:
3378 temp = stack_pointer_rtx;
3379 break;
3380 case POST_INC:
3381 case POST_DEC:
3382 case POST_MODIFY:
3383 temp = plus_constant (Pmode, stack_pointer_rtx, -adjust);
3384 break;
3385 default:
3386 gcc_unreachable ();
3387 }
3388
3389 return replace_equiv_address (x, temp);
3390}
3391
3392/* A subroutine of emit_move_complex. Generate a move from Y into X.
3393 X is known to satisfy push_operand, and MODE is known to be complex.
3394 Returns the last instruction emitted. */
3395
3396rtx_insn *
3397emit_move_complex_push (machine_mode mode, rtx x, rtx y)
3398{
3399 scalar_mode submode = GET_MODE_INNER (mode);
3400 bool imag_first;
3401
3402#ifdef PUSH_ROUNDING
3403 unsigned int submodesize = GET_MODE_SIZE (submode);
3404
3405 /* In case we output to the stack, but the size is smaller than the
3406 machine can push exactly, we need to use move instructions. */
3407 if (PUSH_ROUNDING (submodesize) != submodesize)
3408 {
3409 x = emit_move_resolve_push (mode, x);
3410 return emit_move_insn (x, y);
3411 }
3412#endif
3413
3414 /* Note that the real part always precedes the imag part in memory
3415 regardless of machine's endianness. */
3416 switch (GET_CODE (XEXP (x, 0)))
3417 {
3418 case PRE_DEC:
3419 case POST_DEC:
3420 imag_first = true;
3421 break;
3422 case PRE_INC:
3423 case POST_INC:
3424 imag_first = false;
3425 break;
3426 default:
3427 gcc_unreachable ();
3428 }
3429
3430 emit_move_insn (gen_rtx_MEM (submode, XEXP (x, 0)),
3431 read_complex_part (y, imag_first));
3432 return emit_move_insn (gen_rtx_MEM (submode, XEXP (x, 0)),
3433 read_complex_part (y, !imag_first));
3434}
3435
3436/* A subroutine of emit_move_complex. Perform the move from Y to X
3437 via two moves of the parts. Returns the last instruction emitted. */
3438
3439rtx_insn *
3440emit_move_complex_parts (rtx x, rtx y)
3441{
3442 /* Show the output dies here. This is necessary for SUBREGs
3443 of pseudos since we cannot track their lifetimes correctly;
3444 hard regs shouldn't appear here except as return values. */
3445 if (!reload_completed && !reload_in_progress
3446 && REG_P (x) && !reg_overlap_mentioned_p (x, y))
3447 emit_clobber (x);
3448
3449 write_complex_part (x, read_complex_part (y, false), false);
3450 write_complex_part (x, read_complex_part (y, true), true);
3451
3452 return get_last_insn ();
3453}
3454
3455/* A subroutine of emit_move_insn_1. Generate a move from Y into X.
3456 MODE is known to be complex. Returns the last instruction emitted. */
3457
3458static rtx_insn *
3459emit_move_complex (machine_mode mode, rtx x, rtx y)
3460{
3461 bool try_int;
3462
3463 /* Need to take special care for pushes, to maintain proper ordering
3464 of the data, and possibly extra padding. */
3465 if (push_operand (x, mode))
3466 return emit_move_complex_push (mode, x, y);
3467
3468 /* See if we can coerce the target into moving both values at once, except
3469 for floating point where we favor moving as parts if this is easy. */
3470 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3471 && optab_handler (mov_optab, GET_MODE_INNER (mode)) != CODE_FOR_nothing
3472 && !(REG_P (x)
3473 && HARD_REGISTER_P (x)
3474 && REG_NREGS (x) == 1)
3475 && !(REG_P (y)
3476 && HARD_REGISTER_P (y)
3477 && REG_NREGS (y) == 1))
3478 try_int = false;
3479 /* Not possible if the values are inherently not adjacent. */
3480 else if (GET_CODE (x) == CONCAT || GET_CODE (y) == CONCAT)
3481 try_int = false;
3482 /* Is possible if both are registers (or subregs of registers). */
3483 else if (register_operand (x, mode) && register_operand (y, mode))
3484 try_int = true;
3485 /* If one of the operands is a memory, and alignment constraints
3486 are friendly enough, we may be able to do combined memory operations.
3487 We do not attempt this if Y is a constant because that combination is
3488 usually better with the by-parts thing below. */
3489 else if ((MEM_P (x) ? !CONSTANT_P (y) : MEM_P (y))
3490 && (!STRICT_ALIGNMENT
3491 || get_mode_alignment (mode) == BIGGEST_ALIGNMENT))
3492 try_int = true;
3493 else
3494 try_int = false;
3495
3496 if (try_int)
3497 {
3498 rtx_insn *ret;
3499
3500 /* For memory to memory moves, optimal behavior can be had with the
3501 existing block move logic. */
3502 if (MEM_P (x) && MEM_P (y))
3503 {
3504 emit_block_move (x, y, GEN_INT (GET_MODE_SIZE (mode)),
3505 BLOCK_OP_NO_LIBCALL);
3506 return get_last_insn ();
3507 }
3508
3509 ret = emit_move_via_integer (mode, x, y, true);
3510 if (ret)
3511 return ret;
3512 }
3513
3514 return emit_move_complex_parts (x, y);
3515}
3516
3517/* A subroutine of emit_move_insn_1. Generate a move from Y into X.
3518 MODE is known to be MODE_CC. Returns the last instruction emitted. */
3519
3520static rtx_insn *
3521emit_move_ccmode (machine_mode mode, rtx x, rtx y)
3522{
3523 rtx_insn *ret;
3524
3525 /* Assume all MODE_CC modes are equivalent; if we have movcc, use it. */
3526 if (mode != CCmode)
3527 {
3528 enum insn_code code = optab_handler (mov_optab, CCmode);
3529 if (code != CODE_FOR_nothing)
3530 {
3531 x = emit_move_change_mode (CCmode, mode, x, true);
3532 y = emit_move_change_mode (CCmode, mode, y, true);
3533 return emit_insn (GEN_FCN (code) (x, y));
3534 }
3535 }
3536
3537 /* Otherwise, find the MODE_INT mode of the same width. */
3538 ret = emit_move_via_integer (mode, x, y, false);
3539 gcc_assert (ret != NULL);
3540 return ret;
3541}
3542
3543/* Return true if word I of OP lies entirely in the
3544 undefined bits of a paradoxical subreg. */
3545
3546static bool
3547undefined_operand_subword_p (const_rtx op, int i)
3548{
3549 if (GET_CODE (op) != SUBREG)
3550 return false;
3551 machine_mode innermostmode = GET_MODE (SUBREG_REG (op));
3552 HOST_WIDE_INT offset = i * UNITS_PER_WORD + subreg_memory_offset (op);
3553 return (offset >= GET_MODE_SIZE (innermostmode)
3554 || offset <= -UNITS_PER_WORD);
3555}
3556
3557/* A subroutine of emit_move_insn_1. Generate a move from Y into X.
3558 MODE is any multi-word or full-word mode that lacks a move_insn
3559 pattern. Note that you will get better code if you define such
3560 patterns, even if they must turn into multiple assembler instructions. */
3561
3562static rtx_insn *
3563emit_move_multi_word (machine_mode mode, rtx x, rtx y)
3564{
3565 rtx_insn *last_insn = 0;
3566 rtx_insn *seq;
3567 rtx inner;
3568 bool need_clobber;
3569 int i;
3570
3571 gcc_assert (GET_MODE_SIZE (mode) >= UNITS_PER_WORD);
3572
3573 /* If X is a push on the stack, do the push now and replace
3574 X with a reference to the stack pointer. */
3575 if (push_operand (x, mode))
3576 x = emit_move_resolve_push (mode, x);
3577
3578 /* If we are in reload, see if either operand is a MEM whose address
3579 is scheduled for replacement. */
3580 if (reload_in_progress && MEM_P (x)
3581 && (inner = find_replacement (&XEXP (x, 0))) != XEXP (x, 0))
3582 x = replace_equiv_address_nv (x, inner);
3583 if (reload_in_progress && MEM_P (y)
3584 && (inner = find_replacement (&XEXP (y, 0))) != XEXP (y, 0))
3585 y = replace_equiv_address_nv (y, inner);
3586
3587 start_sequence ();
3588
3589 need_clobber = false;
3590 for (i = 0;
3591 i < (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
3592 i++)
3593 {
3594 rtx xpart = operand_subword (x, i, 1, mode);
3595 rtx ypart;
3596
3597 /* Do not generate code for a move if it would come entirely
3598 from the undefined bits of a paradoxical subreg. */
3599 if (undefined_operand_subword_p (y, i))
3600 continue;
3601
3602 ypart = operand_subword (y, i, 1, mode);
3603
3604 /* If we can't get a part of Y, put Y into memory if it is a
3605 constant. Otherwise, force it into a register. Then we must
3606 be able to get a part of Y. */
3607 if (ypart == 0 && CONSTANT_P (y))
3608 {
3609 y = use_anchored_address (force_const_mem (mode, y));
3610 ypart = operand_subword (y, i, 1, mode);
3611 }
3612 else if (ypart == 0)
3613 ypart = operand_subword_force (y, i, mode);
3614
3615 gcc_assert (xpart && ypart);
3616
3617 need_clobber |= (GET_CODE (xpart) == SUBREG);
3618
3619 last_insn = emit_move_insn (xpart, ypart);
3620 }
3621
3622 seq = get_insns ();
3623 end_sequence ();
3624
3625 /* Show the output dies here. This is necessary for SUBREGs
3626 of pseudos since we cannot track their lifetimes correctly;
3627 hard regs shouldn't appear here except as return values.
3628 We never want to emit such a clobber after reload. */
3629 if (x != y
3630 && ! (reload_in_progress || reload_completed)
3631 && need_clobber != 0)
3632 emit_clobber (x);
3633
3634 emit_insn (seq);
3635
3636 return last_insn;
3637}
3638
3639/* Low level part of emit_move_insn.
3640 Called just like emit_move_insn, but assumes X and Y
3641 are basically valid. */
3642
3643rtx_insn *
3644emit_move_insn_1 (rtx x, rtx y)
3645{
3646 machine_mode mode = GET_MODE (x);
3647 enum insn_code code;
3648
3649 gcc_assert ((unsigned int) mode < (unsigned int) MAX_MACHINE_MODE);
3650
3651 code = optab_handler (mov_optab, mode);
3652 if (code != CODE_FOR_nothing)
3653 return emit_insn (GEN_FCN (code) (x, y));
3654
3655 /* Expand complex moves by moving real part and imag part. */
3656 if (COMPLEX_MODE_P (mode))
3657 return emit_move_complex (mode, x, y);
3658
3659 if (GET_MODE_CLASS (mode) == MODE_DECIMAL_FLOAT
3660 || ALL_FIXED_POINT_MODE_P (mode))
3661 {
3662 rtx_insn *result = emit_move_via_integer (mode, x, y, true);
3663
3664 /* If we can't find an integer mode, use multi words. */
3665 if (result)
3666 return result;
3667 else
3668 return emit_move_multi_word (mode, x, y);
3669 }
3670
3671 if (GET_MODE_CLASS (mode) == MODE_CC)
3672 return emit_move_ccmode (mode, x, y);
3673
3674 /* Try using a move pattern for the corresponding integer mode. This is
3675 only safe when simplify_subreg can convert MODE constants into integer
3676 constants. At present, it can only do this reliably if the value
3677 fits within a HOST_WIDE_INT. */
3678 if (!CONSTANT_P (y) || GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3679 {
3680 rtx_insn *ret = emit_move_via_integer (mode, x, y, lra_in_progress);
3681
3682 if (ret)
3683 {
3684 if (! lra_in_progress || recog (PATTERN (ret), ret, 0) >= 0)
3685 return ret;
3686 }
3687 }
3688
3689 return emit_move_multi_word (mode, x, y);
3690}
3691
3692/* Generate code to copy Y into X.
3693 Both Y and X must have the same mode, except that
3694 Y can be a constant with VOIDmode.
3695 This mode cannot be BLKmode; use emit_block_move for that.
3696
3697 Return the last instruction emitted. */
3698
3699rtx_insn *
3700emit_move_insn (rtx x, rtx y)
3701{
3702 machine_mode mode = GET_MODE (x);
3703 rtx y_cst = NULL_RTX;
3704 rtx_insn *last_insn;
3705 rtx set;
3706
3707 gcc_assert (mode != BLKmode
3708 && (GET_MODE (y) == mode || GET_MODE (y) == VOIDmode));
3709
3710 if (CONSTANT_P (y))
3711 {
3712 if (optimize
3713 && SCALAR_FLOAT_MODE_P (GET_MODE (x))
3714 && (last_insn = compress_float_constant (x, y)))
3715 return last_insn;
3716
3717 y_cst = y;
3718
3719 if (!targetm.legitimate_constant_p (mode, y))
3720 {
3721 y = force_const_mem (mode, y);
3722
3723 /* If the target's cannot_force_const_mem prevented the spill,
3724 assume that the target's move expanders will also take care
3725 of the non-legitimate constant. */
3726 if (!y)
3727 y = y_cst;
3728 else
3729 y = use_anchored_address (y);
3730 }
3731 }
3732
3733 /* If X or Y are memory references, verify that their addresses are valid
3734 for the machine. */
3735 if (MEM_P (x)
3736 && (! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
3737 MEM_ADDR_SPACE (x))
3738 && ! push_operand (x, GET_MODE (x))))
3739 x = validize_mem (x);
3740
3741 if (MEM_P (y)
3742 && ! memory_address_addr_space_p (GET_MODE (y), XEXP (y, 0),
3743 MEM_ADDR_SPACE (y)))
3744 y = validize_mem (y);
3745
3746 gcc_assert (mode != BLKmode);
3747
3748 last_insn = emit_move_insn_1 (x, y);
3749
3750 if (y_cst && REG_P (x)
3751 && (set = single_set (last_insn)) != NULL_RTX
3752 && SET_DEST (set) == x
3753 && ! rtx_equal_p (y_cst, SET_SRC (set)))
3754 set_unique_reg_note (last_insn, REG_EQUAL, copy_rtx (y_cst));
3755
3756 return last_insn;
3757}
3758
3759/* Generate the body of an instruction to copy Y into X.
3760 It may be a list of insns, if one insn isn't enough. */
3761
3762rtx_insn *
3763gen_move_insn (rtx x, rtx y)
3764{
3765 rtx_insn *seq;
3766
3767 start_sequence ();
3768 emit_move_insn_1 (x, y);
3769 seq = get_insns ();
3770 end_sequence ();
3771 return seq;
3772}
3773
3774/* If Y is representable exactly in a narrower mode, and the target can
3775 perform the extension directly from constant or memory, then emit the
3776 move as an extension. */
3777
3778static rtx_insn *
3779compress_float_constant (rtx x, rtx y)
3780{
3781 machine_mode dstmode = GET_MODE (x);
3782 machine_mode orig_srcmode = GET_MODE (y);
3783 machine_mode srcmode;
3784 const REAL_VALUE_TYPE *r;
3785 int oldcost, newcost;
3786 bool speed = optimize_insn_for_speed_p ();
3787
3788 r = CONST_DOUBLE_REAL_VALUE (y);
3789
3790 if (targetm.legitimate_constant_p (dstmode, y))
3791 oldcost = set_src_cost (y, orig_srcmode, speed);
3792 else
3793 oldcost = set_src_cost (force_const_mem (dstmode, y), dstmode, speed);
3794
3795 FOR_EACH_MODE_UNTIL (srcmode, orig_srcmode)
3796 {
3797 enum insn_code ic;
3798 rtx trunc_y;
3799 rtx_insn *last_insn;
3800
3801 /* Skip if the target can't extend this way. */
3802 ic = can_extend_p (dstmode, srcmode, 0);
3803 if (ic == CODE_FOR_nothing)
3804 continue;
3805
3806 /* Skip if the narrowed value isn't exact. */
3807 if (! exact_real_truncate (srcmode, r))
3808 continue;
3809
3810 trunc_y = const_double_from_real_value (*r, srcmode);
3811
3812 if (targetm.legitimate_constant_p (srcmode, trunc_y))
3813 {
3814 /* Skip if the target needs extra instructions to perform
3815 the extension. */
3816 if (!insn_operand_matches (ic, 1, trunc_y))
3817 continue;
3818 /* This is valid, but may not be cheaper than the original. */
3819 newcost = set_src_cost (gen_rtx_FLOAT_EXTEND (dstmode, trunc_y),
3820 dstmode, speed);
3821 if (oldcost < newcost)
3822 continue;
3823 }
3824 else if (float_extend_from_mem[dstmode][srcmode])
3825 {
3826 trunc_y = force_const_mem (srcmode, trunc_y);
3827 /* This is valid, but may not be cheaper than the original. */
3828 newcost = set_src_cost (gen_rtx_FLOAT_EXTEND (dstmode, trunc_y),
3829 dstmode, speed);
3830 if (oldcost < newcost)
3831 continue;
3832 trunc_y = validize_mem (trunc_y);
3833 }
3834 else
3835 continue;
3836
3837 /* For CSE's benefit, force the compressed constant pool entry
3838 into a new pseudo. This constant may be used in different modes,
3839 and if not, combine will put things back together for us. */
3840 trunc_y = force_reg (srcmode, trunc_y);
3841
3842 /* If x is a hard register, perform the extension into a pseudo,
3843 so that e.g. stack realignment code is aware of it. */
3844 rtx target = x;
3845 if (REG_P (x) && HARD_REGISTER_P (x))
3846 target = gen_reg_rtx (dstmode);
3847
3848 emit_unop_insn (ic, target, trunc_y, UNKNOWN);
3849 last_insn = get_last_insn ();
3850
3851 if (REG_P (target))
3852 set_unique_reg_note (last_insn, REG_EQUAL, y);
3853
3854 if (target != x)
3855 return emit_move_insn (x, target);
3856 return last_insn;
3857 }
3858
3859 return NULL;
3860}
3861
3862/* Pushing data onto the stack. */
3863
3864/* Push a block of length SIZE (perhaps variable)
3865 and return an rtx to address the beginning of the block.
3866 The value may be virtual_outgoing_args_rtx.
3867
3868 EXTRA is the number of bytes of padding to push in addition to SIZE.
3869 BELOW nonzero means this padding comes at low addresses;
3870 otherwise, the padding comes at high addresses. */
3871
3872rtx
3873push_block (rtx size, int extra, int below)
3874{
3875 rtx temp;
3876
3877 size = convert_modes (Pmode, ptr_mode, size, 1);
3878 if (CONSTANT_P (size))
3879 anti_adjust_stack (plus_constant (Pmode, size, extra));
3880 else if (REG_P (size) && extra == 0)
3881 anti_adjust_stack (size);
3882 else
3883 {
3884 temp = copy_to_mode_reg (Pmode, size);
3885 if (extra != 0)
3886 temp = expand_binop (Pmode, add_optab, temp,
3887 gen_int_mode (extra, Pmode),
3888 temp, 0, OPTAB_LIB_WIDEN);
3889 anti_adjust_stack (temp);
3890 }
3891
3892 if (STACK_GROWS_DOWNWARD)
3893 {
3894 temp = virtual_outgoing_args_rtx;
3895 if (extra != 0 && below)
3896 temp = plus_constant (Pmode, temp, extra);
3897 }
3898 else
3899 {
3900 if (CONST_INT_P (size))
3901 temp = plus_constant (Pmode, virtual_outgoing_args_rtx,
3902 -INTVAL (size) - (below ? 0 : extra));
3903 else if (extra != 0 && !below)
3904 temp = gen_rtx_PLUS (Pmode, virtual_outgoing_args_rtx,
3905 negate_rtx (Pmode, plus_constant (Pmode, size,
3906 extra)));
3907 else
3908 temp = gen_rtx_PLUS (Pmode, virtual_outgoing_args_rtx,
3909 negate_rtx (Pmode, size));
3910 }
3911
3912 return memory_address (NARROWEST_INT_MODE, temp);
3913}
3914
3915/* A utility routine that returns the base of an auto-inc memory, or NULL. */
3916
3917static rtx
3918mem_autoinc_base (rtx mem)
3919{
3920 if (MEM_P (mem))
3921 {
3922 rtx addr = XEXP (mem, 0);
3923 if (GET_RTX_CLASS (GET_CODE (addr)) == RTX_AUTOINC)
3924 return XEXP (addr, 0);
3925 }
3926 return NULL;
3927}
3928
3929/* A utility routine used here, in reload, and in try_split. The insns
3930 after PREV up to and including LAST are known to adjust the stack,
3931 with a final value of END_ARGS_SIZE. Iterate backward from LAST
3932 placing notes as appropriate. PREV may be NULL, indicating the
3933 entire insn sequence prior to LAST should be scanned.
3934
3935 The set of allowed stack pointer modifications is small:
3936 (1) One or more auto-inc style memory references (aka pushes),
3937 (2) One or more addition/subtraction with the SP as destination,
3938 (3) A single move insn with the SP as destination,
3939 (4) A call_pop insn,
3940 (5) Noreturn call insns if !ACCUMULATE_OUTGOING_ARGS.
3941
3942 Insns in the sequence that do not modify the SP are ignored,
3943 except for noreturn calls.
3944
3945 The return value is the amount of adjustment that can be trivially
3946 verified, via immediate operand or auto-inc. If the adjustment
3947 cannot be trivially extracted, the return value is INT_MIN. */
3948
3949HOST_WIDE_INT
3950find_args_size_adjust (rtx_insn *insn)
3951{
3952 rtx dest, set, pat;
3953 int i;
3954
3955 pat = PATTERN (insn);
3956 set = NULL;
3957
3958 /* Look for a call_pop pattern. */
3959 if (CALL_P (insn))
3960 {
3961 /* We have to allow non-call_pop patterns for the case
3962 of emit_single_push_insn of a TLS address. */
3963 if (GET_CODE (pat) != PARALLEL)
3964 return 0;
3965
3966 /* All call_pop have a stack pointer adjust in the parallel.
3967 The call itself is always first, and the stack adjust is
3968 usually last, so search from the end. */
3969 for (i = XVECLEN (pat, 0) - 1; i > 0; --i)
3970 {
3971 set = XVECEXP (pat, 0, i);
3972 if (GET_CODE (set) != SET)
3973 continue;
3974 dest = SET_DEST (set);
3975 if (dest == stack_pointer_rtx)
3976 break;
3977 }
3978 /* We'd better have found the stack pointer adjust. */
3979 if (i == 0)
3980 return 0;
3981 /* Fall through to process the extracted SET and DEST
3982 as if it was a standalone insn. */
3983 }
3984 else if (GET_CODE (pat) == SET)
3985 set = pat;
3986 else if ((set = single_set (insn)) != NULL)
3987 ;
3988 else if (GET_CODE (pat) == PARALLEL)
3989 {
3990 /* ??? Some older ports use a parallel with a stack adjust
3991 and a store for a PUSH_ROUNDING pattern, rather than a
3992 PRE/POST_MODIFY rtx. Don't force them to update yet... */
3993 /* ??? See h8300 and m68k, pushqi1. */
3994 for (i = XVECLEN (pat, 0) - 1; i >= 0; --i)
3995 {
3996 set = XVECEXP (pat, 0, i);
3997 if (GET_CODE (set) != SET)
3998 continue;
3999 dest = SET_DEST (set);
4000 if (dest == stack_pointer_rtx)
4001 break;
4002
4003 /* We do not expect an auto-inc of the sp in the parallel. */
4004 gcc_checking_assert (mem_autoinc_base (dest) != stack_pointer_rtx);
4005 gcc_checking_assert (mem_autoinc_base (SET_SRC (set))
4006 != stack_pointer_rtx);
4007 }
4008 if (i < 0)
4009 return 0;
4010 }
4011 else
4012 return 0;
4013
4014 dest = SET_DEST (set);
4015
4016 /* Look for direct modifications of the stack pointer. */
4017 if (REG_P (dest) && REGNO (dest) == STACK_POINTER_REGNUM)
4018 {
4019 /* Look for a trivial adjustment, otherwise assume nothing. */
4020 /* Note that the SPU restore_stack_block pattern refers to
4021 the stack pointer in V4SImode. Consider that non-trivial. */
4022 if (SCALAR_INT_MODE_P (GET_MODE (dest))
4023 && GET_CODE (SET_SRC (set)) == PLUS
4024 && XEXP (SET_SRC (set), 0) == stack_pointer_rtx
4025 && CONST_INT_P (XEXP (SET_SRC (set), 1)))
4026 return INTVAL (XEXP (SET_SRC (set), 1));
4027 /* ??? Reload can generate no-op moves, which will be cleaned
4028 up later. Recognize it and continue searching. */
4029 else if (rtx_equal_p (dest, SET_SRC (set)))
4030 return 0;
4031 else
4032 return HOST_WIDE_INT_MIN;
4033 }
4034 else
4035 {
4036 rtx mem, addr;
4037
4038 /* Otherwise only think about autoinc patterns. */
4039 if (mem_autoinc_base (dest) == stack_pointer_rtx)
4040 {
4041 mem = dest;
4042 gcc_checking_assert (mem_autoinc_base (SET_SRC (set))
4043 != stack_pointer_rtx);
4044 }
4045 else if (mem_autoinc_base (SET_SRC (set)) == stack_pointer_rtx)
4046 mem = SET_SRC (set);
4047 else
4048 return 0;
4049
4050 addr = XEXP (mem, 0);
4051 switch (GET_CODE (addr))
4052 {
4053 case PRE_INC:
4054 case POST_INC:
4055 return GET_MODE_SIZE (GET_MODE (mem));
4056 case PRE_DEC:
4057 case POST_DEC:
4058 return -GET_MODE_SIZE (GET_MODE (mem));
4059 case PRE_MODIFY:
4060 case POST_MODIFY:
4061 addr = XEXP (addr, 1);
4062 gcc_assert (GET_CODE (addr) == PLUS);
4063 gcc_assert (XEXP (addr, 0) == stack_pointer_rtx);
4064 gcc_assert (CONST_INT_P (XEXP (addr, 1)));
4065 return INTVAL (XEXP (addr, 1));
4066 default:
4067 gcc_unreachable ();
4068 }
4069 }
4070}
4071
4072int
4073fixup_args_size_notes (rtx_insn *prev, rtx_insn *last, int end_args_size)
4074{
4075 int args_size = end_args_size;
4076 bool saw_unknown = false;
4077 rtx_insn *insn;
4078
4079 for (insn = last; insn != prev; insn = PREV_INSN (insn))
4080 {
4081 HOST_WIDE_INT this_delta;
4082
4083 if (!NONDEBUG_INSN_P (insn))
4084 continue;
4085
4086 this_delta = find_args_size_adjust (insn);
4087 if (this_delta == 0)
4088 {
4089 if (!CALL_P (insn)
4090 || ACCUMULATE_OUTGOING_ARGS
4091 || find_reg_note (insn, REG_NORETURN, NULL_RTX) == NULL_RTX)
4092 continue;
4093 }
4094
4095 gcc_assert (!saw_unknown);
4096 if (this_delta == HOST_WIDE_INT_MIN)
4097 saw_unknown = true;
4098
4099 add_reg_note (insn, REG_ARGS_SIZE, GEN_INT (args_size));
4100 if (STACK_GROWS_DOWNWARD)
4101 this_delta = -(unsigned HOST_WIDE_INT) this_delta;
4102
4103 if (saw_unknown)
4104 args_size = INT_MIN;
4105 else
4106 args_size -= this_delta;
4107 }
4108
4109 return args_size;
4110}
4111
4112#ifdef PUSH_ROUNDING
4113/* Emit single push insn. */
4114
4115static void
4116emit_single_push_insn_1 (machine_mode mode, rtx x, tree type)
4117{
4118 rtx dest_addr;
4119 unsigned rounded_size = PUSH_ROUNDING (GET_MODE_SIZE (mode));
4120 rtx dest;
4121 enum insn_code icode;
4122
4123