1/* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2017 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
10 version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21
22/* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
24 split.
25
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
33
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
37 allocations;
38 o some heuristics to choose insn alternative to improve the
39 inheritance;
40 o early clobbers etc.
41
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
45 changed.
46
47 There is special code for preventing all LRA and this pass cycling
48 in case of bugs.
49
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
54
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
57 traversal of EBBs.
58
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
62
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
65 ... => ...
66 reload_p2 <- p reload_p2 <- new_p
67
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
70 pseudo*.
71
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
75
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
82 insns.
83
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
86
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
89 ... =>
90 ... r <- s (new insn -- restore)
91 ... <- r ... <- r
92
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
95
96 Splitting is done:
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
101
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
106
107#undef REG_OK_STRICT
108
109#include "config.h"
110#include "system.h"
111#include "coretypes.h"
112#include "backend.h"
113#include "target.h"
114#include "rtl.h"
115#include "tree.h"
116#include "predict.h"
117#include "df.h"
118#include "memmodel.h"
119#include "tm_p.h"
120#include "expmed.h"
121#include "optabs.h"
122#include "regs.h"
123#include "ira.h"
124#include "recog.h"
125#include "output.h"
126#include "addresses.h"
127#include "expr.h"
128#include "cfgrtl.h"
129#include "rtl-error.h"
130#include "params.h"
131#include "lra.h"
132#include "lra-int.h"
133#include "print-rtl.h"
134
135/* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
136 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
137 reload insns. */
138static int bb_reload_num;
139
140/* The current insn being processed and corresponding its single set
141 (NULL otherwise), its data (basic block, the insn data, the insn
142 static data, and the mode of each operand). */
143static rtx_insn *curr_insn;
144static rtx curr_insn_set;
145static basic_block curr_bb;
146static lra_insn_recog_data_t curr_id;
147static struct lra_static_insn_data *curr_static_id;
148static machine_mode curr_operand_mode[MAX_RECOG_OPERANDS];
149/* Mode of the register substituted by its equivalence with VOIDmode
150 (e.g. constant) and whose subreg is given operand of the current
151 insn. VOIDmode in all other cases. */
152static machine_mode original_subreg_reg_mode[MAX_RECOG_OPERANDS];
153
154
155
156/* Start numbers for new registers and insns at the current constraints
157 pass start. */
158static int new_regno_start;
159static int new_insn_uid_start;
160
161/* If LOC is nonnull, strip any outer subreg from it. */
162static inline rtx *
163strip_subreg (rtx *loc)
164{
165 return loc && GET_CODE (*loc) == SUBREG ? &SUBREG_REG (*loc) : loc;
166}
167
168/* Return hard regno of REGNO or if it is was not assigned to a hard
169 register, use a hard register from its allocno class. */
170static int
171get_try_hard_regno (int regno)
172{
173 int hard_regno;
174 enum reg_class rclass;
175
176 if ((hard_regno = regno) >= FIRST_PSEUDO_REGISTER)
177 hard_regno = lra_get_regno_hard_regno (regno);
178 if (hard_regno >= 0)
179 return hard_regno;
180 rclass = lra_get_allocno_class (regno);
181 if (rclass == NO_REGS)
182 return -1;
183 return ira_class_hard_regs[rclass][0];
184}
185
186/* Return the hard regno of X after removing its subreg. If X is not
187 a register or a subreg of a register, return -1. If X is a pseudo,
188 use its assignment. If FINAL_P return the final hard regno which will
189 be after elimination. */
190static int
191get_hard_regno (rtx x, bool final_p)
192{
193 rtx reg;
194 int hard_regno;
195
196 reg = x;
197 if (SUBREG_P (x))
198 reg = SUBREG_REG (x);
199 if (! REG_P (reg))
200 return -1;
201 if (! HARD_REGISTER_NUM_P (hard_regno = REGNO (reg)))
202 hard_regno = lra_get_regno_hard_regno (hard_regno);
203 if (hard_regno < 0)
204 return -1;
205 if (final_p)
206 hard_regno = lra_get_elimination_hard_regno (hard_regno);
207 if (SUBREG_P (x))
208 hard_regno += subreg_regno_offset (hard_regno, GET_MODE (reg),
209 SUBREG_BYTE (x), GET_MODE (x));
210 return hard_regno;
211}
212
213/* If REGNO is a hard register or has been allocated a hard register,
214 return the class of that register. If REGNO is a reload pseudo
215 created by the current constraints pass, return its allocno class.
216 Return NO_REGS otherwise. */
217static enum reg_class
218get_reg_class (int regno)
219{
220 int hard_regno;
221
222 if (! HARD_REGISTER_NUM_P (hard_regno = regno))
223 hard_regno = lra_get_regno_hard_regno (regno);
224 if (hard_regno >= 0)
225 {
226 hard_regno = lra_get_elimination_hard_regno (hard_regno);
227 return REGNO_REG_CLASS (hard_regno);
228 }
229 if (regno >= new_regno_start)
230 return lra_get_allocno_class (regno);
231 return NO_REGS;
232}
233
234/* Return true if REG satisfies (or will satisfy) reg class constraint
235 CL. Use elimination first if REG is a hard register. If REG is a
236 reload pseudo created by this constraints pass, assume that it will
237 be allocated a hard register from its allocno class, but allow that
238 class to be narrowed to CL if it is currently a superset of CL.
239
240 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
241 REGNO (reg), or NO_REGS if no change in its class was needed. */
242static bool
243in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class)
244{
245 enum reg_class rclass, common_class;
246 machine_mode reg_mode;
247 int class_size, hard_regno, nregs, i, j;
248 int regno = REGNO (reg);
249
250 if (new_class != NULL)
251 *new_class = NO_REGS;
252 if (regno < FIRST_PSEUDO_REGISTER)
253 {
254 rtx final_reg = reg;
255 rtx *final_loc = &final_reg;
256
257 lra_eliminate_reg_if_possible (final_loc);
258 return TEST_HARD_REG_BIT (reg_class_contents[cl], REGNO (*final_loc));
259 }
260 reg_mode = GET_MODE (reg);
261 rclass = get_reg_class (regno);
262 if (regno < new_regno_start
263 /* Do not allow the constraints for reload instructions to
264 influence the classes of new pseudos. These reloads are
265 typically moves that have many alternatives, and restricting
266 reload pseudos for one alternative may lead to situations
267 where other reload pseudos are no longer allocatable. */
268 || (INSN_UID (curr_insn) >= new_insn_uid_start
269 && curr_insn_set != NULL
270 && ((OBJECT_P (SET_SRC (curr_insn_set))
271 && ! CONSTANT_P (SET_SRC (curr_insn_set)))
272 || (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG
273 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set)))
274 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set)))))))
275 /* When we don't know what class will be used finally for reload
276 pseudos, we use ALL_REGS. */
277 return ((regno >= new_regno_start && rclass == ALL_REGS)
278 || (rclass != NO_REGS && ira_class_subset_p[rclass][cl]
279 && ! hard_reg_set_subset_p (reg_class_contents[cl],
280 lra_no_alloc_regs)));
281 else
282 {
283 common_class = ira_reg_class_subset[rclass][cl];
284 if (new_class != NULL)
285 *new_class = common_class;
286 if (hard_reg_set_subset_p (reg_class_contents[common_class],
287 lra_no_alloc_regs))
288 return false;
289 /* Check that there are enough allocatable regs. */
290 class_size = ira_class_hard_regs_num[common_class];
291 for (i = 0; i < class_size; i++)
292 {
293 hard_regno = ira_class_hard_regs[common_class][i];
294 nregs = hard_regno_nregs (hard_regno, reg_mode);
295 if (nregs == 1)
296 return true;
297 for (j = 0; j < nregs; j++)
298 if (TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno + j)
299 || ! TEST_HARD_REG_BIT (reg_class_contents[common_class],
300 hard_regno + j))
301 break;
302 if (j >= nregs)
303 return true;
304 }
305 return false;
306 }
307}
308
309/* Return true if REGNO satisfies a memory constraint. */
310static bool
311in_mem_p (int regno)
312{
313 return get_reg_class (regno) == NO_REGS;
314}
315
316/* Return 1 if ADDR is a valid memory address for mode MODE in address
317 space AS, and check that each pseudo has the proper kind of hard
318 reg. */
319static int
320valid_address_p (machine_mode mode ATTRIBUTE_UNUSED,
321 rtx addr, addr_space_t as)
322{
323#ifdef GO_IF_LEGITIMATE_ADDRESS
324 lra_assert (ADDR_SPACE_GENERIC_P (as));
325 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
326 return 0;
327
328 win:
329 return 1;
330#else
331 return targetm.addr_space.legitimate_address_p (mode, addr, 0, as);
332#endif
333}
334
335namespace {
336 /* Temporarily eliminates registers in an address (for the lifetime of
337 the object). */
338 class address_eliminator {
339 public:
340 address_eliminator (struct address_info *ad);
341 ~address_eliminator ();
342
343 private:
344 struct address_info *m_ad;
345 rtx *m_base_loc;
346 rtx m_base_reg;
347 rtx *m_index_loc;
348 rtx m_index_reg;
349 };
350}
351
352address_eliminator::address_eliminator (struct address_info *ad)
353 : m_ad (ad),
354 m_base_loc (strip_subreg (ad->base_term)),
355 m_base_reg (NULL_RTX),
356 m_index_loc (strip_subreg (ad->index_term)),
357 m_index_reg (NULL_RTX)
358{
359 if (m_base_loc != NULL)
360 {
361 m_base_reg = *m_base_loc;
362 lra_eliminate_reg_if_possible (m_base_loc);
363 if (m_ad->base_term2 != NULL)
364 *m_ad->base_term2 = *m_ad->base_term;
365 }
366 if (m_index_loc != NULL)
367 {
368 m_index_reg = *m_index_loc;
369 lra_eliminate_reg_if_possible (m_index_loc);
370 }
371}
372
373address_eliminator::~address_eliminator ()
374{
375 if (m_base_loc && *m_base_loc != m_base_reg)
376 {
377 *m_base_loc = m_base_reg;
378 if (m_ad->base_term2 != NULL)
379 *m_ad->base_term2 = *m_ad->base_term;
380 }
381 if (m_index_loc && *m_index_loc != m_index_reg)
382 *m_index_loc = m_index_reg;
383}
384
385/* Return true if the eliminated form of AD is a legitimate target address. */
386static bool
387valid_address_p (struct address_info *ad)
388{
389 address_eliminator eliminator (ad);
390 return valid_address_p (ad->mode, *ad->outer, ad->as);
391}
392
393/* Return true if the eliminated form of memory reference OP satisfies
394 extra (special) memory constraint CONSTRAINT. */
395static bool
396satisfies_memory_constraint_p (rtx op, enum constraint_num constraint)
397{
398 struct address_info ad;
399
400 decompose_mem_address (&ad, op);
401 address_eliminator eliminator (&ad);
402 return constraint_satisfied_p (op, constraint);
403}
404
405/* Return true if the eliminated form of address AD satisfies extra
406 address constraint CONSTRAINT. */
407static bool
408satisfies_address_constraint_p (struct address_info *ad,
409 enum constraint_num constraint)
410{
411 address_eliminator eliminator (ad);
412 return constraint_satisfied_p (*ad->outer, constraint);
413}
414
415/* Return true if the eliminated form of address OP satisfies extra
416 address constraint CONSTRAINT. */
417static bool
418satisfies_address_constraint_p (rtx op, enum constraint_num constraint)
419{
420 struct address_info ad;
421
422 decompose_lea_address (&ad, &op);
423 return satisfies_address_constraint_p (&ad, constraint);
424}
425
426/* Initiate equivalences for LRA. As we keep original equivalences
427 before any elimination, we need to make copies otherwise any change
428 in insns might change the equivalences. */
429void
430lra_init_equiv (void)
431{
432 ira_expand_reg_equiv ();
433 for (int i = FIRST_PSEUDO_REGISTER; i < max_reg_num (); i++)
434 {
435 rtx res;
436
437 if ((res = ira_reg_equiv[i].memory) != NULL_RTX)
438 ira_reg_equiv[i].memory = copy_rtx (res);
439 if ((res = ira_reg_equiv[i].invariant) != NULL_RTX)
440 ira_reg_equiv[i].invariant = copy_rtx (res);
441 }
442}
443
444static rtx loc_equivalence_callback (rtx, const_rtx, void *);
445
446/* Update equivalence for REGNO. We need to this as the equivalence
447 might contain other pseudos which are changed by their
448 equivalences. */
449static void
450update_equiv (int regno)
451{
452 rtx x;
453
454 if ((x = ira_reg_equiv[regno].memory) != NULL_RTX)
455 ira_reg_equiv[regno].memory
456 = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback,
457 NULL_RTX);
458 if ((x = ira_reg_equiv[regno].invariant) != NULL_RTX)
459 ira_reg_equiv[regno].invariant
460 = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback,
461 NULL_RTX);
462}
463
464/* If we have decided to substitute X with another value, return that
465 value, otherwise return X. */
466static rtx
467get_equiv (rtx x)
468{
469 int regno;
470 rtx res;
471
472 if (! REG_P (x) || (regno = REGNO (x)) < FIRST_PSEUDO_REGISTER
473 || ! ira_reg_equiv[regno].defined_p
474 || ! ira_reg_equiv[regno].profitable_p
475 || lra_get_regno_hard_regno (regno) >= 0)
476 return x;
477 if ((res = ira_reg_equiv[regno].memory) != NULL_RTX)
478 {
479 if (targetm.cannot_substitute_mem_equiv_p (res))
480 return x;
481 return res;
482 }
483 if ((res = ira_reg_equiv[regno].constant) != NULL_RTX)
484 return res;
485 if ((res = ira_reg_equiv[regno].invariant) != NULL_RTX)
486 return res;
487 gcc_unreachable ();
488}
489
490/* If we have decided to substitute X with the equivalent value,
491 return that value after elimination for INSN, otherwise return
492 X. */
493static rtx
494get_equiv_with_elimination (rtx x, rtx_insn *insn)
495{
496 rtx res = get_equiv (x);
497
498 if (x == res || CONSTANT_P (res))
499 return res;
500 return lra_eliminate_regs_1 (insn, res, GET_MODE (res),
501 false, false, 0, true);
502}
503
504/* Set up curr_operand_mode. */
505static void
506init_curr_operand_mode (void)
507{
508 int nop = curr_static_id->n_operands;
509 for (int i = 0; i < nop; i++)
510 {
511 machine_mode mode = GET_MODE (*curr_id->operand_loc[i]);
512 if (mode == VOIDmode)
513 {
514 /* The .md mode for address operands is the mode of the
515 addressed value rather than the mode of the address itself. */
516 if (curr_id->icode >= 0 && curr_static_id->operand[i].is_address)
517 mode = Pmode;
518 else
519 mode = curr_static_id->operand[i].mode;
520 }
521 curr_operand_mode[i] = mode;
522 }
523}
524
525
526
527/* The page contains code to reuse input reloads. */
528
529/* Structure describes input reload of the current insns. */
530struct input_reload
531{
532 /* True for input reload of matched operands. */
533 bool match_p;
534 /* Reloaded value. */
535 rtx input;
536 /* Reload pseudo used. */
537 rtx reg;
538};
539
540/* The number of elements in the following array. */
541static int curr_insn_input_reloads_num;
542/* Array containing info about input reloads. It is used to find the
543 same input reload and reuse the reload pseudo in this case. */
544static struct input_reload curr_insn_input_reloads[LRA_MAX_INSN_RELOADS];
545
546/* Initiate data concerning reuse of input reloads for the current
547 insn. */
548static void
549init_curr_insn_input_reloads (void)
550{
551 curr_insn_input_reloads_num = 0;
552}
553
554/* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
555 created input reload pseudo (only if TYPE is not OP_OUT). Don't
556 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
557 wrapped up in SUBREG. The result pseudo is returned through
558 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
559 reused the already created input reload pseudo. Use TITLE to
560 describe new registers for debug purposes. */
561static bool
562get_reload_reg (enum op_type type, machine_mode mode, rtx original,
563 enum reg_class rclass, bool in_subreg_p,
564 const char *title, rtx *result_reg)
565{
566 int i, regno;
567 enum reg_class new_class;
568 bool unique_p = false;
569
570 if (type == OP_OUT)
571 {
572 *result_reg
573 = lra_create_new_reg_with_unique_value (mode, original, rclass, title);
574 return true;
575 }
576 /* Prevent reuse value of expression with side effects,
577 e.g. volatile memory. */
578 if (! side_effects_p (original))
579 for (i = 0; i < curr_insn_input_reloads_num; i++)
580 {
581 if (! curr_insn_input_reloads[i].match_p
582 && rtx_equal_p (curr_insn_input_reloads[i].input, original)
583 && in_class_p (curr_insn_input_reloads[i].reg, rclass, &new_class))
584 {
585 rtx reg = curr_insn_input_reloads[i].reg;
586 regno = REGNO (reg);
587 /* If input is equal to original and both are VOIDmode,
588 GET_MODE (reg) might be still different from mode.
589 Ensure we don't return *result_reg with wrong mode. */
590 if (GET_MODE (reg) != mode)
591 {
592 if (in_subreg_p)
593 continue;
594 if (GET_MODE_SIZE (GET_MODE (reg)) < GET_MODE_SIZE (mode))
595 continue;
596 reg = lowpart_subreg (mode, reg, GET_MODE (reg));
597 if (reg == NULL_RTX || GET_CODE (reg) != SUBREG)
598 continue;
599 }
600 *result_reg = reg;
601 if (lra_dump_file != NULL)
602 {
603 fprintf (lra_dump_file, " Reuse r%d for reload ", regno);
604 dump_value_slim (lra_dump_file, original, 1);
605 }
606 if (new_class != lra_get_allocno_class (regno))
607 lra_change_class (regno, new_class, ", change to", false);
608 if (lra_dump_file != NULL)
609 fprintf (lra_dump_file, "\n");
610 return false;
611 }
612 /* If we have an input reload with a different mode, make sure it
613 will get a different hard reg. */
614 else if (REG_P (original)
615 && REG_P (curr_insn_input_reloads[i].input)
616 && REGNO (original) == REGNO (curr_insn_input_reloads[i].input)
617 && (GET_MODE (original)
618 != GET_MODE (curr_insn_input_reloads[i].input)))
619 unique_p = true;
620 }
621 *result_reg = (unique_p
622 ? lra_create_new_reg_with_unique_value
623 : lra_create_new_reg) (mode, original, rclass, title);
624 lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS);
625 curr_insn_input_reloads[curr_insn_input_reloads_num].input = original;
626 curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = false;
627 curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = *result_reg;
628 return true;
629}
630
631
632
633/* The page contains code to extract memory address parts. */
634
635/* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
636static inline bool
637ok_for_index_p_nonstrict (rtx reg)
638{
639 unsigned regno = REGNO (reg);
640
641 return regno >= FIRST_PSEUDO_REGISTER || REGNO_OK_FOR_INDEX_P (regno);
642}
643
644/* A version of regno_ok_for_base_p for use here, when all pseudos
645 should count as OK. Arguments as for regno_ok_for_base_p. */
646static inline bool
647ok_for_base_p_nonstrict (rtx reg, machine_mode mode, addr_space_t as,
648 enum rtx_code outer_code, enum rtx_code index_code)
649{
650 unsigned regno = REGNO (reg);
651
652 if (regno >= FIRST_PSEUDO_REGISTER)
653 return true;
654 return ok_for_base_p_1 (regno, mode, as, outer_code, index_code);
655}
656
657
658
659/* The page contains major code to choose the current insn alternative
660 and generate reloads for it. */
661
662/* Return the offset from REGNO of the least significant register
663 in (reg:MODE REGNO).
664
665 This function is used to tell whether two registers satisfy
666 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
667
668 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
669 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
670int
671lra_constraint_offset (int regno, machine_mode mode)
672{
673 lra_assert (regno < FIRST_PSEUDO_REGISTER);
674
675 scalar_int_mode int_mode;
676 if (WORDS_BIG_ENDIAN
677 && is_a <scalar_int_mode> (mode, &int_mode)
678 && GET_MODE_SIZE (int_mode) > UNITS_PER_WORD)
679 return hard_regno_nregs (regno, mode) - 1;
680 return 0;
681}
682
683/* Like rtx_equal_p except that it allows a REG and a SUBREG to match
684 if they are the same hard reg, and has special hacks for
685 auto-increment and auto-decrement. This is specifically intended for
686 process_alt_operands to use in determining whether two operands
687 match. X is the operand whose number is the lower of the two.
688
689 It is supposed that X is the output operand and Y is the input
690 operand. Y_HARD_REGNO is the final hard regno of register Y or
691 register in subreg Y as we know it now. Otherwise, it is a
692 negative value. */
693static bool
694operands_match_p (rtx x, rtx y, int y_hard_regno)
695{
696 int i;
697 RTX_CODE code = GET_CODE (x);
698 const char *fmt;
699
700 if (x == y)
701 return true;
702 if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x))))
703 && (REG_P (y) || (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)))))
704 {
705 int j;
706
707 i = get_hard_regno (x, false);
708 if (i < 0)
709 goto slow;
710
711 if ((j = y_hard_regno) < 0)
712 goto slow;
713
714 i += lra_constraint_offset (i, GET_MODE (x));
715 j += lra_constraint_offset (j, GET_MODE (y));
716
717 return i == j;
718 }
719
720 /* If two operands must match, because they are really a single
721 operand of an assembler insn, then two post-increments are invalid
722 because the assembler insn would increment only once. On the
723 other hand, a post-increment matches ordinary indexing if the
724 post-increment is the output operand. */
725 if (code == POST_DEC || code == POST_INC || code == POST_MODIFY)
726 return operands_match_p (XEXP (x, 0), y, y_hard_regno);
727
728 /* Two pre-increments are invalid because the assembler insn would
729 increment only once. On the other hand, a pre-increment matches
730 ordinary indexing if the pre-increment is the input operand. */
731 if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC
732 || GET_CODE (y) == PRE_MODIFY)
733 return operands_match_p (x, XEXP (y, 0), -1);
734
735 slow:
736
737 if (code == REG && REG_P (y))
738 return REGNO (x) == REGNO (y);
739
740 if (code == REG && GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))
741 && x == SUBREG_REG (y))
742 return true;
743 if (GET_CODE (y) == REG && code == SUBREG && REG_P (SUBREG_REG (x))
744 && SUBREG_REG (x) == y)
745 return true;
746
747 /* Now we have disposed of all the cases in which different rtx
748 codes can match. */
749 if (code != GET_CODE (y))
750 return false;
751
752 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
753 if (GET_MODE (x) != GET_MODE (y))
754 return false;
755
756 switch (code)
757 {
758 CASE_CONST_UNIQUE:
759 return false;
760
761 case LABEL_REF:
762 return label_ref_label (x) == label_ref_label (y);
763 case SYMBOL_REF:
764 return XSTR (x, 0) == XSTR (y, 0);
765
766 default:
767 break;
768 }
769
770 /* Compare the elements. If any pair of corresponding elements fail
771 to match, return false for the whole things. */
772
773 fmt = GET_RTX_FORMAT (code);
774 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
775 {
776 int val, j;
777 switch (fmt[i])
778 {
779 case 'w':
780 if (XWINT (x, i) != XWINT (y, i))
781 return false;
782 break;
783
784 case 'i':
785 if (XINT (x, i) != XINT (y, i))
786 return false;
787 break;
788
789 case 'e':
790 val = operands_match_p (XEXP (x, i), XEXP (y, i), -1);
791 if (val == 0)
792 return false;
793 break;
794
795 case '0':
796 break;
797
798 case 'E':
799 if (XVECLEN (x, i) != XVECLEN (y, i))
800 return false;
801 for (j = XVECLEN (x, i) - 1; j >= 0; --j)
802 {
803 val = operands_match_p (XVECEXP (x, i, j), XVECEXP (y, i, j), -1);
804 if (val == 0)
805 return false;
806 }
807 break;
808
809 /* It is believed that rtx's at this level will never
810 contain anything but integers and other rtx's, except for
811 within LABEL_REFs and SYMBOL_REFs. */
812 default:
813 gcc_unreachable ();
814 }
815 }
816 return true;
817}
818
819/* True if X is a constant that can be forced into the constant pool.
820 MODE is the mode of the operand, or VOIDmode if not known. */
821#define CONST_POOL_OK_P(MODE, X) \
822 ((MODE) != VOIDmode \
823 && CONSTANT_P (X) \
824 && GET_CODE (X) != HIGH \
825 && !targetm.cannot_force_const_mem (MODE, X))
826
827/* True if C is a non-empty register class that has too few registers
828 to be safely used as a reload target class. */
829#define SMALL_REGISTER_CLASS_P(C) \
830 (ira_class_hard_regs_num [(C)] == 1 \
831 || (ira_class_hard_regs_num [(C)] >= 1 \
832 && targetm.class_likely_spilled_p (C)))
833
834/* If REG is a reload pseudo, try to make its class satisfying CL. */
835static void
836narrow_reload_pseudo_class (rtx reg, enum reg_class cl)
837{
838 enum reg_class rclass;
839
840 /* Do not make more accurate class from reloads generated. They are
841 mostly moves with a lot of constraints. Making more accurate
842 class may results in very narrow class and impossibility of find
843 registers for several reloads of one insn. */
844 if (INSN_UID (curr_insn) >= new_insn_uid_start)
845 return;
846 if (GET_CODE (reg) == SUBREG)
847 reg = SUBREG_REG (reg);
848 if (! REG_P (reg) || (int) REGNO (reg) < new_regno_start)
849 return;
850 if (in_class_p (reg, cl, &rclass) && rclass != cl)
851 lra_change_class (REGNO (reg), rclass, " Change to", true);
852}
853
854/* Searches X for any reference to a reg with the same value as REGNO,
855 returning the rtx of the reference found if any. Otherwise,
856 returns NULL_RTX. */
857static rtx
858regno_val_use_in (unsigned int regno, rtx x)
859{
860 const char *fmt;
861 int i, j;
862 rtx tem;
863
864 if (REG_P (x) && lra_reg_info[REGNO (x)].val == lra_reg_info[regno].val)
865 return x;
866
867 fmt = GET_RTX_FORMAT (GET_CODE (x));
868 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
869 {
870 if (fmt[i] == 'e')
871 {
872 if ((tem = regno_val_use_in (regno, XEXP (x, i))))
873 return tem;
874 }
875 else if (fmt[i] == 'E')
876 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
877 if ((tem = regno_val_use_in (regno , XVECEXP (x, i, j))))
878 return tem;
879 }
880
881 return NULL_RTX;
882}
883
884/* Return true if all current insn non-output operands except INS (it
885 has a negaitve end marker) do not use pseudos with the same value
886 as REGNO. */
887static bool
888check_conflict_input_operands (int regno, signed char *ins)
889{
890 int in;
891 int n_operands = curr_static_id->n_operands;
892
893 for (int nop = 0; nop < n_operands; nop++)
894 if (! curr_static_id->operand[nop].is_operator
895 && curr_static_id->operand[nop].type != OP_OUT)
896 {
897 for (int i = 0; (in = ins[i]) >= 0; i++)
898 if (in == nop)
899 break;
900 if (in < 0
901 && regno_val_use_in (regno, *curr_id->operand_loc[nop]) != NULL_RTX)
902 return false;
903 }
904 return true;
905}
906
907/* Generate reloads for matching OUT and INS (array of input operand
908 numbers with end marker -1) with reg class GOAL_CLASS, considering
909 output operands OUTS (similar array to INS) needing to be in different
910 registers. Add input and output reloads correspondingly to the lists
911 *BEFORE and *AFTER. OUT might be negative. In this case we generate
912 input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag
913 that the output operand is early clobbered for chosen alternative. */
914static void
915match_reload (signed char out, signed char *ins, signed char *outs,
916 enum reg_class goal_class, rtx_insn **before,
917 rtx_insn **after, bool early_clobber_p)
918{
919 bool out_conflict;
920 int i, in;
921 rtx new_in_reg, new_out_reg, reg;
922 machine_mode inmode, outmode;
923 rtx in_rtx = *curr_id->operand_loc[ins[0]];
924 rtx out_rtx = out < 0 ? in_rtx : *curr_id->operand_loc[out];
925
926 inmode = curr_operand_mode[ins[0]];
927 outmode = out < 0 ? inmode : curr_operand_mode[out];
928 push_to_sequence (*before);
929 if (inmode != outmode)
930 {
931 if (partial_subreg_p (outmode, inmode))
932 {
933 reg = new_in_reg
934 = lra_create_new_reg_with_unique_value (inmode, in_rtx,
935 goal_class, "");
936 if (SCALAR_INT_MODE_P (inmode))
937 new_out_reg = gen_lowpart_SUBREG (outmode, reg);
938 else
939 new_out_reg = gen_rtx_SUBREG (outmode, reg, 0);
940 LRA_SUBREG_P (new_out_reg) = 1;
941 /* If the input reg is dying here, we can use the same hard
942 register for REG and IN_RTX. We do it only for original
943 pseudos as reload pseudos can die although original
944 pseudos still live where reload pseudos dies. */
945 if (REG_P (in_rtx) && (int) REGNO (in_rtx) < lra_new_regno_start
946 && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx))
947 && (!early_clobber_p
948 || check_conflict_input_operands(REGNO (in_rtx), ins)))
949 lra_assign_reg_val (REGNO (in_rtx), REGNO (reg));
950 }
951 else
952 {
953 reg = new_out_reg
954 = lra_create_new_reg_with_unique_value (outmode, out_rtx,
955 goal_class, "");
956 if (SCALAR_INT_MODE_P (outmode))
957 new_in_reg = gen_lowpart_SUBREG (inmode, reg);
958 else
959 new_in_reg = gen_rtx_SUBREG (inmode, reg, 0);
960 /* NEW_IN_REG is non-paradoxical subreg. We don't want
961 NEW_OUT_REG living above. We add clobber clause for
962 this. This is just a temporary clobber. We can remove
963 it at the end of LRA work. */
964 rtx_insn *clobber = emit_clobber (new_out_reg);
965 LRA_TEMP_CLOBBER_P (PATTERN (clobber)) = 1;
966 LRA_SUBREG_P (new_in_reg) = 1;
967 if (GET_CODE (in_rtx) == SUBREG)
968 {
969 rtx subreg_reg = SUBREG_REG (in_rtx);
970
971 /* If SUBREG_REG is dying here and sub-registers IN_RTX
972 and NEW_IN_REG are similar, we can use the same hard
973 register for REG and SUBREG_REG. */
974 if (REG_P (subreg_reg)
975 && (int) REGNO (subreg_reg) < lra_new_regno_start
976 && GET_MODE (subreg_reg) == outmode
977 && SUBREG_BYTE (in_rtx) == SUBREG_BYTE (new_in_reg)
978 && find_regno_note (curr_insn, REG_DEAD, REGNO (subreg_reg))
979 && (! early_clobber_p
980 || check_conflict_input_operands (REGNO (subreg_reg),
981 ins)))
982 lra_assign_reg_val (REGNO (subreg_reg), REGNO (reg));
983 }
984 }
985 }
986 else
987 {
988 /* Pseudos have values -- see comments for lra_reg_info.
989 Different pseudos with the same value do not conflict even if
990 they live in the same place. When we create a pseudo we
991 assign value of original pseudo (if any) from which we
992 created the new pseudo. If we create the pseudo from the
993 input pseudo, the new pseudo will have no conflict with the
994 input pseudo which is wrong when the input pseudo lives after
995 the insn and as the new pseudo value is changed by the insn
996 output. Therefore we create the new pseudo from the output
997 except the case when we have single matched dying input
998 pseudo.
999
1000 We cannot reuse the current output register because we might
1001 have a situation like "a <- a op b", where the constraints
1002 force the second input operand ("b") to match the output
1003 operand ("a"). "b" must then be copied into a new register
1004 so that it doesn't clobber the current value of "a".
1005
1006 We can not use the same value if the output pseudo is
1007 early clobbered or the input pseudo is mentioned in the
1008 output, e.g. as an address part in memory, because
1009 output reload will actually extend the pseudo liveness.
1010 We don't care about eliminable hard regs here as we are
1011 interesting only in pseudos. */
1012
1013 /* Matching input's register value is the same as one of the other
1014 output operand. Output operands in a parallel insn must be in
1015 different registers. */
1016 out_conflict = false;
1017 if (REG_P (in_rtx))
1018 {
1019 for (i = 0; outs[i] >= 0; i++)
1020 {
1021 rtx other_out_rtx = *curr_id->operand_loc[outs[i]];
1022 if (REG_P (other_out_rtx)
1023 && (regno_val_use_in (REGNO (in_rtx), other_out_rtx)
1024 != NULL_RTX))
1025 {
1026 out_conflict = true;
1027 break;
1028 }
1029 }
1030 }
1031
1032 new_in_reg = new_out_reg
1033 = (! early_clobber_p && ins[1] < 0 && REG_P (in_rtx)
1034 && (int) REGNO (in_rtx) < lra_new_regno_start
1035 && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx))
1036 && (! early_clobber_p
1037 || check_conflict_input_operands (REGNO (in_rtx), ins))
1038 && (out < 0
1039 || regno_val_use_in (REGNO (in_rtx), out_rtx) == NULL_RTX)
1040 && !out_conflict
1041 ? lra_create_new_reg (inmode, in_rtx, goal_class, "")
1042 : lra_create_new_reg_with_unique_value (outmode, out_rtx,
1043 goal_class, ""));
1044 }
1045 /* In operand can be got from transformations before processing insn
1046 constraints. One example of such transformations is subreg
1047 reloading (see function simplify_operand_subreg). The new
1048 pseudos created by the transformations might have inaccurate
1049 class (ALL_REGS) and we should make their classes more
1050 accurate. */
1051 narrow_reload_pseudo_class (in_rtx, goal_class);
1052 lra_emit_move (copy_rtx (new_in_reg), in_rtx);
1053 *before = get_insns ();
1054 end_sequence ();
1055 /* Add the new pseudo to consider values of subsequent input reload
1056 pseudos. */
1057 lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS);
1058 curr_insn_input_reloads[curr_insn_input_reloads_num].input = in_rtx;
1059 curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = true;
1060 curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = new_in_reg;
1061 for (i = 0; (in = ins[i]) >= 0; i++)
1062 {
1063 lra_assert
1064 (GET_MODE (*curr_id->operand_loc[in]) == VOIDmode
1065 || GET_MODE (new_in_reg) == GET_MODE (*curr_id->operand_loc[in]));
1066 *curr_id->operand_loc[in] = new_in_reg;
1067 }
1068 lra_update_dups (curr_id, ins);
1069 if (out < 0)
1070 return;
1071 /* See a comment for the input operand above. */
1072 narrow_reload_pseudo_class (out_rtx, goal_class);
1073 if (find_reg_note (curr_insn, REG_UNUSED, out_rtx) == NULL_RTX)
1074 {
1075 start_sequence ();
1076 lra_emit_move (out_rtx, copy_rtx (new_out_reg));
1077 emit_insn (*after);
1078 *after = get_insns ();
1079 end_sequence ();
1080 }
1081 *curr_id->operand_loc[out] = new_out_reg;
1082 lra_update_dup (curr_id, out);
1083}
1084
1085/* Return register class which is union of all reg classes in insn
1086 constraint alternative string starting with P. */
1087static enum reg_class
1088reg_class_from_constraints (const char *p)
1089{
1090 int c, len;
1091 enum reg_class op_class = NO_REGS;
1092
1093 do
1094 switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c)
1095 {
1096 case '#':
1097 case ',':
1098 return op_class;
1099
1100 case 'g':
1101 op_class = reg_class_subunion[op_class][GENERAL_REGS];
1102 break;
1103
1104 default:
1105 enum constraint_num cn = lookup_constraint (p);
1106 enum reg_class cl = reg_class_for_constraint (cn);
1107 if (cl == NO_REGS)
1108 {
1109 if (insn_extra_address_constraint (cn))
1110 op_class
1111 = (reg_class_subunion
1112 [op_class][base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
1113 ADDRESS, SCRATCH)]);
1114 break;
1115 }
1116
1117 op_class = reg_class_subunion[op_class][cl];
1118 break;
1119 }
1120 while ((p += len), c);
1121 return op_class;
1122}
1123
1124/* If OP is a register, return the class of the register as per
1125 get_reg_class, otherwise return NO_REGS. */
1126static inline enum reg_class
1127get_op_class (rtx op)
1128{
1129 return REG_P (op) ? get_reg_class (REGNO (op)) : NO_REGS;
1130}
1131
1132/* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1133 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1134 SUBREG for VAL to make them equal. */
1135static rtx_insn *
1136emit_spill_move (bool to_p, rtx mem_pseudo, rtx val)
1137{
1138 if (GET_MODE (mem_pseudo) != GET_MODE (val))
1139 {
1140 /* Usually size of mem_pseudo is greater than val size but in
1141 rare cases it can be less as it can be defined by target
1142 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1143 if (! MEM_P (val))
1144 {
1145 val = gen_lowpart_SUBREG (GET_MODE (mem_pseudo),
1146 GET_CODE (val) == SUBREG
1147 ? SUBREG_REG (val) : val);
1148 LRA_SUBREG_P (val) = 1;
1149 }
1150 else
1151 {
1152 mem_pseudo = gen_lowpart_SUBREG (GET_MODE (val), mem_pseudo);
1153 LRA_SUBREG_P (mem_pseudo) = 1;
1154 }
1155 }
1156 return to_p ? gen_move_insn (mem_pseudo, val)
1157 : gen_move_insn (val, mem_pseudo);
1158}
1159
1160/* Process a special case insn (register move), return true if we
1161 don't need to process it anymore. INSN should be a single set
1162 insn. Set up that RTL was changed through CHANGE_P and that hook
1163 TARGET_SECONDARY_MEMORY_NEEDED says to use secondary memory through
1164 SEC_MEM_P. */
1165static bool
1166check_and_process_move (bool *change_p, bool *sec_mem_p ATTRIBUTE_UNUSED)
1167{
1168 int sregno, dregno;
1169 rtx dest, src, dreg, sreg, new_reg, scratch_reg;
1170 rtx_insn *before;
1171 enum reg_class dclass, sclass, secondary_class;
1172 secondary_reload_info sri;
1173
1174 lra_assert (curr_insn_set != NULL_RTX);
1175 dreg = dest = SET_DEST (curr_insn_set);
1176 sreg = src = SET_SRC (curr_insn_set);
1177 if (GET_CODE (dest) == SUBREG)
1178 dreg = SUBREG_REG (dest);
1179 if (GET_CODE (src) == SUBREG)
1180 sreg = SUBREG_REG (src);
1181 if (! (REG_P (dreg) || MEM_P (dreg)) || ! (REG_P (sreg) || MEM_P (sreg)))
1182 return false;
1183 sclass = dclass = NO_REGS;
1184 if (REG_P (dreg))
1185 dclass = get_reg_class (REGNO (dreg));
1186 gcc_assert (dclass < LIM_REG_CLASSES);
1187 if (dclass == ALL_REGS)
1188 /* ALL_REGS is used for new pseudos created by transformations
1189 like reload of SUBREG_REG (see function
1190 simplify_operand_subreg). We don't know their class yet. We
1191 should figure out the class from processing the insn
1192 constraints not in this fast path function. Even if ALL_REGS
1193 were a right class for the pseudo, secondary_... hooks usually
1194 are not define for ALL_REGS. */
1195 return false;
1196 if (REG_P (sreg))
1197 sclass = get_reg_class (REGNO (sreg));
1198 gcc_assert (sclass < LIM_REG_CLASSES);
1199 if (sclass == ALL_REGS)
1200 /* See comments above. */
1201 return false;
1202 if (sclass == NO_REGS && dclass == NO_REGS)
1203 return false;
1204 if (targetm.secondary_memory_needed (GET_MODE (src), sclass, dclass)
1205 && ((sclass != NO_REGS && dclass != NO_REGS)
1206 || (GET_MODE (src)
1207 != targetm.secondary_memory_needed_mode (GET_MODE (src)))))
1208 {
1209 *sec_mem_p = true;
1210 return false;
1211 }
1212 if (! REG_P (dreg) || ! REG_P (sreg))
1213 return false;
1214 sri.prev_sri = NULL;
1215 sri.icode = CODE_FOR_nothing;
1216 sri.extra_cost = 0;
1217 secondary_class = NO_REGS;
1218 /* Set up hard register for a reload pseudo for hook
1219 secondary_reload because some targets just ignore unassigned
1220 pseudos in the hook. */
1221 if (dclass != NO_REGS && lra_get_regno_hard_regno (REGNO (dreg)) < 0)
1222 {
1223 dregno = REGNO (dreg);
1224 reg_renumber[dregno] = ira_class_hard_regs[dclass][0];
1225 }
1226 else
1227 dregno = -1;
1228 if (sclass != NO_REGS && lra_get_regno_hard_regno (REGNO (sreg)) < 0)
1229 {
1230 sregno = REGNO (sreg);
1231 reg_renumber[sregno] = ira_class_hard_regs[sclass][0];
1232 }
1233 else
1234 sregno = -1;
1235 if (sclass != NO_REGS)
1236 secondary_class
1237 = (enum reg_class) targetm.secondary_reload (false, dest,
1238 (reg_class_t) sclass,
1239 GET_MODE (src), &sri);
1240 if (sclass == NO_REGS
1241 || ((secondary_class != NO_REGS || sri.icode != CODE_FOR_nothing)
1242 && dclass != NO_REGS))
1243 {
1244 enum reg_class old_sclass = secondary_class;
1245 secondary_reload_info old_sri = sri;
1246
1247 sri.prev_sri = NULL;
1248 sri.icode = CODE_FOR_nothing;
1249 sri.extra_cost = 0;
1250 secondary_class
1251 = (enum reg_class) targetm.secondary_reload (true, src,
1252 (reg_class_t) dclass,
1253 GET_MODE (src), &sri);
1254 /* Check the target hook consistency. */
1255 lra_assert
1256 ((secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing)
1257 || (old_sclass == NO_REGS && old_sri.icode == CODE_FOR_nothing)
1258 || (secondary_class == old_sclass && sri.icode == old_sri.icode));
1259 }
1260 if (sregno >= 0)
1261 reg_renumber [sregno] = -1;
1262 if (dregno >= 0)
1263 reg_renumber [dregno] = -1;
1264 if (secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing)
1265 return false;
1266 *change_p = true;
1267 new_reg = NULL_RTX;
1268 if (secondary_class != NO_REGS)
1269 new_reg = lra_create_new_reg_with_unique_value (GET_MODE (src), NULL_RTX,
1270 secondary_class,
1271 "secondary");
1272 start_sequence ();
1273 if (sri.icode == CODE_FOR_nothing)
1274 lra_emit_move (new_reg, src);
1275 else
1276 {
1277 enum reg_class scratch_class;
1278
1279 scratch_class = (reg_class_from_constraints
1280 (insn_data[sri.icode].operand[2].constraint));
1281 scratch_reg = (lra_create_new_reg_with_unique_value
1282 (insn_data[sri.icode].operand[2].mode, NULL_RTX,
1283 scratch_class, "scratch"));
1284 emit_insn (GEN_FCN (sri.icode) (new_reg != NULL_RTX ? new_reg : dest,
1285 src, scratch_reg));
1286 }
1287 before = get_insns ();
1288 end_sequence ();
1289 lra_process_new_insns (curr_insn, before, NULL, "Inserting the move");
1290 if (new_reg != NULL_RTX)
1291 SET_SRC (curr_insn_set) = new_reg;
1292 else
1293 {
1294 if (lra_dump_file != NULL)
1295 {
1296 fprintf (lra_dump_file, "Deleting move %u\n", INSN_UID (curr_insn));
1297 dump_insn_slim (lra_dump_file, curr_insn);
1298 }
1299 lra_set_insn_deleted (curr_insn);
1300 return true;
1301 }
1302 return false;
1303}
1304
1305/* The following data describe the result of process_alt_operands.
1306 The data are used in curr_insn_transform to generate reloads. */
1307
1308/* The chosen reg classes which should be used for the corresponding
1309 operands. */
1310static enum reg_class goal_alt[MAX_RECOG_OPERANDS];
1311/* True if the operand should be the same as another operand and that
1312 other operand does not need a reload. */
1313static bool goal_alt_match_win[MAX_RECOG_OPERANDS];
1314/* True if the operand does not need a reload. */
1315static bool goal_alt_win[MAX_RECOG_OPERANDS];
1316/* True if the operand can be offsetable memory. */
1317static bool goal_alt_offmemok[MAX_RECOG_OPERANDS];
1318/* The number of an operand to which given operand can be matched to. */
1319static int goal_alt_matches[MAX_RECOG_OPERANDS];
1320/* The number of elements in the following array. */
1321static int goal_alt_dont_inherit_ops_num;
1322/* Numbers of operands whose reload pseudos should not be inherited. */
1323static int goal_alt_dont_inherit_ops[MAX_RECOG_OPERANDS];
1324/* True if the insn commutative operands should be swapped. */
1325static bool goal_alt_swapped;
1326/* The chosen insn alternative. */
1327static int goal_alt_number;
1328
1329/* True if the corresponding operand is the result of an equivalence
1330 substitution. */
1331static bool equiv_substition_p[MAX_RECOG_OPERANDS];
1332
1333/* The following five variables are used to choose the best insn
1334 alternative. They reflect final characteristics of the best
1335 alternative. */
1336
1337/* Number of necessary reloads and overall cost reflecting the
1338 previous value and other unpleasantness of the best alternative. */
1339static int best_losers, best_overall;
1340/* Overall number hard registers used for reloads. For example, on
1341 some targets we need 2 general registers to reload DFmode and only
1342 one floating point register. */
1343static int best_reload_nregs;
1344/* Overall number reflecting distances of previous reloading the same
1345 value. The distances are counted from the current BB start. It is
1346 used to improve inheritance chances. */
1347static int best_reload_sum;
1348
1349/* True if the current insn should have no correspondingly input or
1350 output reloads. */
1351static bool no_input_reloads_p, no_output_reloads_p;
1352
1353/* True if we swapped the commutative operands in the current
1354 insn. */
1355static int curr_swapped;
1356
1357/* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1358 register of class CL. Add any input reloads to list BEFORE. AFTER
1359 is nonnull if *LOC is an automodified value; handle that case by
1360 adding the required output reloads to list AFTER. Return true if
1361 the RTL was changed.
1362
1363 if CHECK_ONLY_P is true, check that the *LOC is a correct address
1364 register. Return false if the address register is correct. */
1365static bool
1366process_addr_reg (rtx *loc, bool check_only_p, rtx_insn **before, rtx_insn **after,
1367 enum reg_class cl)
1368{
1369 int regno;
1370 enum reg_class rclass, new_class;
1371 rtx reg;
1372 rtx new_reg;
1373 machine_mode mode;
1374 bool subreg_p, before_p = false;
1375
1376 subreg_p = GET_CODE (*loc) == SUBREG;
1377 if (subreg_p)
1378 {
1379 reg = SUBREG_REG (*loc);
1380 mode = GET_MODE (reg);
1381
1382 /* For mode with size bigger than ptr_mode, there unlikely to be "mov"
1383 between two registers with different classes, but there normally will
1384 be "mov" which transfers element of vector register into the general
1385 register, and this normally will be a subreg which should be reloaded
1386 as a whole. This is particularly likely to be triggered when
1387 -fno-split-wide-types specified. */
1388 if (!REG_P (reg)
1389 || in_class_p (reg, cl, &new_class)
1390 || GET_MODE_SIZE (mode) <= GET_MODE_SIZE (ptr_mode))
1391 loc = &SUBREG_REG (*loc);
1392 }
1393
1394 reg = *loc;
1395 mode = GET_MODE (reg);
1396 if (! REG_P (reg))
1397 {
1398 if (check_only_p)
1399 return true;
1400 /* Always reload memory in an address even if the target supports
1401 such addresses. */
1402 new_reg = lra_create_new_reg_with_unique_value (mode, reg, cl, "address");
1403 before_p = true;
1404 }
1405 else
1406 {
1407 regno = REGNO (reg);
1408 rclass = get_reg_class (regno);
1409 if (! check_only_p
1410 && (*loc = get_equiv_with_elimination (reg, curr_insn)) != reg)
1411 {
1412 if (lra_dump_file != NULL)
1413 {
1414 fprintf (lra_dump_file,
1415 "Changing pseudo %d in address of insn %u on equiv ",
1416 REGNO (reg), INSN_UID (curr_insn));
1417 dump_value_slim (lra_dump_file, *loc, 1);
1418 fprintf (lra_dump_file, "\n");
1419 }
1420 *loc = copy_rtx (*loc);
1421 }
1422 if (*loc != reg || ! in_class_p (reg, cl, &new_class))
1423 {
1424 if (check_only_p)
1425 return true;
1426 reg = *loc;
1427 if (get_reload_reg (after == NULL ? OP_IN : OP_INOUT,
1428 mode, reg, cl, subreg_p, "address", &new_reg))
1429 before_p = true;
1430 }
1431 else if (new_class != NO_REGS && rclass != new_class)
1432 {
1433 if (check_only_p)
1434 return true;
1435 lra_change_class (regno, new_class, " Change to", true);
1436 return false;
1437 }
1438 else
1439 return false;
1440 }
1441 if (before_p)
1442 {
1443 push_to_sequence (*before);
1444 lra_emit_move (new_reg, reg);
1445 *before = get_insns ();
1446 end_sequence ();
1447 }
1448 *loc = new_reg;
1449 if (after != NULL)
1450 {
1451 start_sequence ();
1452 lra_emit_move (before_p ? copy_rtx (reg) : reg, new_reg);
1453 emit_insn (*after);
1454 *after = get_insns ();
1455 end_sequence ();
1456 }
1457 return true;
1458}
1459
1460/* Insert move insn in simplify_operand_subreg. BEFORE returns
1461 the insn to be inserted before curr insn. AFTER returns the
1462 the insn to be inserted after curr insn. ORIGREG and NEWREG
1463 are the original reg and new reg for reload. */
1464static void
1465insert_move_for_subreg (rtx_insn **before, rtx_insn **after, rtx origreg,
1466 rtx newreg)
1467{
1468 if (before)
1469 {
1470 push_to_sequence (*before);
1471 lra_emit_move (newreg, origreg);
1472 *before = get_insns ();
1473 end_sequence ();
1474 }
1475 if (after)
1476 {
1477 start_sequence ();
1478 lra_emit_move (origreg, newreg);
1479 emit_insn (*after);
1480 *after = get_insns ();
1481 end_sequence ();
1482 }
1483}
1484
1485static int valid_address_p (machine_mode mode, rtx addr, addr_space_t as);
1486static bool process_address (int, bool, rtx_insn **, rtx_insn **);
1487
1488/* Make reloads for subreg in operand NOP with internal subreg mode
1489 REG_MODE, add new reloads for further processing. Return true if
1490 any change was done. */
1491static bool
1492simplify_operand_subreg (int nop, machine_mode reg_mode)
1493{
1494 int hard_regno;
1495 rtx_insn *before, *after;
1496 machine_mode mode, innermode;
1497 rtx reg, new_reg;
1498 rtx operand = *curr_id->operand_loc[nop];
1499 enum reg_class regclass;
1500 enum op_type type;
1501
1502 before = after = NULL;
1503
1504 if (GET_CODE (operand) != SUBREG)
1505 return false;
1506
1507 mode = GET_MODE (operand);
1508 reg = SUBREG_REG (operand);
1509 innermode = GET_MODE (reg);
1510 type = curr_static_id->operand[nop].type;
1511 if (MEM_P (reg))
1512 {
1513 const bool addr_was_valid
1514 = valid_address_p (innermode, XEXP (reg, 0), MEM_ADDR_SPACE (reg));
1515 alter_subreg (curr_id->operand_loc[nop], false);
1516 rtx subst = *curr_id->operand_loc[nop];
1517 lra_assert (MEM_P (subst));
1518
1519 if (!addr_was_valid
1520 || valid_address_p (GET_MODE (subst), XEXP (subst, 0),
1521 MEM_ADDR_SPACE (subst))
1522 || ((get_constraint_type (lookup_constraint
1523 (curr_static_id->operand[nop].constraint))
1524 != CT_SPECIAL_MEMORY)
1525 /* We still can reload address and if the address is
1526 valid, we can remove subreg without reloading its
1527 inner memory. */
1528 && valid_address_p (GET_MODE (subst),
1529 regno_reg_rtx
1530 [ira_class_hard_regs
1531 [base_reg_class (GET_MODE (subst),
1532 MEM_ADDR_SPACE (subst),
1533 ADDRESS, SCRATCH)][0]],
1534 MEM_ADDR_SPACE (subst))))
1535 {
1536 /* If we change the address for a paradoxical subreg of memory, the
1537 new address might violate the necessary alignment or the access
1538 might be slow; take this into consideration. We need not worry
1539 about accesses beyond allocated memory for paradoxical memory
1540 subregs as we don't substitute such equiv memory (see processing
1541 equivalences in function lra_constraints) and because for spilled
1542 pseudos we allocate stack memory enough for the biggest
1543 corresponding paradoxical subreg.
1544
1545 However, do not blindly simplify a (subreg (mem ...)) for
1546 WORD_REGISTER_OPERATIONS targets as this may lead to loading junk
1547 data into a register when the inner is narrower than outer or
1548 missing important data from memory when the inner is wider than
1549 outer. This rule only applies to modes that are no wider than
1550 a word. */
1551 if (!(GET_MODE_PRECISION (mode) != GET_MODE_PRECISION (innermode)
1552 && GET_MODE_SIZE (mode) <= UNITS_PER_WORD
1553 && GET_MODE_SIZE (innermode) <= UNITS_PER_WORD
1554 && WORD_REGISTER_OPERATIONS)
1555 && (!(MEM_ALIGN (subst) < GET_MODE_ALIGNMENT (mode)
1556 && targetm.slow_unaligned_access (mode, MEM_ALIGN (subst)))
1557 || (MEM_ALIGN (reg) < GET_MODE_ALIGNMENT (innermode)
1558 && targetm.slow_unaligned_access (innermode,
1559 MEM_ALIGN (reg)))))
1560 return true;
1561
1562 *curr_id->operand_loc[nop] = operand;
1563
1564 /* But if the address was not valid, we cannot reload the MEM without
1565 reloading the address first. */
1566 if (!addr_was_valid)
1567 process_address (nop, false, &before, &after);
1568
1569 /* INNERMODE is fast, MODE slow. Reload the mem in INNERMODE. */
1570 enum reg_class rclass
1571 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1572 if (get_reload_reg (curr_static_id->operand[nop].type, innermode,
1573 reg, rclass, TRUE, "slow mem", &new_reg))
1574 {
1575 bool insert_before, insert_after;
1576 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1577
1578 insert_before = (type != OP_OUT
1579 || partial_subreg_p (mode, innermode));
1580 insert_after = type != OP_IN;
1581 insert_move_for_subreg (insert_before ? &before : NULL,
1582 insert_after ? &after : NULL,
1583 reg, new_reg);
1584 }
1585 SUBREG_REG (operand) = new_reg;
1586
1587 /* Convert to MODE. */
1588 reg = operand;
1589 rclass
1590 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1591 if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg,
1592 rclass, TRUE, "slow mem", &new_reg))
1593 {
1594 bool insert_before, insert_after;
1595 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1596
1597 insert_before = type != OP_OUT;
1598 insert_after = type != OP_IN;
1599 insert_move_for_subreg (insert_before ? &before : NULL,
1600 insert_after ? &after : NULL,
1601 reg, new_reg);
1602 }
1603 *curr_id->operand_loc[nop] = new_reg;
1604 lra_process_new_insns (curr_insn, before, after,
1605 "Inserting slow mem reload");
1606 return true;
1607 }
1608
1609 /* If the address was valid and became invalid, prefer to reload
1610 the memory. Typical case is when the index scale should
1611 correspond the memory. */
1612 *curr_id->operand_loc[nop] = operand;
1613 /* Do not return false here as the MEM_P (reg) will be processed
1614 later in this function. */
1615 }
1616 else if (REG_P (reg) && REGNO (reg) < FIRST_PSEUDO_REGISTER)
1617 {
1618 alter_subreg (curr_id->operand_loc[nop], false);
1619 return true;
1620 }
1621 else if (CONSTANT_P (reg))
1622 {
1623 /* Try to simplify subreg of constant. It is usually result of
1624 equivalence substitution. */
1625 if (innermode == VOIDmode
1626 && (innermode = original_subreg_reg_mode[nop]) == VOIDmode)
1627 innermode = curr_static_id->operand[nop].mode;
1628 if ((new_reg = simplify_subreg (mode, reg, innermode,
1629 SUBREG_BYTE (operand))) != NULL_RTX)
1630 {
1631 *curr_id->operand_loc[nop] = new_reg;
1632 return true;
1633 }
1634 }
1635 /* Put constant into memory when we have mixed modes. It generates
1636 a better code in most cases as it does not need a secondary
1637 reload memory. It also prevents LRA looping when LRA is using
1638 secondary reload memory again and again. */
1639 if (CONSTANT_P (reg) && CONST_POOL_OK_P (reg_mode, reg)
1640 && SCALAR_INT_MODE_P (reg_mode) != SCALAR_INT_MODE_P (mode))
1641 {
1642 SUBREG_REG (operand) = force_const_mem (reg_mode, reg);
1643 alter_subreg (curr_id->operand_loc[nop], false);
1644 return true;
1645 }
1646 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1647 if there may be a problem accessing OPERAND in the outer
1648 mode. */
1649 if ((REG_P (reg)
1650 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
1651 && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0
1652 /* Don't reload paradoxical subregs because we could be looping
1653 having repeatedly final regno out of hard regs range. */
1654 && (hard_regno_nregs (hard_regno, innermode)
1655 >= hard_regno_nregs (hard_regno, mode))
1656 && simplify_subreg_regno (hard_regno, innermode,
1657 SUBREG_BYTE (operand), mode) < 0
1658 /* Don't reload subreg for matching reload. It is actually
1659 valid subreg in LRA. */
1660 && ! LRA_SUBREG_P (operand))
1661 || CONSTANT_P (reg) || GET_CODE (reg) == PLUS || MEM_P (reg))
1662 {
1663 enum reg_class rclass;
1664
1665 if (REG_P (reg))
1666 /* There is a big probability that we will get the same class
1667 for the new pseudo and we will get the same insn which
1668 means infinite looping. So spill the new pseudo. */
1669 rclass = NO_REGS;
1670 else
1671 /* The class will be defined later in curr_insn_transform. */
1672 rclass
1673 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1674
1675 if (get_reload_reg (curr_static_id->operand[nop].type, reg_mode, reg,
1676 rclass, TRUE, "subreg reg", &new_reg))
1677 {
1678 bool insert_before, insert_after;
1679 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1680
1681 insert_before = (type != OP_OUT
1682 || read_modify_subreg_p (operand));
1683 insert_after = (type != OP_IN);
1684 insert_move_for_subreg (insert_before ? &before : NULL,
1685 insert_after ? &after : NULL,
1686 reg, new_reg);
1687 }
1688 SUBREG_REG (operand) = new_reg;
1689 lra_process_new_insns (curr_insn, before, after,
1690 "Inserting subreg reload");
1691 return true;
1692 }
1693 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1694 IRA allocates hardreg to the inner pseudo reg according to its mode
1695 instead of the outermode, so the size of the hardreg may not be enough
1696 to contain the outermode operand, in that case we may need to insert
1697 reload for the reg. For the following two types of paradoxical subreg,
1698 we need to insert reload:
1699 1. If the op_type is OP_IN, and the hardreg could not be paired with
1700 other hardreg to contain the outermode operand
1701 (checked by in_hard_reg_set_p), we need to insert the reload.
1702 2. If the op_type is OP_OUT or OP_INOUT.
1703
1704 Here is a paradoxical subreg example showing how the reload is generated:
1705
1706 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1707 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1708
1709 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1710 here, if reg107 is assigned to hardreg R15, because R15 is the last
1711 hardreg, compiler cannot find another hardreg to pair with R15 to
1712 contain TImode data. So we insert a TImode reload reg180 for it.
1713 After reload is inserted:
1714
1715 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1716 (reg:DI 107 [ __comp ])) -1
1717 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1718 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1719
1720 Two reload hard registers will be allocated to reg180 to save TImode data
1721 in LRA_assign. */
1722 else if (REG_P (reg)
1723 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
1724 && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0
1725 && (hard_regno_nregs (hard_regno, innermode)
1726 < hard_regno_nregs (hard_regno, mode))
1727 && (regclass = lra_get_allocno_class (REGNO (reg)))
1728 && (type != OP_IN
1729 || !in_hard_reg_set_p (reg_class_contents[regclass],
1730 mode, hard_regno)))
1731 {
1732 /* The class will be defined later in curr_insn_transform. */
1733 enum reg_class rclass
1734 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1735
1736 if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg,
1737 rclass, TRUE, "paradoxical subreg", &new_reg))
1738 {
1739 rtx subreg;
1740 bool insert_before, insert_after;
1741
1742 PUT_MODE (new_reg, mode);
1743 subreg = gen_lowpart_SUBREG (innermode, new_reg);
1744 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1745
1746 insert_before = (type != OP_OUT);
1747 insert_after = (type != OP_IN);
1748 insert_move_for_subreg (insert_before ? &before : NULL,
1749 insert_after ? &after : NULL,
1750 reg, subreg);
1751 }
1752 SUBREG_REG (operand) = new_reg;
1753 lra_process_new_insns (curr_insn, before, after,
1754 "Inserting paradoxical subreg reload");
1755 return true;
1756 }
1757 return false;
1758}
1759
1760/* Return TRUE if X refers for a hard register from SET. */
1761static bool
1762uses_hard_regs_p (rtx x, HARD_REG_SET set)
1763{
1764 int i, j, x_hard_regno;
1765 machine_mode mode;
1766 const char *fmt;
1767 enum rtx_code code;
1768
1769 if (x == NULL_RTX)
1770 return false;
1771 code = GET_CODE (x);
1772 mode = GET_MODE (x);
1773 if (code == SUBREG)
1774 {
1775 mode = wider_subreg_mode (x);
1776 x = SUBREG_REG (x);
1777 code = GET_CODE (x);
1778 }
1779
1780 if (REG_P (x))
1781 {
1782 x_hard_regno = get_hard_regno (x, true);
1783 return (x_hard_regno >= 0
1784 && overlaps_hard_reg_set_p (set, mode, x_hard_regno));
1785 }
1786 if (MEM_P (x))
1787 {
1788 struct address_info ad;
1789
1790 decompose_mem_address (&ad, x);
1791 if (ad.base_term != NULL && uses_hard_regs_p (*ad.base_term, set))
1792 return true;
1793 if (ad.index_term != NULL && uses_hard_regs_p (*ad.index_term, set))
1794 return true;
1795 }
1796 fmt = GET_RTX_FORMAT (code);
1797 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1798 {
1799 if (fmt[i] == 'e')
1800 {
1801 if (uses_hard_regs_p (XEXP (x, i), set))
1802 return true;
1803 }
1804 else if (fmt[i] == 'E')
1805 {
1806 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1807 if (uses_hard_regs_p (XVECEXP (x, i, j), set))
1808 return true;
1809 }
1810 }
1811 return false;
1812}
1813
1814/* Return true if OP is a spilled pseudo. */
1815static inline bool
1816spilled_pseudo_p (rtx op)
1817{
1818 return (REG_P (op)
1819 && REGNO (op) >= FIRST_PSEUDO_REGISTER && in_mem_p (REGNO (op)));
1820}
1821
1822/* Return true if X is a general constant. */
1823static inline bool
1824general_constant_p (rtx x)
1825{
1826 return CONSTANT_P (x) && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (x));
1827}
1828
1829static bool
1830reg_in_class_p (rtx reg, enum reg_class cl)
1831{
1832 if (cl == NO_REGS)
1833 return get_reg_class (REGNO (reg)) == NO_REGS;
1834 return in_class_p (reg, cl, NULL);
1835}
1836
1837/* Return true if SET of RCLASS contains no hard regs which can be
1838 used in MODE. */
1839static bool
1840prohibited_class_reg_set_mode_p (enum reg_class rclass,
1841 HARD_REG_SET &set,
1842 machine_mode mode)
1843{
1844 HARD_REG_SET temp;
1845
1846 lra_assert (hard_reg_set_subset_p (reg_class_contents[rclass], set));
1847 COPY_HARD_REG_SET (temp, set);
1848 AND_COMPL_HARD_REG_SET (temp, lra_no_alloc_regs);
1849 return (hard_reg_set_subset_p
1850 (temp, ira_prohibited_class_mode_regs[rclass][mode]));
1851}
1852
1853
1854/* Used to check validity info about small class input operands. It
1855 should be incremented at start of processing an insn
1856 alternative. */
1857static unsigned int curr_small_class_check = 0;
1858
1859/* Update number of used inputs of class OP_CLASS for operand NOP.
1860 Return true if we have more such class operands than the number of
1861 available regs. */
1862static bool
1863update_and_check_small_class_inputs (int nop, enum reg_class op_class)
1864{
1865 static unsigned int small_class_check[LIM_REG_CLASSES];
1866 static int small_class_input_nums[LIM_REG_CLASSES];
1867
1868 if (SMALL_REGISTER_CLASS_P (op_class)
1869 /* We are interesting in classes became small because of fixing
1870 some hard regs, e.g. by an user through GCC options. */
1871 && hard_reg_set_intersect_p (reg_class_contents[op_class],
1872 ira_no_alloc_regs)
1873 && (curr_static_id->operand[nop].type != OP_OUT
1874 || curr_static_id->operand[nop].early_clobber))
1875 {
1876 if (small_class_check[op_class] == curr_small_class_check)
1877 small_class_input_nums[op_class]++;
1878 else
1879 {
1880 small_class_check[op_class] = curr_small_class_check;
1881 small_class_input_nums[op_class] = 1;
1882 }
1883 if (small_class_input_nums[op_class] > ira_class_hard_regs_num[op_class])
1884 return true;
1885 }
1886 return false;
1887}
1888
1889/* Major function to choose the current insn alternative and what
1890 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1891 negative we should consider only this alternative. Return false if
1892 we can not choose the alternative or find how to reload the
1893 operands. */
1894static bool
1895process_alt_operands (int only_alternative)
1896{
1897 bool ok_p = false;
1898 int nop, overall, nalt;
1899 int n_alternatives = curr_static_id->n_alternatives;
1900 int n_operands = curr_static_id->n_operands;
1901 /* LOSERS counts the operands that don't fit this alternative and
1902 would require loading. */
1903 int losers;
1904 int addr_losers;
1905 /* REJECT is a count of how undesirable this alternative says it is
1906 if any reloading is required. If the alternative matches exactly
1907 then REJECT is ignored, but otherwise it gets this much counted
1908 against it in addition to the reloading needed. */
1909 int reject;
1910 /* This is defined by '!' or '?' alternative constraint and added to
1911 reject. But in some cases it can be ignored. */
1912 int static_reject;
1913 int op_reject;
1914 /* The number of elements in the following array. */
1915 int early_clobbered_regs_num;
1916 /* Numbers of operands which are early clobber registers. */
1917 int early_clobbered_nops[MAX_RECOG_OPERANDS];
1918 enum reg_class curr_alt[MAX_RECOG_OPERANDS];
1919 HARD_REG_SET curr_alt_set[MAX_RECOG_OPERANDS];
1920 bool curr_alt_match_win[MAX_RECOG_OPERANDS];
1921 bool curr_alt_win[MAX_RECOG_OPERANDS];
1922 bool curr_alt_offmemok[MAX_RECOG_OPERANDS];
1923 int curr_alt_matches[MAX_RECOG_OPERANDS];
1924 /* The number of elements in the following array. */
1925 int curr_alt_dont_inherit_ops_num;
1926 /* Numbers of operands whose reload pseudos should not be inherited. */
1927 int curr_alt_dont_inherit_ops[MAX_RECOG_OPERANDS];
1928 rtx op;
1929 /* The register when the operand is a subreg of register, otherwise the
1930 operand itself. */
1931 rtx no_subreg_reg_operand[MAX_RECOG_OPERANDS];
1932 /* The register if the operand is a register or subreg of register,
1933 otherwise NULL. */
1934 rtx operand_reg[MAX_RECOG_OPERANDS];
1935 int hard_regno[MAX_RECOG_OPERANDS];
1936 machine_mode biggest_mode[MAX_RECOG_OPERANDS];
1937 int reload_nregs, reload_sum;
1938 bool costly_p;
1939 enum reg_class cl;
1940
1941 /* Calculate some data common for all alternatives to speed up the
1942 function. */
1943 for (nop = 0; nop < n_operands; nop++)
1944 {
1945 rtx reg;
1946
1947 op = no_subreg_reg_operand[nop] = *curr_id->operand_loc[nop];
1948 /* The real hard regno of the operand after the allocation. */
1949 hard_regno[nop] = get_hard_regno (op, true);
1950
1951 operand_reg[nop] = reg = op;
1952 biggest_mode[nop] = GET_MODE (op);
1953 if (GET_CODE (op) == SUBREG)
1954 {
1955 biggest_mode[nop] = wider_subreg_mode (op);
1956 operand_reg[nop] = reg = SUBREG_REG (op);
1957 }
1958 if (! REG_P (reg))
1959 operand_reg[nop] = NULL_RTX;
1960 else if (REGNO (reg) >= FIRST_PSEUDO_REGISTER
1961 || ((int) REGNO (reg)
1962 == lra_get_elimination_hard_regno (REGNO (reg))))
1963 no_subreg_reg_operand[nop] = reg;
1964 else
1965 operand_reg[nop] = no_subreg_reg_operand[nop]
1966 /* Just use natural mode for elimination result. It should
1967 be enough for extra constraints hooks. */
1968 = regno_reg_rtx[hard_regno[nop]];
1969 }
1970
1971 /* The constraints are made of several alternatives. Each operand's
1972 constraint looks like foo,bar,... with commas separating the
1973 alternatives. The first alternatives for all operands go
1974 together, the second alternatives go together, etc.
1975
1976 First loop over alternatives. */
1977 alternative_mask preferred = curr_id->preferred_alternatives;
1978 if (only_alternative >= 0)
1979 preferred &= ALTERNATIVE_BIT (only_alternative);
1980
1981 for (nalt = 0; nalt < n_alternatives; nalt++)
1982 {
1983 /* Loop over operands for one constraint alternative. */
1984 if (!TEST_BIT (preferred, nalt))
1985 continue;
1986
1987 curr_small_class_check++;
1988 overall = losers = addr_losers = 0;
1989 static_reject = reject = reload_nregs = reload_sum = 0;
1990 for (nop = 0; nop < n_operands; nop++)
1991 {
1992 int inc = (curr_static_id
1993 ->operand_alternative[nalt * n_operands + nop].reject);
1994 if (lra_dump_file != NULL && inc != 0)
1995 fprintf (lra_dump_file,
1996 " Staticly defined alt reject+=%d\n", inc);
1997 static_reject += inc;
1998 }
1999 reject += static_reject;
2000 early_clobbered_regs_num = 0;
2001
2002 for (nop = 0; nop < n_operands; nop++)
2003 {
2004 const char *p;
2005 char *end;
2006 int len, c, m, i, opalt_num, this_alternative_matches;
2007 bool win, did_match, offmemok, early_clobber_p;
2008 /* false => this operand can be reloaded somehow for this
2009 alternative. */
2010 bool badop;
2011 /* true => this operand can be reloaded if the alternative
2012 allows regs. */
2013 bool winreg;
2014 /* True if a constant forced into memory would be OK for
2015 this operand. */
2016 bool constmemok;
2017 enum reg_class this_alternative, this_costly_alternative;
2018 HARD_REG_SET this_alternative_set, this_costly_alternative_set;
2019 bool this_alternative_match_win, this_alternative_win;
2020 bool this_alternative_offmemok;
2021 bool scratch_p;
2022 machine_mode mode;
2023 enum constraint_num cn;
2024
2025 opalt_num = nalt * n_operands + nop;
2026 if (curr_static_id->operand_alternative[opalt_num].anything_ok)
2027 {
2028 /* Fast track for no constraints at all. */
2029 curr_alt[nop] = NO_REGS;
2030 CLEAR_HARD_REG_SET (curr_alt_set[nop]);
2031 curr_alt_win[nop] = true;
2032 curr_alt_match_win[nop] = false;
2033 curr_alt_offmemok[nop] = false;
2034 curr_alt_matches[nop] = -1;
2035 continue;
2036 }
2037
2038 op = no_subreg_reg_operand[nop];
2039 mode = curr_operand_mode[nop];
2040
2041 win = did_match = winreg = offmemok = constmemok = false;
2042 badop = true;
2043
2044 early_clobber_p = false;
2045 p = curr_static_id->operand_alternative[opalt_num].constraint;
2046
2047 this_costly_alternative = this_alternative = NO_REGS;
2048 /* We update set of possible hard regs besides its class
2049 because reg class might be inaccurate. For example,
2050 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
2051 is translated in HI_REGS because classes are merged by
2052 pairs and there is no accurate intermediate class. */
2053 CLEAR_HARD_REG_SET (this_alternative_set);
2054 CLEAR_HARD_REG_SET (this_costly_alternative_set);
2055 this_alternative_win = false;
2056 this_alternative_match_win = false;
2057 this_alternative_offmemok = false;
2058 this_alternative_matches = -1;
2059
2060 /* An empty constraint should be excluded by the fast
2061 track. */
2062 lra_assert (*p != 0 && *p != ',');
2063
2064 op_reject = 0;
2065 /* Scan this alternative's specs for this operand; set WIN
2066 if the operand fits any letter in this alternative.
2067 Otherwise, clear BADOP if this operand could fit some
2068 letter after reloads, or set WINREG if this operand could
2069 fit after reloads provided the constraint allows some
2070 registers. */
2071 costly_p = false;
2072 do
2073 {
2074 switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c)
2075 {
2076 case '\0':
2077 len = 0;
2078 break;
2079 case ',':
2080 c = '\0';
2081 break;
2082
2083 case '&':
2084 early_clobber_p = true;
2085 break;
2086
2087 case '$':
2088 op_reject += LRA_MAX_REJECT;
2089 break;
2090 case '^':
2091 op_reject += LRA_LOSER_COST_FACTOR;
2092 break;
2093
2094 case '#':
2095 /* Ignore rest of this alternative. */
2096 c = '\0';
2097 break;
2098
2099 case '0': case '1': case '2': case '3': case '4':
2100 case '5': case '6': case '7': case '8': case '9':
2101 {
2102 int m_hregno;
2103 bool match_p;
2104
2105 m = strtoul (p, &end, 10);
2106 p = end;
2107 len = 0;
2108 lra_assert (nop > m);
2109
2110 this_alternative_matches = m;
2111 m_hregno = get_hard_regno (*curr_id->operand_loc[m], false);
2112 /* We are supposed to match a previous operand.
2113 If we do, we win if that one did. If we do
2114 not, count both of the operands as losers.
2115 (This is too conservative, since most of the
2116 time only a single reload insn will be needed
2117 to make the two operands win. As a result,
2118 this alternative may be rejected when it is
2119 actually desirable.) */
2120 match_p = false;
2121 if (operands_match_p (*curr_id->operand_loc[nop],
2122 *curr_id->operand_loc[m], m_hregno))
2123 {
2124 /* We should reject matching of an early
2125 clobber operand if the matching operand is
2126 not dying in the insn. */
2127 if (! curr_static_id->operand[m].early_clobber
2128 || operand_reg[nop] == NULL_RTX
2129 || (find_regno_note (curr_insn, REG_DEAD,
2130 REGNO (op))
2131 || REGNO (op) == REGNO (operand_reg[m])))
2132 match_p = true;
2133 }
2134 if (match_p)
2135 {
2136 /* If we are matching a non-offsettable
2137 address where an offsettable address was
2138 expected, then we must reject this
2139 combination, because we can't reload
2140 it. */
2141 if (curr_alt_offmemok[m]
2142 && MEM_P (*curr_id->operand_loc[m])
2143 && curr_alt[m] == NO_REGS && ! curr_alt_win[m])
2144 continue;
2145 }
2146 else
2147 {
2148 /* Operands don't match. Both operands must
2149 allow a reload register, otherwise we
2150 cannot make them match. */
2151 if (curr_alt[m] == NO_REGS)
2152 break;
2153 /* Retroactively mark the operand we had to
2154 match as a loser, if it wasn't already and
2155 it wasn't matched to a register constraint
2156 (e.g it might be matched by memory). */
2157 if (curr_alt_win[m]
2158 && (operand_reg[m] == NULL_RTX
2159 || hard_regno[m] < 0))
2160 {
2161 losers++;
2162 reload_nregs
2163 += (ira_reg_class_max_nregs[curr_alt[m]]
2164 [GET_MODE (*curr_id->operand_loc[m])]);
2165 }
2166
2167 /* Prefer matching earlyclobber alternative as
2168 it results in less hard regs required for
2169 the insn than a non-matching earlyclobber
2170 alternative. */
2171 if (curr_static_id->operand[m].early_clobber)
2172 {
2173 if (lra_dump_file != NULL)
2174 fprintf
2175 (lra_dump_file,
2176 " %d Matching earlyclobber alt:"
2177 " reject--\n",
2178 nop);
2179 reject--;
2180 }
2181 /* Otherwise we prefer no matching
2182 alternatives because it gives more freedom
2183 in RA. */
2184 else if (operand_reg[nop] == NULL_RTX
2185 || (find_regno_note (curr_insn, REG_DEAD,
2186 REGNO (operand_reg[nop]))
2187 == NULL_RTX))
2188 {
2189 if (lra_dump_file != NULL)
2190 fprintf
2191 (lra_dump_file,
2192 " %d Matching alt: reject+=2\n",
2193 nop);
2194 reject += 2;
2195 }
2196 }
2197 /* If we have to reload this operand and some
2198 previous operand also had to match the same
2199 thing as this operand, we don't know how to do
2200 that. */
2201 if (!match_p || !curr_alt_win[m])
2202 {
2203 for (i = 0; i < nop; i++)
2204 if (curr_alt_matches[i] == m)
2205 break;
2206 if (i < nop)
2207 break;
2208 }
2209 else
2210 did_match = true;
2211
2212 /* This can be fixed with reloads if the operand
2213 we are supposed to match can be fixed with
2214 reloads. */
2215 badop = false;
2216 this_alternative = curr_alt[m];
2217 COPY_HARD_REG_SET (this_alternative_set, curr_alt_set[m]);
2218 winreg = this_alternative != NO_REGS;
2219 break;
2220 }
2221
2222 case 'g':
2223 if (MEM_P (op)
2224 || general_constant_p (op)
2225 || spilled_pseudo_p (op))
2226 win = true;
2227 cl = GENERAL_REGS;
2228 goto reg;
2229
2230 default:
2231 cn = lookup_constraint (p);
2232 switch (get_constraint_type (cn))
2233 {
2234 case CT_REGISTER:
2235 cl = reg_class_for_constraint (cn);
2236 if (cl != NO_REGS)
2237 goto reg;
2238 break;
2239
2240 case CT_CONST_INT:
2241 if (CONST_INT_P (op)
2242 && insn_const_int_ok_for_constraint (INTVAL (op), cn))
2243 win = true;
2244 break;
2245
2246 case CT_MEMORY:
2247 if (MEM_P (op)
2248 && satisfies_memory_constraint_p (op, cn))
2249 win = true;
2250 else if (spilled_pseudo_p (op))
2251 win = true;
2252
2253 /* If we didn't already win, we can reload constants
2254 via force_const_mem or put the pseudo value into
2255 memory, or make other memory by reloading the
2256 address like for 'o'. */
2257 if (CONST_POOL_OK_P (mode, op)
2258 || MEM_P (op) || REG_P (op)
2259 /* We can restore the equiv insn by a
2260 reload. */
2261 || equiv_substition_p[nop])
2262 badop = false;
2263 constmemok = true;
2264 offmemok = true;
2265 break;
2266
2267 case CT_ADDRESS:
2268 /* If we didn't already win, we can reload the address
2269 into a base register. */
2270 if (satisfies_address_constraint_p (op, cn))
2271 win = true;
2272 cl = base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
2273 ADDRESS, SCRATCH);
2274 badop = false;
2275 goto reg;
2276
2277 case CT_FIXED_FORM:
2278 if (constraint_satisfied_p (op, cn))
2279 win = true;
2280 break;
2281
2282 case CT_SPECIAL_MEMORY:
2283 if (MEM_P (op)
2284 && satisfies_memory_constraint_p (op, cn))
2285 win = true;
2286 else if (spilled_pseudo_p (op))
2287 win = true;
2288 break;
2289 }
2290 break;
2291
2292 reg:
2293 this_alternative = reg_class_subunion[this_alternative][cl];
2294 IOR_HARD_REG_SET (this_alternative_set,
2295 reg_class_contents[cl]);
2296 if (costly_p)
2297 {
2298 this_costly_alternative
2299 = reg_class_subunion[this_costly_alternative][cl];
2300 IOR_HARD_REG_SET (this_costly_alternative_set,
2301 reg_class_contents[cl]);
2302 }
2303 if (mode == BLKmode)
2304 break;
2305 winreg = true;
2306 if (REG_P (op))
2307 {
2308 if (hard_regno[nop] >= 0
2309 && in_hard_reg_set_p (this_alternative_set,
2310 mode, hard_regno[nop]))
2311 win = true;
2312 else if (hard_regno[nop] < 0
2313 && in_class_p (op, this_alternative, NULL))
2314 win = true;
2315 }
2316 break;
2317 }
2318 if (c != ' ' && c != '\t')
2319 costly_p = c == '*';
2320 }
2321 while ((p += len), c);
2322
2323 scratch_p = (operand_reg[nop] != NULL_RTX
2324 && lra_former_scratch_p (REGNO (operand_reg[nop])));
2325 /* Record which operands fit this alternative. */
2326 if (win)
2327 {
2328 this_alternative_win = true;
2329 if (operand_reg[nop] != NULL_RTX)
2330 {
2331 if (hard_regno[nop] >= 0)
2332 {
2333 if (in_hard_reg_set_p (this_costly_alternative_set,
2334 mode, hard_regno[nop]))
2335 {
2336 if (lra_dump_file != NULL)
2337 fprintf (lra_dump_file,
2338 " %d Costly set: reject++\n",
2339 nop);
2340 reject++;
2341 }
2342 }
2343 else
2344 {
2345 /* Prefer won reg to spilled pseudo under other
2346 equal conditions for possibe inheritance. */
2347 if (! scratch_p)
2348 {
2349 if (lra_dump_file != NULL)
2350 fprintf
2351 (lra_dump_file,
2352 " %d Non pseudo reload: reject++\n",
2353 nop);
2354 reject++;
2355 }
2356 if (in_class_p (operand_reg[nop],
2357 this_costly_alternative, NULL))
2358 {
2359 if (lra_dump_file != NULL)
2360 fprintf
2361 (lra_dump_file,
2362 " %d Non pseudo costly reload:"
2363 " reject++\n",
2364 nop);
2365 reject++;
2366 }
2367 }
2368 /* We simulate the behavior of old reload here.
2369 Although scratches need hard registers and it
2370 might result in spilling other pseudos, no reload
2371 insns are generated for the scratches. So it
2372 might cost something but probably less than old
2373 reload pass believes. */
2374 if (scratch_p)
2375 {
2376 if (lra_dump_file != NULL)
2377 fprintf (lra_dump_file,
2378 " %d Scratch win: reject+=2\n",
2379 nop);
2380 reject += 2;
2381 }
2382 }
2383 }
2384 else if (did_match)
2385 this_alternative_match_win = true;
2386 else
2387 {
2388 int const_to_mem = 0;
2389 bool no_regs_p;
2390
2391 reject += op_reject;
2392 /* Never do output reload of stack pointer. It makes
2393 impossible to do elimination when SP is changed in
2394 RTL. */
2395 if (op == stack_pointer_rtx && ! frame_pointer_needed
2396 && curr_static_id->operand[nop].type != OP_IN)
2397 goto fail;
2398
2399 /* If this alternative asks for a specific reg class, see if there
2400 is at least one allocatable register in that class. */
2401 no_regs_p
2402 = (this_alternative == NO_REGS
2403 || (hard_reg_set_subset_p
2404 (reg_class_contents[this_alternative],
2405 lra_no_alloc_regs)));
2406
2407 /* For asms, verify that the class for this alternative is possible
2408 for the mode that is specified. */
2409 if (!no_regs_p && INSN_CODE (curr_insn) < 0)
2410 {
2411 int i;
2412 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2413 if (targetm.hard_regno_mode_ok (i, mode)
2414 && in_hard_reg_set_p (reg_class_contents[this_alternative],
2415 mode, i))
2416 break;
2417 if (i == FIRST_PSEUDO_REGISTER)
2418 winreg = false;
2419 }
2420
2421 /* If this operand accepts a register, and if the
2422 register class has at least one allocatable register,
2423 then this operand can be reloaded. */
2424 if (winreg && !no_regs_p)
2425 badop = false;
2426
2427 if (badop)
2428 {
2429 if (lra_dump_file != NULL)
2430 fprintf (lra_dump_file,
2431 " alt=%d: Bad operand -- refuse\n",
2432 nalt);
2433 goto fail;
2434 }
2435
2436 if (this_alternative != NO_REGS)
2437 {
2438 HARD_REG_SET available_regs;
2439
2440 COPY_HARD_REG_SET (available_regs,
2441 reg_class_contents[this_alternative]);
2442 AND_COMPL_HARD_REG_SET
2443 (available_regs,
2444 ira_prohibited_class_mode_regs[this_alternative][mode]);
2445 AND_COMPL_HARD_REG_SET (available_regs, lra_no_alloc_regs);
2446 if (hard_reg_set_empty_p (available_regs))
2447 {
2448 /* There are no hard regs holding a value of given
2449 mode. */
2450 if (offmemok)
2451 {
2452 this_alternative = NO_REGS;
2453 if (lra_dump_file != NULL)
2454 fprintf (lra_dump_file,
2455 " %d Using memory because of"
2456 " a bad mode: reject+=2\n",
2457 nop);
2458 reject += 2;
2459 }
2460 else
2461 {
2462 if (lra_dump_file != NULL)
2463 fprintf (lra_dump_file,
2464 " alt=%d: Wrong mode -- refuse\n",
2465 nalt);
2466 goto fail;
2467 }
2468 }
2469 }
2470
2471 /* If not assigned pseudo has a class which a subset of
2472 required reg class, it is a less costly alternative
2473 as the pseudo still can get a hard reg of necessary
2474 class. */
2475 if (! no_regs_p && REG_P (op) && hard_regno[nop] < 0
2476 && (cl = get_reg_class (REGNO (op))) != NO_REGS
2477 && ira_class_subset_p[this_alternative][cl])
2478 {
2479 if (lra_dump_file != NULL)
2480 fprintf
2481 (lra_dump_file,
2482 " %d Super set class reg: reject-=3\n", nop);
2483 reject -= 3;
2484 }
2485
2486 this_alternative_offmemok = offmemok;
2487 if (this_costly_alternative != NO_REGS)
2488 {
2489 if (lra_dump_file != NULL)
2490 fprintf (lra_dump_file,
2491 " %d Costly loser: reject++\n", nop);
2492 reject++;
2493 }
2494 /* If the operand is dying, has a matching constraint,
2495 and satisfies constraints of the matched operand
2496 which failed to satisfy the own constraints, most probably
2497 the reload for this operand will be gone. */
2498 if (this_alternative_matches >= 0
2499 && !curr_alt_win[this_alternative_matches]
2500 && REG_P (op)
2501 && find_regno_note (curr_insn, REG_DEAD, REGNO (op))
2502 && (hard_regno[nop] >= 0
2503 ? in_hard_reg_set_p (this_alternative_set,
2504 mode, hard_regno[nop])
2505 : in_class_p (op, this_alternative, NULL)))
2506 {
2507 if (lra_dump_file != NULL)
2508 fprintf
2509 (lra_dump_file,
2510 " %d Dying matched operand reload: reject++\n",
2511 nop);
2512 reject++;
2513 }
2514 else
2515 {
2516 /* Strict_low_part requires to reload the register
2517 not the sub-register. In this case we should
2518 check that a final reload hard reg can hold the
2519 value mode. */
2520 if (curr_static_id->operand[nop].strict_low
2521 && REG_P (op)
2522 && hard_regno[nop] < 0
2523 && GET_CODE (*curr_id->operand_loc[nop]) == SUBREG
2524 && ira_class_hard_regs_num[this_alternative] > 0
2525 && (!targetm.hard_regno_mode_ok
2526 (ira_class_hard_regs[this_alternative][0],
2527 GET_MODE (*curr_id->operand_loc[nop]))))
2528 {
2529 if (lra_dump_file != NULL)
2530 fprintf
2531 (lra_dump_file,
2532 " alt=%d: Strict low subreg reload -- refuse\n",
2533 nalt);
2534 goto fail;
2535 }
2536 losers++;
2537 }
2538 if (operand_reg[nop] != NULL_RTX
2539 /* Output operands and matched input operands are
2540 not inherited. The following conditions do not
2541 exactly describe the previous statement but they
2542 are pretty close. */
2543 && curr_static_id->operand[nop].type != OP_OUT
2544 && (this_alternative_matches < 0
2545 || curr_static_id->operand[nop].type != OP_IN))
2546 {
2547 int last_reload = (lra_reg_info[ORIGINAL_REGNO
2548 (operand_reg[nop])]
2549 .last_reload);
2550
2551 /* The value of reload_sum has sense only if we
2552 process insns in their order. It happens only on
2553 the first constraints sub-pass when we do most of
2554 reload work. */
2555 if (lra_constraint_iter == 1 && last_reload > bb_reload_num)
2556 reload_sum += last_reload - bb_reload_num;
2557 }
2558 /* If this is a constant that is reloaded into the
2559 desired class by copying it to memory first, count
2560 that as another reload. This is consistent with
2561 other code and is required to avoid choosing another
2562 alternative when the constant is moved into memory.
2563 Note that the test here is precisely the same as in
2564 the code below that calls force_const_mem. */
2565 if (CONST_POOL_OK_P (mode, op)
2566 && ((targetm.preferred_reload_class
2567 (op, this_alternative) == NO_REGS)
2568 || no_input_reloads_p))
2569 {
2570 const_to_mem = 1;
2571 if (! no_regs_p)
2572 losers++;
2573 }
2574
2575 /* Alternative loses if it requires a type of reload not
2576 permitted for this insn. We can always reload
2577 objects with a REG_UNUSED note. */
2578 if ((curr_static_id->operand[nop].type != OP_IN
2579 && no_output_reloads_p
2580 && ! find_reg_note (curr_insn, REG_UNUSED, op))
2581 || (curr_static_id->operand[nop].type != OP_OUT
2582 && no_input_reloads_p && ! const_to_mem)
2583 || (this_alternative_matches >= 0
2584 && (no_input_reloads_p
2585 || (no_output_reloads_p
2586 && (curr_static_id->operand
2587 [this_alternative_matches].type != OP_IN)
2588 && ! find_reg_note (curr_insn, REG_UNUSED,
2589 no_subreg_reg_operand
2590 [this_alternative_matches])))))
2591 {
2592 if (lra_dump_file != NULL)
2593 fprintf
2594 (lra_dump_file,
2595 " alt=%d: No input/otput reload -- refuse\n",
2596 nalt);
2597 goto fail;
2598 }
2599
2600 /* Alternative loses if it required class pseudo can not
2601 hold value of required mode. Such insns can be
2602 described by insn definitions with mode iterators. */
2603 if (GET_MODE (*curr_id->operand_loc[nop]) != VOIDmode
2604 && ! hard_reg_set_empty_p (this_alternative_set)
2605 /* It is common practice for constraints to use a
2606 class which does not have actually enough regs to
2607 hold the value (e.g. x86 AREG for mode requiring
2608 more one general reg). Therefore we have 2
2609 conditions to check that the reload pseudo can
2610 not hold the mode value. */
2611 && (!targetm.hard_regno_mode_ok
2612 (ira_class_hard_regs[this_alternative][0],
2613 GET_MODE (*curr_id->operand_loc[nop])))
2614 /* The above condition is not enough as the first
2615 reg in ira_class_hard_regs can be not aligned for
2616 multi-words mode values. */
2617 && (prohibited_class_reg_set_mode_p
2618 (this_alternative, this_alternative_set,
2619 GET_MODE (*curr_id->operand_loc[nop]))))
2620 {
2621 if (lra_dump_file != NULL)
2622 fprintf (lra_dump_file,
2623 " alt=%d: reload pseudo for op %d "
2624 " can not hold the mode value -- refuse\n",
2625 nalt, nop);
2626 goto fail;
2627 }
2628
2629 /* Check strong discouragement of reload of non-constant
2630 into class THIS_ALTERNATIVE. */
2631 if (! CONSTANT_P (op) && ! no_regs_p
2632 && (targetm.preferred_reload_class
2633 (op, this_alternative) == NO_REGS
2634 || (curr_static_id->operand[nop].type == OP_OUT
2635 && (targetm.preferred_output_reload_class
2636 (op, this_alternative) == NO_REGS))))
2637 {
2638 if (lra_dump_file != NULL)
2639 fprintf (lra_dump_file,
2640 " %d Non-prefered reload: reject+=%d\n",
2641 nop, LRA_MAX_REJECT);
2642 reject += LRA_MAX_REJECT;
2643 }
2644
2645 if (! (MEM_P (op) && offmemok)
2646 && ! (const_to_mem && constmemok))
2647 {
2648 /* We prefer to reload pseudos over reloading other
2649 things, since such reloads may be able to be
2650 eliminated later. So bump REJECT in other cases.
2651 Don't do this in the case where we are forcing a
2652 constant into memory and it will then win since
2653 we don't want to have a different alternative
2654 match then. */
2655 if (! (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER))
2656 {
2657 if (lra_dump_file != NULL)
2658 fprintf
2659 (lra_dump_file,
2660 " %d Non-pseudo reload: reject+=2\n",
2661 nop);
2662 reject += 2;
2663 }
2664
2665 if (! no_regs_p)
2666 reload_nregs
2667 += ira_reg_class_max_nregs[this_alternative][mode];
2668
2669 if (SMALL_REGISTER_CLASS_P (this_alternative))
2670 {
2671 if (lra_dump_file != NULL)
2672 fprintf
2673 (lra_dump_file,
2674 " %d Small class reload: reject+=%d\n",
2675 nop, LRA_LOSER_COST_FACTOR / 2);
2676 reject += LRA_LOSER_COST_FACTOR / 2;
2677 }
2678 }
2679
2680 /* We are trying to spill pseudo into memory. It is
2681 usually more costly than moving to a hard register
2682 although it might takes the same number of
2683 reloads.
2684
2685 Non-pseudo spill may happen also. Suppose a target allows both
2686 register and memory in the operand constraint alternatives,
2687 then it's typical that an eliminable register has a substition
2688 of "base + offset" which can either be reloaded by a simple
2689 "new_reg <= base + offset" which will match the register
2690 constraint, or a similar reg addition followed by further spill
2691 to and reload from memory which will match the memory
2692 constraint, but this memory spill will be much more costly
2693 usually.
2694
2695 Code below increases the reject for both pseudo and non-pseudo
2696 spill. */
2697 if (no_regs_p
2698 && !(MEM_P (op) && offmemok)
2699 && !(REG_P (op) && hard_regno[nop] < 0))
2700 {
2701 if (lra_dump_file != NULL)
2702 fprintf
2703 (lra_dump_file,
2704 " %d Spill %spseudo into memory: reject+=3\n",
2705 nop, REG_P (op) ? "" : "Non-");
2706 reject += 3;
2707 if (VECTOR_MODE_P (mode))
2708 {
2709 /* Spilling vectors into memory is usually more
2710 costly as they contain big values. */
2711 if (lra_dump_file != NULL)
2712 fprintf
2713 (lra_dump_file,
2714 " %d Spill vector pseudo: reject+=2\n",
2715 nop);
2716 reject += 2;
2717 }
2718 }
2719
2720 /* When we use an operand requiring memory in given
2721 alternative, the insn should write *and* read the
2722 value to/from memory it is costly in comparison with
2723 an insn alternative which does not use memory
2724 (e.g. register or immediate operand). We exclude
2725 memory operand for such case as we can satisfy the
2726 memory constraints by reloading address. */
2727 if (no_regs_p && offmemok && !MEM_P (op))
2728 {
2729 if (lra_dump_file != NULL)
2730 fprintf
2731 (lra_dump_file,
2732 " Using memory insn operand %d: reject+=3\n",
2733 nop);
2734 reject += 3;
2735 }
2736
2737 /* If reload requires moving value through secondary
2738 memory, it will need one more insn at least. */
2739 if (this_alternative != NO_REGS
2740 && REG_P (op) && (cl = get_reg_class (REGNO (op))) != NO_REGS
2741 && ((curr_static_id->operand[nop].type != OP_OUT
2742 && targetm.secondary_memory_needed (GET_MODE (op), cl,
2743 this_alternative))
2744 || (curr_static_id->operand[nop].type != OP_IN
2745 && (targetm.secondary_memory_needed
2746 (GET_MODE (op), this_alternative, cl)))))
2747 losers++;
2748
2749 /* Input reloads can be inherited more often than output
2750 reloads can be removed, so penalize output
2751 reloads. */
2752 if (!REG_P (op) || curr_static_id->operand[nop].type != OP_IN)
2753 {
2754 if (lra_dump_file != NULL)
2755 fprintf
2756 (lra_dump_file,
2757 " %d Non input pseudo reload: reject++\n",
2758 nop);
2759 reject++;
2760 }
2761
2762 if (MEM_P (op) && offmemok)
2763 addr_losers++;
2764 else if (curr_static_id->operand[nop].type == OP_INOUT)
2765 {
2766 if (lra_dump_file != NULL)
2767 fprintf
2768 (lra_dump_file,
2769 " %d Input/Output reload: reject+=%d\n",
2770 nop, LRA_LOSER_COST_FACTOR);
2771 reject += LRA_LOSER_COST_FACTOR;
2772 }
2773 }
2774
2775 if (early_clobber_p && ! scratch_p)
2776 {
2777 if (lra_dump_file != NULL)
2778 fprintf (lra_dump_file,
2779 " %d Early clobber: reject++\n", nop);
2780 reject++;
2781 }
2782 /* ??? We check early clobbers after processing all operands
2783 (see loop below) and there we update the costs more.
2784 Should we update the cost (may be approximately) here
2785 because of early clobber register reloads or it is a rare
2786 or non-important thing to be worth to do it. */
2787 overall = (losers * LRA_LOSER_COST_FACTOR + reject
2788 - (addr_losers == losers ? static_reject : 0));
2789 if ((best_losers == 0 || losers != 0) && best_overall < overall)
2790 {
2791 if (lra_dump_file != NULL)
2792 fprintf (lra_dump_file,
2793 " alt=%d,overall=%d,losers=%d -- refuse\n",
2794 nalt, overall, losers);
2795 goto fail;
2796 }
2797
2798 if (update_and_check_small_class_inputs (nop, this_alternative))
2799 {
2800 if (lra_dump_file != NULL)
2801 fprintf (lra_dump_file,
2802 " alt=%d, not enough small class regs -- refuse\n",
2803 nalt);
2804 goto fail;
2805 }
2806 curr_alt[nop] = this_alternative;
2807 COPY_HARD_REG_SET (curr_alt_set[nop], this_alternative_set);
2808 curr_alt_win[nop] = this_alternative_win;
2809 curr_alt_match_win[nop] = this_alternative_match_win;
2810 curr_alt_offmemok[nop] = this_alternative_offmemok;
2811 curr_alt_matches[nop] = this_alternative_matches;
2812
2813 if (this_alternative_matches >= 0
2814 && !did_match && !this_alternative_win)
2815 curr_alt_win[this_alternative_matches] = false;
2816
2817 if (early_clobber_p && operand_reg[nop] != NULL_RTX)
2818 early_clobbered_nops[early_clobbered_regs_num++] = nop;
2819 }
2820
2821 if (curr_insn_set != NULL_RTX && n_operands == 2
2822 /* Prevent processing non-move insns. */
2823 && (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG
2824 || SET_SRC (curr_insn_set) == no_subreg_reg_operand[1])
2825 && ((! curr_alt_win[0] && ! curr_alt_win[1]
2826 && REG_P (no_subreg_reg_operand[0])
2827 && REG_P (no_subreg_reg_operand[1])
2828 && (reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1])
2829 || reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0])))
2830 || (! curr_alt_win[0] && curr_alt_win[1]
2831 && REG_P (no_subreg_reg_operand[1])
2832 /* Check that we reload memory not the memory
2833 address. */
2834 && ! (curr_alt_offmemok[0]
2835 && MEM_P (no_subreg_reg_operand[0]))
2836 && reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0]))
2837 || (curr_alt_win[0] && ! curr_alt_win[1]
2838 && REG_P (no_subreg_reg_operand[0])
2839 /* Check that we reload memory not the memory
2840 address. */
2841 && ! (curr_alt_offmemok[1]
2842 && MEM_P (no_subreg_reg_operand[1]))
2843 && reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1])
2844 && (! CONST_POOL_OK_P (curr_operand_mode[1],
2845 no_subreg_reg_operand[1])
2846 || (targetm.preferred_reload_class
2847 (no_subreg_reg_operand[1],
2848 (enum reg_class) curr_alt[1]) != NO_REGS))
2849 /* If it is a result of recent elimination in move
2850 insn we can transform it into an add still by
2851 using this alternative. */
2852 && GET_CODE (no_subreg_reg_operand[1]) != PLUS)))
2853 {
2854 /* We have a move insn and a new reload insn will be similar
2855 to the current insn. We should avoid such situation as
2856 it results in LRA cycling. */
2857 if (lra_dump_file != NULL)
2858 fprintf (lra_dump_file,
2859 " Cycle danger: overall += LRA_MAX_REJECT\n");
2860 overall += LRA_MAX_REJECT;
2861 }
2862 ok_p = true;
2863 curr_alt_dont_inherit_ops_num = 0;
2864 for (nop = 0; nop < early_clobbered_regs_num; nop++)
2865 {
2866 int i, j, clobbered_hard_regno, first_conflict_j, last_conflict_j;
2867 HARD_REG_SET temp_set;
2868
2869 i = early_clobbered_nops[nop];
2870 if ((! curr_alt_win[i] && ! curr_alt_match_win[i])
2871 || hard_regno[i] < 0)
2872 continue;
2873 lra_assert (operand_reg[i] != NULL_RTX);
2874 clobbered_hard_regno = hard_regno[i];
2875 CLEAR_HARD_REG_SET (temp_set);
2876 add_to_hard_reg_set (&temp_set, biggest_mode[i], clobbered_hard_regno);
2877 first_conflict_j = last_conflict_j = -1;
2878 for (j = 0; j < n_operands; j++)
2879 if (j == i
2880 /* We don't want process insides of match_operator and
2881 match_parallel because otherwise we would process
2882 their operands once again generating a wrong
2883 code. */
2884 || curr_static_id->operand[j].is_operator)
2885 continue;
2886 else if ((curr_alt_matches[j] == i && curr_alt_match_win[j])
2887 || (curr_alt_matches[i] == j && curr_alt_match_win[i]))
2888 continue;
2889 /* If we don't reload j-th operand, check conflicts. */
2890 else if ((curr_alt_win[j] || curr_alt_match_win[j])
2891 && uses_hard_regs_p (*curr_id->operand_loc[j], temp_set))
2892 {
2893 if (first_conflict_j < 0)
2894 first_conflict_j = j;
2895 last_conflict_j = j;
2896 }
2897 if (last_conflict_j < 0)
2898 continue;
2899 /* If earlyclobber operand conflicts with another
2900 non-matching operand which is actually the same register
2901 as the earlyclobber operand, it is better to reload the
2902 another operand as an operand matching the earlyclobber
2903 operand can be also the same. */
2904 if (first_conflict_j == last_conflict_j
2905 && operand_reg[last_conflict_j] != NULL_RTX
2906 && ! curr_alt_match_win[last_conflict_j]
2907 && REGNO (operand_reg[i]) == REGNO (operand_reg[last_conflict_j]))
2908 {
2909 curr_alt_win[last_conflict_j] = false;
2910 curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++]
2911 = last_conflict_j;
2912 losers++;
2913 /* Early clobber was already reflected in REJECT. */
2914 lra_assert (reject > 0);
2915 if (lra_dump_file != NULL)
2916 fprintf
2917 (lra_dump_file,
2918 " %d Conflict early clobber reload: reject--\n",
2919 i);
2920 reject--;
2921 overall += LRA_LOSER_COST_FACTOR - 1;
2922 }
2923 else
2924 {
2925 /* We need to reload early clobbered register and the
2926 matched registers. */
2927 for (j = 0; j < n_operands; j++)
2928 if (curr_alt_matches[j] == i)
2929 {
2930 curr_alt_match_win[j] = false;
2931 losers++;
2932 overall += LRA_LOSER_COST_FACTOR;
2933 }
2934 if (! curr_alt_match_win[i])
2935 curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] = i;
2936 else
2937 {
2938 /* Remember pseudos used for match reloads are never
2939 inherited. */
2940 lra_assert (curr_alt_matches[i] >= 0);
2941 curr_alt_win[curr_alt_matches[i]] = false;
2942 }
2943 curr_alt_win[i] = curr_alt_match_win[i] = false;
2944 losers++;
2945 /* Early clobber was already reflected in REJECT. */
2946 lra_assert (reject > 0);
2947 if (lra_dump_file != NULL)
2948 fprintf
2949 (lra_dump_file,
2950 " %d Matched conflict early clobber reloads: "
2951 "reject--\n",
2952 i);
2953 reject--;
2954 overall += LRA_LOSER_COST_FACTOR - 1;
2955 }
2956 }
2957 if (lra_dump_file != NULL)
2958 fprintf (lra_dump_file, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2959 nalt, overall, losers, reload_nregs);
2960
2961 /* If this alternative can be made to work by reloading, and it
2962 needs less reloading than the others checked so far, record
2963 it as the chosen goal for reloading. */
2964 if ((best_losers != 0 && losers == 0)
2965 || (((best_losers == 0 && losers == 0)
2966 || (best_losers != 0 && losers != 0))
2967 && (best_overall > overall
2968 || (best_overall == overall
2969 /* If the cost of the reloads is the same,
2970 prefer alternative which requires minimal
2971 number of reload regs. */
2972 && (reload_nregs < best_reload_nregs
2973 || (reload_nregs == best_reload_nregs
2974 && (best_reload_sum < reload_sum
2975 || (best_reload_sum == reload_sum
2976 && nalt < goal_alt_number))))))))
2977 {
2978 for (nop = 0; nop < n_operands; nop++)
2979 {
2980 goal_alt_win[nop] = curr_alt_win[nop];
2981 goal_alt_match_win[nop] = curr_alt_match_win[nop];
2982 goal_alt_matches[nop] = curr_alt_matches[nop];
2983 goal_alt[nop] = curr_alt[nop];
2984 goal_alt_offmemok[nop] = curr_alt_offmemok[nop];
2985 }
2986 goal_alt_dont_inherit_ops_num = curr_alt_dont_inherit_ops_num;
2987 for (nop = 0; nop < curr_alt_dont_inherit_ops_num; nop++)
2988 goal_alt_dont_inherit_ops[nop] = curr_alt_dont_inherit_ops[nop];
2989 goal_alt_swapped = curr_swapped;
2990 best_overall = overall;
2991 best_losers = losers;
2992 best_reload_nregs = reload_nregs;
2993 best_reload_sum = reload_sum;
2994 goal_alt_number = nalt;
2995 }
2996 if (losers == 0)
2997 /* Everything is satisfied. Do not process alternatives
2998 anymore. */
2999 break;
3000 fail:
3001 ;
3002 }
3003 return ok_p;
3004}
3005
3006/* Make reload base reg from address AD. */
3007static rtx
3008base_to_reg (struct address_info *ad)
3009{
3010 enum reg_class cl;
3011 int code = -1;
3012 rtx new_inner = NULL_RTX;
3013 rtx new_reg = NULL_RTX;
3014 rtx_insn *insn;
3015 rtx_insn *last_insn = get_last_insn();
3016
3017 lra_assert (ad->disp == ad->disp_term);
3018 cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code,
3019 get_index_code (ad));
3020 new_reg = lra_create_new_reg (GET_MODE (*ad->base), NULL_RTX,
3021 cl, "base");
3022 new_inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), new_reg,
3023 ad->disp_term == NULL
3024 ? const0_rtx
3025 : *ad->disp_term);
3026 if (!valid_address_p (ad->mode, new_inner, ad->as))
3027 return NULL_RTX;
3028 insn = emit_insn (gen_rtx_SET (new_reg, *ad->base));
3029 code = recog_memoized (insn);
3030 if (code < 0)
3031 {
3032 delete_insns_since (last_insn);
3033 return NULL_RTX;
3034 }
3035
3036 return new_inner;
3037}
3038
3039/* Make reload base reg + disp from address AD. Return the new pseudo. */
3040static rtx
3041base_plus_disp_to_reg (struct address_info *ad)
3042{
3043 enum reg_class cl;
3044 rtx new_reg;
3045
3046 lra_assert (ad->base == ad->base_term && ad->disp == ad->disp_term);
3047 cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code,
3048 get_index_code (ad));
3049 new_reg = lra_create_new_reg (GET_MODE (*ad->base_term), NULL_RTX,
3050 cl, "base + disp");
3051 lra_emit_add (new_reg, *ad->base_term, *ad->disp_term);
3052 return new_reg;
3053}
3054
3055/* Make reload of index part of address AD. Return the new
3056 pseudo. */
3057static rtx
3058index_part_to_reg (struct address_info *ad)
3059{
3060 rtx new_reg;
3061
3062 new_reg = lra_create_new_reg (GET_MODE (*ad->index), NULL_RTX,
3063 INDEX_REG_CLASS, "index term");
3064 expand_mult (GET_MODE (*ad->index), *ad->index_term,
3065 GEN_INT (get_index_scale (ad)), new_reg, 1);
3066 return new_reg;
3067}
3068
3069/* Return true if we can add a displacement to address AD, even if that
3070 makes the address invalid. The fix-up code requires any new address
3071 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
3072static bool
3073can_add_disp_p (struct address_info *ad)
3074{
3075 return (!ad->autoinc_p
3076 && ad->segment == NULL
3077 && ad->base == ad->base_term
3078 && ad->disp == ad->disp_term);
3079}
3080
3081/* Make equiv substitution in address AD. Return true if a substitution
3082 was made. */
3083static bool
3084equiv_address_substitution (struct address_info *ad)
3085{
3086 rtx base_reg, new_base_reg, index_reg, new_index_reg, *base_term, *index_term;
3087 HOST_WIDE_INT disp, scale;
3088 bool change_p;
3089
3090 base_term = strip_subreg (ad->base_term);
3091 if (base_term == NULL)
3092 base_reg = new_base_reg = NULL_RTX;
3093 else
3094 {
3095 base_reg = *base_term;
3096 new_base_reg = get_equiv_with_elimination (base_reg, curr_insn);
3097 }
3098 index_term = strip_subreg (ad->index_term);
3099 if (index_term == NULL)
3100 index_reg = new_index_reg = NULL_RTX;
3101 else
3102 {
3103 index_reg = *index_term;
3104 new_index_reg = get_equiv_with_elimination (index_reg, curr_insn);
3105 }
3106 if (base_reg == new_base_reg && index_reg == new_index_reg)
3107 return false;
3108 disp = 0;
3109 change_p = false;
3110 if (lra_dump_file != NULL)
3111 {
3112 fprintf (lra_dump_file, "Changing address in insn %d ",
3113 INSN_UID (curr_insn));
3114 dump_value_slim (lra_dump_file, *ad->outer, 1);
3115 }
3116 if (base_reg != new_base_reg)
3117 {
3118 if (REG_P (new_base_reg))
3119 {
3120 *base_term = new_base_reg;
3121 change_p = true;
3122 }
3123 else if (GET_CODE (new_base_reg) == PLUS
3124 && REG_P (XEXP (new_base_reg, 0))
3125 && CONST_INT_P (XEXP (new_base_reg, 1))
3126 && can_add_disp_p (ad))
3127 {
3128 disp += INTVAL (XEXP (new_base_reg, 1));
3129 *base_term = XEXP (new_base_reg, 0);
3130 change_p = true;
3131 }
3132 if (ad->base_term2 != NULL)
3133 *ad->base_term2 = *ad->base_term;
3134 }
3135 if (index_reg != new_index_reg)
3136 {
3137 if (REG_P (new_index_reg))
3138 {
3139 *index_term = new_index_reg;
3140 change_p = true;
3141 }
3142 else if (GET_CODE (new_index_reg) == PLUS
3143 && REG_P (XEXP (new_index_reg, 0))
3144 && CONST_INT_P (XEXP (new_index_reg, 1))
3145 && can_add_disp_p (ad)
3146 && (scale = get_index_scale (ad)))
3147 {
3148 disp += INTVAL (XEXP (new_index_reg, 1)) * scale;
3149 *index_term = XEXP (new_index_reg, 0);
3150 change_p = true;
3151 }
3152 }
3153 if (disp != 0)
3154 {
3155 if (ad->disp != NULL)
3156 *ad->disp = plus_constant (GET_MODE (*ad->inner), *ad->disp, disp);
3157 else
3158 {
3159 *ad->inner = plus_constant (GET_MODE (*ad->inner), *ad->inner, disp);
3160 update_address (ad);
3161 }
3162 change_p = true;
3163 }
3164 if (lra_dump_file != NULL)
3165 {
3166 if (! change_p)
3167 fprintf (lra_dump_file, " -- no change\n");
3168 else
3169 {
3170 fprintf (lra_dump_file, " on equiv ");
3171 dump_value_slim (lra_dump_file, *ad->outer, 1);
3172 fprintf (lra_dump_file, "\n");
3173 }
3174 }
3175 return change_p;
3176}
3177
3178/* Major function to make reloads for an address in operand NOP or
3179 check its correctness (If CHECK_ONLY_P is true). The supported
3180 cases are:
3181
3182 1) an address that existed before LRA started, at which point it
3183 must have been valid. These addresses are subject to elimination
3184 and may have become invalid due to the elimination offset being out
3185 of range.
3186
3187 2) an address created by forcing a constant to memory
3188 (force_const_to_mem). The initial form of these addresses might
3189 not be valid, and it is this function's job to make them valid.
3190
3191 3) a frame address formed from a register and a (possibly zero)
3192 constant offset. As above, these addresses might not be valid and
3193 this function must make them so.
3194
3195 Add reloads to the lists *BEFORE and *AFTER. We might need to add
3196 reloads to *AFTER because of inc/dec, {pre, post} modify in the
3197 address. Return true for any RTL change.
3198
3199 The function is a helper function which does not produce all
3200 transformations (when CHECK_ONLY_P is false) which can be
3201 necessary. It does just basic steps. To do all necessary
3202 transformations use function process_address. */
3203static bool
3204process_address_1 (int nop, bool check_only_p,
3205 rtx_insn **before, rtx_insn **after)
3206{
3207 struct address_info ad;
3208 rtx new_reg;
3209 HOST_WIDE_INT scale;
3210 rtx op = *curr_id->operand_loc[nop];
3211 const char *constraint = curr_static_id->operand[nop].constraint;
3212 enum constraint_num cn = lookup_constraint (constraint);
3213 bool change_p = false;
3214
3215 if (MEM_P (op)
3216 && GET_MODE (op) == BLKmode
3217 && GET_CODE (XEXP (op, 0)) == SCRATCH)
3218 return false;
3219
3220 if (insn_extra_address_constraint (cn))
3221 decompose_lea_address (&ad, curr_id->operand_loc[nop]);
3222 /* Do not attempt to decompose arbitrary addresses generated by combine
3223 for asm operands with loose constraints, e.g 'X'. */
3224 else if (MEM_P (op)
3225 && !(INSN_CODE (curr_insn) < 0
3226 && get_constraint_type (cn) == CT_FIXED_FORM
3227 && constraint_satisfied_p (op, cn)))
3228 decompose_mem_address (&ad, op);
3229 else if (GET_CODE (op) == SUBREG
3230 && MEM_P (SUBREG_REG (op)))
3231 decompose_mem_address (&ad, SUBREG_REG (op));
3232 else
3233 return false;
3234 /* If INDEX_REG_CLASS is assigned to base_term already and isn't to
3235 index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
3236 when INDEX_REG_CLASS is a single register class. */
3237 if (ad.base_term != NULL
3238 && ad.index_term != NULL
3239 && ira_class_hard_regs_num[INDEX_REG_CLASS] == 1
3240 && REG_P (*ad.base_term)
3241 && REG_P (*ad.index_term)
3242 && in_class_p (*ad.base_term, INDEX_REG_CLASS, NULL)
3243 && ! in_class_p (*ad.index_term, INDEX_REG_CLASS, NULL))
3244 {
3245 std::swap (ad.base, ad.index);
3246 std::swap (ad.base_term, ad.index_term);
3247 }
3248 if (! check_only_p)
3249 change_p = equiv_address_substitution (&ad);
3250 if (ad.base_term != NULL
3251 && (process_addr_reg
3252 (ad.base_term, check_only_p, before,
3253 (ad.autoinc_p
3254 && !(REG_P (*ad.base_term)
3255 && find_regno_note (curr_insn, REG_DEAD,
3256 REGNO (*ad.base_term)) != NULL_RTX)
3257 ? after : NULL),
3258 base_reg_class (ad.mode, ad.as, ad.base_outer_code,
3259 get_index_code (&ad)))))
3260 {
3261 change_p = true;
3262 if (ad.base_term2 != NULL)
3263 *ad.base_term2 = *ad.base_term;
3264 }
3265 if (ad.index_term != NULL
3266 && process_addr_reg (ad.index_term, check_only_p,
3267 before, NULL, INDEX_REG_CLASS))
3268 change_p = true;
3269
3270 /* Target hooks sometimes don't treat extra-constraint addresses as
3271 legitimate address_operands, so handle them specially. */
3272 if (insn_extra_address_constraint (cn)
3273 && satisfies_address_constraint_p (&ad, cn))
3274 return change_p;
3275
3276 if (check_only_p)
3277 return change_p;
3278
3279 /* There are three cases where the shape of *AD.INNER may now be invalid:
3280
3281 1) the original address was valid, but either elimination or
3282 equiv_address_substitution was applied and that made
3283 the address invalid.
3284
3285 2) the address is an invalid symbolic address created by
3286 force_const_to_mem.
3287
3288 3) the address is a frame address with an invalid offset.
3289
3290 4) the address is a frame address with an invalid base.
3291
3292 All these cases involve a non-autoinc address, so there is no
3293 point revalidating other types. */
3294 if (ad.autoinc_p || valid_address_p (&ad))
3295 return change_p;
3296
3297 /* Any index existed before LRA started, so we can assume that the
3298 presence and shape of the index is valid. */
3299 push_to_sequence (*before);
3300 lra_assert (ad.disp == ad.disp_term);
3301 if (ad.base == NULL)
3302 {
3303 if (ad.index == NULL)
3304 {
3305 rtx_insn *insn;
3306 rtx_insn *last = get_last_insn ();
3307 int code = -1;
3308 enum reg_class cl = base_reg_class (ad.mode, ad.as,
3309 SCRATCH, SCRATCH);
3310 rtx addr = *ad.inner;
3311
3312 new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr");
3313 if (HAVE_lo_sum)
3314 {
3315 /* addr => lo_sum (new_base, addr), case (2) above. */
3316 insn = emit_insn (gen_rtx_SET
3317 (new_reg,
3318 gen_rtx_HIGH (Pmode, copy_rtx (addr))));
3319 code = recog_memoized (insn);
3320 if (code >= 0)
3321 {
3322 *ad.inner = gen_rtx_LO_SUM (Pmode, new_reg, addr);
3323 if (! valid_address_p (ad.mode, *ad.outer, ad.as))
3324 {
3325 /* Try to put lo_sum into register. */
3326 insn = emit_insn (gen_rtx_SET
3327 (new_reg,
3328 gen_rtx_LO_SUM (Pmode, new_reg, addr)));
3329 code = recog_memoized (insn);
3330 if (code >= 0)
3331 {
3332 *ad.inner = new_reg;
3333 if (! valid_address_p (ad.mode, *ad.outer, ad.as))
3334 {
3335 *ad.inner = addr;
3336 code = -1;
3337 }
3338 }
3339
3340 }
3341 }
3342 if (code < 0)
3343 delete_insns_since (last);
3344 }
3345
3346 if (code < 0)
3347 {
3348 /* addr => new_base, case (2) above. */
3349 lra_emit_move (new_reg, addr);
3350
3351 for (insn = last == NULL_RTX ? get_insns () : NEXT_INSN (last);
3352 insn != NULL_RTX;
3353 insn = NEXT_INSN (insn))
3354 if (recog_memoized (insn) < 0)
3355 break;
3356 if (insn != NULL_RTX)
3357 {
3358 /* Do nothing if we cannot generate right insns.
3359 This is analogous to reload pass behavior. */
3360 delete_insns_since (last);
3361 end_sequence ();
3362 return false;
3363 }
3364 *ad.inner = new_reg;
3365 }
3366 }
3367 else
3368 {
3369 /* index * scale + disp => new base + index * scale,
3370 case (1) above. */
3371 enum reg_class cl = base_reg_class (ad.mode, ad.as, PLUS,
3372 GET_CODE (*ad.index));
3373
3374 lra_assert (INDEX_REG_CLASS != NO_REGS);
3375 new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "disp");
3376 lra_emit_move (new_reg, *ad.disp);
3377 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg),
3378 new_reg, *ad.index);
3379 }
3380 }
3381 else if (ad.index == NULL)
3382 {
3383 int regno;
3384 enum reg_class cl;
3385 rtx set;
3386 rtx_insn *insns, *last_insn;
3387 /* Try to reload base into register only if the base is invalid
3388 for the address but with valid offset, case (4) above. */
3389 start_sequence ();
3390 new_reg = base_to_reg (&ad);
3391
3392 /* base + disp => new base, cases (1) and (3) above. */
3393 /* Another option would be to reload the displacement into an
3394 index register. However, postreload has code to optimize
3395 address reloads that have the same base and different
3396 displacements, so reloading into an index register would
3397 not necessarily be a win. */
3398 if (new_reg == NULL_RTX)
3399 new_reg = base_plus_disp_to_reg (&ad);
3400 insns = get_insns ();
3401 last_insn = get_last_insn ();
3402 /* If we generated at least two insns, try last insn source as
3403 an address. If we succeed, we generate one less insn. */
3404 if (last_insn != insns && (set = single_set (last_insn)) != NULL_RTX
3405 && GET_CODE (SET_SRC (set)) == PLUS
3406 && REG_P (XEXP (SET_SRC (set), 0))
3407 && CONSTANT_P (XEXP (SET_SRC (set), 1)))
3408 {
3409 *ad.inner = SET_SRC (set);
3410 if (valid_address_p (ad.mode, *ad.outer, ad.as))
3411 {
3412 *ad.base_term = XEXP (SET_SRC (set), 0);
3413 *ad.disp_term = XEXP (SET_SRC (set), 1);
3414 cl = base_reg_class (ad.mode, ad.as, ad.base_outer_code,
3415 get_index_code (&ad));
3416 regno = REGNO (*ad.base_term);
3417 if (regno >= FIRST_PSEUDO_REGISTER
3418 && cl != lra_get_allocno_class (regno))
3419 lra_change_class (regno, cl, " Change to", true);
3420 new_reg = SET_SRC (set);
3421 delete_insns_since (PREV_INSN (last_insn));
3422 }
3423 }
3424 /* Try if target can split displacement into legitimite new disp
3425 and offset. If it's the case, we replace the last insn with
3426 insns for base + offset => new_reg and set new_reg + new disp
3427 to *ad.inner. */
3428 last_insn = get_last_insn ();
3429 if ((set = single_set (last_insn)) != NULL_RTX
3430 && GET_CODE (SET_SRC (set)) == PLUS
3431 && REG_P (XEXP (SET_SRC (set), 0))
3432 && REGNO (XEXP (SET_SRC (set), 0)) < FIRST_PSEUDO_REGISTER
3433 && CONST_INT_P (XEXP (SET_SRC (set), 1)))
3434 {
3435 rtx addend, disp = XEXP (SET_SRC (set), 1);
3436 if (targetm.legitimize_address_displacement (&disp, &addend,
3437 ad.mode))
3438 {
3439 rtx_insn *new_insns;
3440 start_sequence ();
3441 lra_emit_add (new_reg, XEXP (SET_SRC (set), 0), addend);
3442 new_insns = get_insns ();
3443 end_sequence ();
3444 new_reg = gen_rtx_PLUS (Pmode, new_reg, disp);
3445 delete_insns_since (PREV_INSN (last_insn));
3446 add_insn (new_insns);
3447 insns = get_insns ();
3448 }
3449 }
3450 end_sequence ();
3451 emit_insn (insns);
3452 *ad.inner = new_reg;
3453 }
3454 else if (ad.disp_term != NULL)
3455 {
3456 /* base + scale * index + disp => new base + scale * index,
3457 case (1) above. */
3458 new_reg = base_plus_disp_to_reg (&ad);
3459 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg),
3460 new_reg, *ad.index);
3461 }
3462 else if ((scale = get_index_scale (&ad)) == 1)
3463 {
3464 /* The last transformation to one reg will be made in
3465 curr_insn_transform function. */
3466 end_sequence ();
3467 return false;
3468 }
3469 else if (scale != 0)
3470 {
3471 /* base + scale * index => base + new_reg,
3472 case (1) above.
3473 Index part of address may become invalid. For example, we
3474 changed pseudo on the equivalent memory and a subreg of the
3475 pseudo onto the memory of different mode for which the scale is
3476 prohibitted. */
3477 new_reg = index_part_to_reg (&ad);
3478 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg),
3479 *ad.base_term, new_reg);
3480 }
3481 else
3482 {
3483 enum reg_class cl = base_reg_class (ad.mode, ad.as,
3484 SCRATCH, SCRATCH);
3485 rtx addr = *ad.inner;
3486
3487 new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr");
3488 /* addr => new_base. */
3489 lra_emit_move (new_reg, addr);
3490 *ad.inner = new_reg;
3491 }
3492 *before = get_insns ();
3493 end_sequence ();
3494 return true;
3495}
3496
3497/* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3498 Use process_address_1 as a helper function. Return true for any
3499 RTL changes.
3500
3501 If CHECK_ONLY_P is true, just check address correctness. Return
3502 false if the address correct. */
3503static bool
3504process_address (int nop, bool check_only_p,
3505 rtx_insn **before, rtx_insn **after)
3506{
3507 bool res = false;
3508
3509 while (process_address_1 (nop, check_only_p, before, after))
3510 {
3511 if (check_only_p)
3512 return true;
3513 res = true;
3514 }
3515 return res;
3516}
3517
3518/* Emit insns to reload VALUE into a new register. VALUE is an
3519 auto-increment or auto-decrement RTX whose operand is a register or
3520 memory location; so reloading involves incrementing that location.
3521 IN is either identical to VALUE, or some cheaper place to reload
3522 value being incremented/decremented from.
3523
3524 INC_AMOUNT is the number to increment or decrement by (always
3525 positive and ignored for POST_MODIFY/PRE_MODIFY).
3526
3527 Return pseudo containing the result. */
3528static rtx
3529emit_inc (enum reg_class new_rclass, rtx in, rtx value, int inc_amount)
3530{
3531 /* REG or MEM to be copied and incremented. */
3532 rtx incloc = XEXP (value, 0);
3533 /* Nonzero if increment after copying. */
3534 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
3535 || GET_CODE (value) == POST_MODIFY);
3536 rtx_insn *last;
3537 rtx inc;
3538 rtx_insn *add_insn;
3539 int code;
3540 rtx real_in = in == value ? incloc : in;
3541 rtx result;
3542 bool plus_p = true;
3543
3544 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
3545 {
3546 lra_assert (GET_CODE (XEXP (value, 1)) == PLUS
3547 || GET_CODE (XEXP (value, 1)) == MINUS);
3548 lra_assert (rtx_equal_p (XEXP (XEXP (value, 1), 0), XEXP (value, 0)));
3549 plus_p = GET_CODE (XEXP (value, 1)) == PLUS;
3550 inc = XEXP (XEXP (value, 1), 1);
3551 }
3552 else
3553 {
3554 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
3555 inc_amount = -inc_amount;
3556
3557 inc = GEN_INT (inc_amount);
3558 }
3559
3560 if (! post && REG_P (incloc))
3561 result = incloc;
3562 else
3563 result = lra_create_new_reg (GET_MODE (value), value, new_rclass,
3564 "INC/DEC result");
3565
3566 if (real_in != result)
3567 {
3568 /* First copy the location to the result register. */
3569 lra_assert (REG_P (result));
3570 emit_insn (gen_move_insn (result, real_in));
3571 }
3572
3573 /* We suppose that there are insns to add/sub with the constant
3574 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3575 old reload worked with this assumption. If the assumption
3576 becomes wrong, we should use approach in function
3577 base_plus_disp_to_reg. */
3578 if (in == value)
3579 {
3580 /* See if we can directly increment INCLOC. */
3581 last = get_last_insn ();
3582 add_insn = emit_insn (plus_p
3583 ? gen_add2_insn (incloc, inc)
3584 : gen_sub2_insn (incloc, inc));
3585
3586 code = recog_memoized (add_insn);
3587 if (code >= 0)
3588 {
3589 if (! post && result != incloc)
3590 emit_insn (gen_move_insn (result, incloc));
3591 return result;
3592 }
3593 delete_insns_since (last);
3594 }
3595
3596 /* If couldn't do the increment directly, must increment in RESULT.
3597 The way we do this depends on whether this is pre- or
3598 post-increment. For pre-increment, copy INCLOC to the reload
3599 register, increment it there, then save back. */
3600 if (! post)
3601 {
3602 if (real_in != result)
3603 emit_insn (gen_move_insn (result, real_in));
3604 if (plus_p)
3605 emit_insn (gen_add2_insn (result, inc));
3606 else
3607 emit_insn (gen_sub2_insn (result, inc));
3608 if (result != incloc)
3609 emit_insn (gen_move_insn (incloc, result));
3610 }
3611 else
3612 {
3613 /* Post-increment.
3614
3615 Because this might be a jump insn or a compare, and because
3616 RESULT may not be available after the insn in an input
3617 reload, we must do the incrementing before the insn being
3618 reloaded for.
3619
3620 We have already copied IN to RESULT. Increment the copy in
3621 RESULT, save that back, then decrement RESULT so it has
3622 the original value. */
3623 if (plus_p)
3624 emit_insn (gen_add2_insn (result, inc));
3625 else
3626 emit_insn (gen_sub2_insn (result, inc));
3627 emit_insn (gen_move_insn (incloc, result));
3628 /* Restore non-modified value for the result. We prefer this
3629 way because it does not require an additional hard
3630 register. */
3631 if (plus_p)
3632 {
3633 if (CONST_INT_P (inc))
3634 emit_insn (gen_add2_insn (result,
3635 gen_int_mode (-INTVAL (inc),
3636 GET_MODE (result))));
3637 else
3638 emit_insn (gen_sub2_insn (result, inc));
3639 }
3640 else
3641 emit_insn (gen_add2_insn (result, inc));
3642 }
3643 return result;
3644}
3645
3646/* Return true if the current move insn does not need processing as we
3647 already know that it satisfies its constraints. */
3648static bool
3649simple_move_p (void)
3650{
3651 rtx dest, src;
3652 enum reg_class dclass, sclass;
3653
3654 lra_assert (curr_insn_set != NULL_RTX);
3655 dest = SET_DEST (curr_insn_set);
3656 src = SET_SRC (curr_insn_set);
3657
3658 /* If the instruction has multiple sets we need to process it even if it
3659 is single_set. This can happen if one or more of the SETs are dead.
3660 See PR73650. */
3661 if (multiple_sets (curr_insn))
3662 return false;
3663
3664 return ((dclass = get_op_class (dest)) != NO_REGS
3665 && (sclass = get_op_class (src)) != NO_REGS
3666 /* The backend guarantees that register moves of cost 2
3667 never need reloads. */
3668 && targetm.register_move_cost (GET_MODE (src), sclass, dclass) == 2);
3669 }
3670
3671/* Swap operands NOP and NOP + 1. */
3672static inline void
3673swap_operands (int nop)
3674{
3675 std::swap (curr_operand_mode[nop], curr_operand_mode[nop + 1]);
3676 std::swap (original_subreg_reg_mode[nop], original_subreg_reg_mode[nop + 1]);
3677 std::swap (*curr_id->operand_loc[nop], *curr_id->operand_loc[nop + 1]);
3678 std::swap (equiv_substition_p[nop], equiv_substition_p[nop + 1]);
3679 /* Swap the duplicates too. */
3680 lra_update_dup (curr_id, nop);
3681 lra_update_dup (curr_id, nop + 1);
3682}
3683
3684/* Main entry point of the constraint code: search the body of the
3685 current insn to choose the best alternative. It is mimicking insn
3686 alternative cost calculation model of former reload pass. That is
3687 because machine descriptions were written to use this model. This
3688 model can be changed in future. Make commutative operand exchange
3689 if it is chosen.
3690
3691 if CHECK_ONLY_P is false, do RTL changes to satisfy the
3692 constraints. Return true if any change happened during function
3693 call.
3694
3695 If CHECK_ONLY_P is true then don't do any transformation. Just
3696 check that the insn satisfies all constraints. If the insn does
3697 not satisfy any constraint, return true. */
3698static bool
3699curr_insn_transform (bool check_only_p)
3700{
3701 int i, j, k;
3702 int n_operands;
3703 int n_alternatives;
3704 int n_outputs;
3705 int commutative;
3706 signed char goal_alt_matched[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS];
3707 signed char match_inputs[MAX_RECOG_OPERANDS + 1];
3708 signed char outputs[MAX_RECOG_OPERANDS + 1];
3709 rtx_insn *before, *after;
3710 bool alt_p = false;
3711 /* Flag that the insn has been changed through a transformation. */
3712 bool change_p;
3713 bool sec_mem_p;
3714 bool use_sec_mem_p;
3715 int max_regno_before;
3716 int reused_alternative_num;
3717
3718 curr_insn_set = single_set (curr_insn);
3719 if (curr_insn_set != NULL_RTX && simple_move_p ())
3720 return false;
3721
3722 no_input_reloads_p = no_output_reloads_p = false;
3723 goal_alt_number = -1;
3724 change_p = sec_mem_p = false;
3725 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3726 reloads; neither are insns that SET cc0. Insns that use CC0 are
3727 not allowed to have any input reloads. */
3728 if (JUMP_P (curr_insn) || CALL_P (curr_insn))
3729 no_output_reloads_p = true;
3730
3731 if (HAVE_cc0 && reg_referenced_p (cc0_rtx, PATTERN (curr_insn)))
3732 no_input_reloads_p = true;
3733 if (HAVE_cc0 && reg_set_p (cc0_rtx, PATTERN (curr_insn)))
3734 no_output_reloads_p = true;
3735
3736 n_operands = curr_static_id->n_operands;
3737 n_alternatives = curr_static_id->n_alternatives;
3738
3739 /* Just return "no reloads" if insn has no operands with
3740 constraints. */
3741 if (n_operands == 0 || n_alternatives == 0)
3742 return false;
3743
3744 max_regno_before = max_reg_num ();
3745
3746 for (i = 0; i < n_operands; i++)
3747 {
3748 goal_alt_matched[i][0] = -1;
3749 goal_alt_matches[i] = -1;
3750 }
3751
3752 commutative = curr_static_id->commutative;
3753
3754 /* Now see what we need for pseudos that didn't get hard regs or got
3755 the wrong kind of hard reg. For this, we must consider all the
3756 operands together against the register constraints. */
3757
3758 best_losers = best_overall = INT_MAX;
3759 best_reload_sum = 0;
3760
3761 curr_swapped = false;
3762 goal_alt_swapped = false;
3763
3764 if (! check_only_p)
3765 /* Make equivalence substitution and memory subreg elimination
3766 before address processing because an address legitimacy can
3767 depend on memory mode. */
3768 for (i = 0; i < n_operands; i++)
3769 {
3770 rtx op, subst, old;
3771 bool op_change_p = false;
3772
3773 if (curr_static_id->operand[i].is_operator)
3774 continue;
3775
3776 old = op = *curr_id->operand_loc[i];
3777 if (GET_CODE (old) == SUBREG)
3778 old = SUBREG_REG (old);
3779 subst = get_equiv_with_elimination (old, curr_insn);
3780 original_subreg_reg_mode[i] = VOIDmode;
3781 equiv_substition_p[i] = false;
3782 if (subst != old)
3783 {
3784 equiv_substition_p[i] = true;
3785 subst = copy_rtx (subst);
3786 lra_assert (REG_P (old));
3787 if (GET_CODE (op) != SUBREG)
3788 *curr_id->operand_loc[i] = subst;
3789 else
3790 {
3791 SUBREG_REG (op) = subst;
3792 if (GET_MODE (subst) == VOIDmode)
3793 original_subreg_reg_mode[i] = GET_MODE (old);
3794 }
3795 if (lra_dump_file != NULL)
3796 {
3797 fprintf (lra_dump_file,
3798 "Changing pseudo %d in operand %i of insn %u on equiv ",
3799 REGNO (old), i, INSN_UID (curr_insn));
3800 dump_value_slim (lra_dump_file, subst, 1);
3801 fprintf (lra_dump_file, "\n");
3802 }
3803 op_change_p = change_p = true;
3804 }
3805 if (simplify_operand_subreg (i, GET_MODE (old)) || op_change_p)
3806 {
3807 change_p = true;
3808 lra_update_dup (curr_id, i);
3809 }
3810 }
3811
3812 /* Reload address registers and displacements. We do it before
3813 finding an alternative because of memory constraints. */
3814 before = after = NULL;
3815 for (i = 0; i < n_operands; i++)
3816 if (! curr_static_id->operand[i].is_operator
3817 && process_address (i, check_only_p, &before, &after))
3818 {
3819 if (check_only_p)
3820 return true;
3821 change_p = true;
3822 lra_update_dup (curr_id, i);
3823 }
3824
3825 if (change_p)
3826 /* If we've changed the instruction then any alternative that
3827 we chose previously may no longer be valid. */
3828 lra_set_used_insn_alternative (curr_insn, -1);
3829
3830 if (! check_only_p && curr_insn_set != NULL_RTX
3831 && check_and_process_move (&change_p, &sec_mem_p))
3832 return change_p;
3833
3834 try_swapped:
3835
3836 reused_alternative_num = check_only_p ? -1 : curr_id->used_insn_alternative;
3837 if (lra_dump_file != NULL && reused_alternative_num >= 0)
3838 fprintf (lra_dump_file, "Reusing alternative %d for insn #%u\n",
3839 reused_alternative_num, INSN_UID (curr_insn));
3840
3841 if (process_alt_operands (reused_alternative_num))
3842 alt_p = true;
3843
3844 if (check_only_p)
3845 return ! alt_p || best_losers != 0;
3846
3847 /* If insn is commutative (it's safe to exchange a certain pair of
3848 operands) then we need to try each alternative twice, the second
3849 time matching those two operands as if we had exchanged them. To
3850 do this, really exchange them in operands.
3851
3852 If we have just tried the alternatives the second time, return
3853 operands to normal and drop through. */
3854
3855 if (reused_alternative_num < 0 && commutative >= 0)
3856 {
3857 curr_swapped = !curr_swapped;
3858 if (curr_swapped)
3859 {
3860 swap_operands (commutative);
3861 goto try_swapped;
3862 }
3863 else
3864 swap_operands (commutative);
3865 }
3866
3867 if (! alt_p && ! sec_mem_p)
3868 {
3869 /* No alternative works with reloads?? */
3870 if (INSN_CODE (curr_insn) >= 0)
3871 fatal_insn ("unable to generate reloads for:", curr_insn);
3872 error_for_asm (curr_insn,
3873 "inconsistent operand constraints in an %<asm%>");
3874 /* Avoid further trouble with this insn. Don't generate use
3875 pattern here as we could use the insn SP offset. */
3876 lra_set_insn_deleted (curr_insn);
3877 return true;
3878 }
3879
3880 /* If the best alternative is with operands 1 and 2 swapped, swap
3881 them. Update the operand numbers of any reloads already
3882 pushed. */
3883
3884 if (goal_alt_swapped)
3885 {
3886 if (lra_dump_file != NULL)
3887 fprintf (lra_dump_file, " Commutative operand exchange in insn %u\n",
3888 INSN_UID (curr_insn));
3889
3890 /* Swap the duplicates too. */
3891 swap_operands (commutative);
3892 change_p = true;
3893 }
3894
3895 /* Some targets' TARGET_SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3896 too conservatively. So we use the secondary memory only if there
3897 is no any alternative without reloads. */
3898 use_sec_mem_p = false;
3899 if (! alt_p)
3900 use_sec_mem_p = true;
3901 else if (sec_mem_p)
3902 {
3903 for (i = 0; i < n_operands; i++)
3904 if (! goal_alt_win[i] && ! goal_alt_match_win[i])
3905 break;
3906 use_sec_mem_p = i < n_operands;
3907 }
3908
3909 if (use_sec_mem_p)
3910 {
3911 int in = -1, out = -1;
3912 rtx new_reg, src, dest, rld;
3913 machine_mode sec_mode, rld_mode;
3914
3915 lra_assert (curr_insn_set != NULL_RTX && sec_mem_p);
3916 dest = SET_DEST (curr_insn_set);
3917 src = SET_SRC (curr_insn_set);
3918 for (i = 0; i < n_operands; i++)
3919 if (*curr_id->operand_loc[i] == dest)
3920 out = i;
3921 else if (*curr_id->operand_loc[i] == src)
3922 in = i;
3923 for (i = 0; i < curr_static_id->n_dups; i++)
3924 if (out < 0 && *curr_id->dup_loc[i] == dest)
3925 out = curr_static_id->dup_num[i];
3926 else if (in < 0 && *curr_id->dup_loc[i] == src)
3927 in = curr_static_id->dup_num[i];
3928 lra_assert (out >= 0 && in >= 0
3929 && curr_static_id->operand[out].type == OP_OUT
3930 && curr_static_id->operand[in].type == OP_IN);
3931 rld = partial_subreg_p (GET_MODE (src), GET_MODE (dest)) ? src : dest;
3932 rld_mode = GET_MODE (rld);
3933 sec_mode = targetm.secondary_memory_needed_mode (rld_mode);
3934 new_reg = lra_create_new_reg (sec_mode, NULL_RTX,
3935 NO_REGS, "secondary");
3936 /* If the mode is changed, it should be wider. */
3937 lra_assert (!partial_subreg_p (sec_mode, rld_mode));
3938 if (sec_mode != rld_mode)
3939 {
3940 /* If the target says specifically to use another mode for
3941 secondary memory moves we can not reuse the original
3942 insn. */
3943 after = emit_spill_move (false, new_reg, dest);
3944 lra_process_new_insns (curr_insn, NULL, after,
3945 "Inserting the sec. move");
3946 /* We may have non null BEFORE here (e.g. after address
3947 processing. */
3948 push_to_sequence (before);
3949 before = emit_spill_move (true, new_reg, src);
3950 emit_insn (before);
3951 before = get_insns ();
3952 end_sequence ();
3953 lra_process_new_insns (curr_insn, before, NULL, "Changing on");
3954 lra_set_insn_deleted (curr_insn);
3955 }
3956 else if (dest == rld)
3957 {
3958 *curr_id->operand_loc[out] = new_reg;
3959 lra_update_dup (curr_id, out);
3960 after = emit_spill_move (false, new_reg, dest);
3961 lra_process_new_insns (curr_insn, NULL, after,
3962 "Inserting the sec. move");
3963 }
3964 else
3965 {
3966 *curr_id->operand_loc[in] = new_reg;
3967 lra_update_dup (curr_id, in);
3968 /* See comments above. */
3969 push_to_sequence (before);
3970 before = emit_spill_move (true, new_reg, src);
3971 emit_insn (before);
3972 before = get_insns ();
3973 end_sequence ();
3974 lra_process_new_insns (curr_insn, before, NULL,
3975 "Inserting the sec. move");
3976 }
3977 lra_update_insn_regno_info (curr_insn);
3978 return true;
3979 }
3980
3981 lra_assert (goal_alt_number >= 0);
3982 lra_set_used_insn_alternative (curr_insn, goal_alt_number);
3983
3984 if (lra_dump_file != NULL)
3985 {
3986 const char *p;
3987
3988 fprintf (lra_dump_file, " Choosing alt %d in insn %u:",
3989 goal_alt_number, INSN_UID (curr_insn));
3990 for (i = 0; i < n_operands; i++)
3991 {
3992 p = (curr_static_id->operand_alternative
3993 [goal_alt_number * n_operands + i].constraint);
3994 if (*p == '\0')
3995 continue;
3996 fprintf (lra_dump_file, " (%d) ", i);
3997 for (; *p != '\0' && *p != ',' && *p != '#'; p++)
3998 fputc (*p, lra_dump_file);
3999 }
4000 if (INSN_CODE (curr_insn) >= 0
4001 && (p = get_insn_name (INSN_CODE (curr_insn))) != NULL)
4002 fprintf (lra_dump_file, " {%s}", p);
4003 if (curr_id->sp_offset != 0)
4004 fprintf (lra_dump_file, " (sp_off=%" HOST_WIDE_INT_PRINT "d)",
4005 curr_id->sp_offset);
4006 fprintf (lra_dump_file, "\n");
4007 }
4008
4009 /* Right now, for any pair of operands I and J that are required to
4010 match, with J < I, goal_alt_matches[I] is J. Add I to
4011 goal_alt_matched[J]. */
4012
4013 for (i = 0; i < n_operands; i++)
4014 if ((j = goal_alt_matches[i]) >= 0)
4015 {
4016 for (k = 0; goal_alt_matched[j][k] >= 0; k++)
4017 ;
4018 /* We allow matching one output operand and several input
4019 operands. */
4020 lra_assert (k == 0
4021 || (curr_static_id->operand[j].type == OP_OUT
4022 && curr_static_id->operand[i].type == OP_IN
4023 && (curr_static_id->operand
4024 [goal_alt_matched[j][0]].type == OP_IN)));
4025 goal_alt_matched[j][k] = i;
4026 goal_alt_matched[j][k + 1] = -1;
4027 }
4028
4029 for (i = 0; i < n_operands; i++)
4030 goal_alt_win[i] |= goal_alt_match_win[i];
4031
4032 /* Any constants that aren't allowed and can't be reloaded into
4033 registers are here changed into memory references. */
4034 for (i = 0; i < n_operands; i++)
4035 if (goal_alt_win[i])
4036 {
4037 int regno;
4038 enum reg_class new_class;
4039 rtx reg = *curr_id->operand_loc[i];
4040
4041 if (GET_CODE (reg) == SUBREG)
4042 reg = SUBREG_REG (reg);
4043
4044 if (REG_P (reg) && (regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER)
4045 {
4046 bool ok_p = in_class_p (reg, goal_alt[i], &new_class);
4047
4048 if (new_class != NO_REGS && get_reg_class (regno) != new_class)
4049 {
4050 lra_assert (ok_p);
4051 lra_change_class (regno, new_class, " Change to", true);
4052 }
4053 }
4054 }
4055 else
4056 {
4057 const char *constraint;
4058 char c;
4059 rtx op = *curr_id->operand_loc[i];
4060 rtx subreg = NULL_RTX;
4061 machine_mode mode = curr_operand_mode[i];
4062
4063 if (GET_CODE (op) == SUBREG)
4064 {
4065 subreg = op;
4066 op = SUBREG_REG (op);
4067 mode = GET_MODE (op);
4068 }
4069
4070 if (CONST_POOL_OK_P (mode, op)
4071 && ((targetm.preferred_reload_class
4072 (op, (enum reg_class) goal_alt[i]) == NO_REGS)
4073 || no_input_reloads_p))
4074 {
4075 rtx tem = force_const_mem (mode, op);
4076
4077 change_p = true;
4078 if (subreg != NULL_RTX)
4079 tem = gen_rtx_SUBREG (mode, tem, SUBREG_BYTE (subreg));
4080
4081 *curr_id->operand_loc[i] = tem;
4082 lra_update_dup (curr_id, i);
4083 process_address (i, false, &before, &after);
4084
4085 /* If the alternative accepts constant pool refs directly
4086 there will be no reload needed at all. */
4087 if (subreg != NULL_RTX)
4088 continue;
4089 /* Skip alternatives before the one requested. */
4090 constraint = (curr_static_id->operand_alternative
4091 [goal_alt_number * n_operands + i].constraint);
4092 for (;
4093 (c = *constraint) && c != ',' && c != '#';
4094 constraint += CONSTRAINT_LEN (c, constraint))
4095 {
4096 enum constraint_num cn = lookup_constraint (constraint);
4097 if ((insn_extra_memory_constraint (cn)
4098 || insn_extra_special_memory_constraint (cn))
4099 && satisfies_memory_constraint_p (tem, cn))
4100 break;
4101 }
4102 if (c == '\0' || c == ',' || c == '#')
4103 continue;
4104
4105 goal_alt_win[i] = true;
4106 }
4107 }
4108
4109 n_outputs = 0;
4110 outputs[0] = -1;
4111 for (i = 0; i < n_operands; i++)
4112 {
4113 int regno;
4114 bool optional_p = false;
4115 rtx old, new_reg;
4116 rtx op = *curr_id->operand_loc[i];
4117
4118 if (goal_alt_win[i])
4119 {
4120 if (goal_alt[i] == NO_REGS
4121 && REG_P (op)
4122 /* When we assign NO_REGS it means that we will not
4123 assign a hard register to the scratch pseudo by
4124 assigment pass and the scratch pseudo will be
4125 spilled. Spilled scratch pseudos are transformed
4126 back to scratches at the LRA end. */
4127 && lra_former_scratch_operand_p (curr_insn, i)
4128 && lra_former_scratch_p (REGNO (op)))
4129 {
4130 int regno = REGNO (op);
4131 lra_change_class (regno, NO_REGS, " Change to", true);
4132 if (lra_get_regno_hard_regno (regno) >= 0)
4133 /* We don't have to mark all insn affected by the
4134 spilled pseudo as there is only one such insn, the
4135 current one. */
4136 reg_renumber[regno] = -1;
4137 lra_assert (bitmap_single_bit_set_p
4138 (&lra_reg_info[REGNO (op)].insn_bitmap));
4139 }
4140 /* We can do an optional reload. If the pseudo got a hard
4141 reg, we might improve the code through inheritance. If
4142 it does not get a hard register we coalesce memory/memory
4143 moves later. Ignore move insns to avoid cycling. */
4144 if (! lra_simple_p
4145 && lra_undo_inheritance_iter < LRA_MAX_INHERITANCE_PASSES
4146 && goal_alt[i] != NO_REGS && REG_P (op)
4147 && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER
4148 && regno < new_regno_start
4149 && ! lra_former_scratch_p (regno)
4150 && reg_renumber[regno] < 0
4151 /* Check that the optional reload pseudo will be able to
4152 hold given mode value. */
4153 && ! (prohibited_class_reg_set_mode_p
4154 (goal_alt[i], reg_class_contents[goal_alt[i]],
4155 PSEUDO_REGNO_MODE (regno)))
4156 && (curr_insn_set == NULL_RTX
4157 || !((REG_P (SET_SRC (curr_insn_set))
4158 || MEM_P (SET_SRC (curr_insn_set))
4159 || GET_CODE (SET_SRC (curr_insn_set)) == SUBREG)
4160 && (REG_P (SET_DEST (curr_insn_set))
4161 || MEM_P (SET_DEST (curr_insn_set))
4162 || GET_CODE (SET_DEST (curr_insn_set)) == SUBREG))))
4163 optional_p = true;
4164 else
4165 continue;
4166 }
4167
4168 /* Operands that match previous ones have already been handled. */
4169 if (goal_alt_matches[i] >= 0)
4170 continue;
4171
4172 /* We should not have an operand with a non-offsettable address
4173 appearing where an offsettable address will do. It also may
4174 be a case when the address should be special in other words
4175 not a general one (e.g. it needs no index reg). */
4176 if (goal_alt_matched[i][0] == -1 && goal_alt_offmemok[i] && MEM_P (op))
4177 {
4178 enum reg_class rclass;
4179 rtx *loc = &XEXP (op, 0);
4180 enum rtx_code code = GET_CODE (*loc);
4181
4182 push_to_sequence (before);
4183 rclass = base_reg_class (GET_MODE (op), MEM_ADDR_SPACE (op),
4184 MEM, SCRATCH);
4185 if (GET_RTX_CLASS (code) == RTX_AUTOINC)
4186 new_reg = emit_inc (rclass, *loc, *loc,
4187 /* This value does not matter for MODIFY. */
4188 GET_MODE_SIZE (GET_MODE (op)));
4189 else if (get_reload_reg (OP_IN, Pmode, *loc, rclass, FALSE,
4190 "offsetable address", &new_reg))
4191 lra_emit_move (new_reg, *loc);
4192 before = get_insns ();
4193 end_sequence ();
4194 *loc = new_reg;
4195 lra_update_dup (curr_id, i);
4196 }
4197 else if (goal_alt_matched[i][0] == -1)
4198 {
4199 machine_mode mode;
4200 rtx reg, *loc;
4201 int hard_regno, byte;
4202 enum op_type type = curr_static_id->operand[i].type;
4203
4204 loc = curr_id->operand_loc[i];
4205 mode = curr_operand_mode[i];
4206 if (GET_CODE (*loc) == SUBREG)
4207 {
4208 reg = SUBREG_REG (*loc);
4209 byte = SUBREG_BYTE (*loc);
4210 if (REG_P (reg)
4211 /* Strict_low_part requires reloading the register and not
4212 just the subreg. Likewise for a strict subreg no wider
4213 than a word for WORD_REGISTER_OPERATIONS targets. */
4214 && (curr_static_id->operand[i].strict_low
4215 || (!paradoxical_subreg_p (mode, GET_MODE (reg))
4216 && (hard_regno
4217 = get_try_hard_regno (REGNO (reg))) >= 0
4218 && (simplify_subreg_regno
4219 (hard_regno,
4220 GET_MODE (reg), byte, mode) < 0)
4221 && (goal_alt[i] == NO_REGS
4222 || (simplify_subreg_regno
4223 (ira_class_hard_regs[goal_alt[i]][0],
4224 GET_MODE (reg), byte, mode) >= 0)))
4225 || (GET_MODE_PRECISION (mode)
4226 < GET_MODE_PRECISION (GET_MODE (reg))
4227 && GET_MODE_SIZE (GET_MODE (reg)) <= UNITS_PER_WORD
4228 && WORD_REGISTER_OPERATIONS)))
4229 {
4230 /* An OP_INOUT is required when reloading a subreg of a
4231 mode wider than a word to ensure that data beyond the
4232 word being reloaded is preserved. Also automatically
4233 ensure that strict_low_part reloads are made into
4234 OP_INOUT which should already be true from the backend
4235 constraints. */
4236 if (type == OP_OUT
4237 && (curr_static_id->operand[i].strict_low
4238 || read_modify_subreg_p (*loc)))
4239 type = OP_INOUT;
4240 loc = &SUBREG_REG (*loc);
4241 mode = GET_MODE (*loc);
4242 }
4243 }
4244 old = *loc;
4245 if (get_reload_reg (type, mode, old, goal_alt[i],
4246 loc != curr_id->operand_loc[i], "", &new_reg)
4247 && type != OP_OUT)
4248 {
4249 push_to_sequence (before);
4250 lra_emit_move (new_reg, old);
4251 before = get_insns ();
4252 end_sequence ();
4253 }
4254 *loc = new_reg;
4255 if (type != OP_IN
4256 && find_reg_note (curr_insn, REG_UNUSED, old) == NULL_RTX)
4257 {
4258 start_sequence ();
4259 lra_emit_move (type == OP_INOUT ? copy_rtx (old) : old, new_reg);
4260 emit_insn (after);
4261 after = get_insns ();
4262 end_sequence ();
4263 *loc = new_reg;
4264 }
4265 for (j = 0; j < goal_alt_dont_inherit_ops_num; j++)
4266 if (goal_alt_dont_inherit_ops[j] == i)
4267 {
4268 lra_set_regno_unique_value (REGNO (new_reg));
4269 break;
4270 }
4271 lra_update_dup (curr_id, i);
4272 }
4273 else if (curr_static_id->operand[i].type == OP_IN
4274 && (curr_static_id->operand[goal_alt_matched[i][0]].type
4275 == OP_OUT
4276 || (curr_static_id->operand[goal_alt_matched[i][0]].type
4277 == OP_INOUT
4278 && (operands_match_p
4279 (*curr_id->operand_loc[i],
4280 *curr_id->operand_loc[goal_alt_matched[i][0]],
4281 -1)))))
4282 {
4283 /* generate reloads for input and matched outputs. */
4284 match_inputs[0] = i;
4285 match_inputs[1] = -1;
4286 match_reload (goal_alt_matched[i][0], match_inputs, outputs,
4287 goal_alt[i], &before, &after,
4288 curr_static_id->operand_alternative
4289 [goal_alt_number * n_operands + goal_alt_matched[i][0]]
4290 .earlyclobber);
4291 }
4292 else if ((curr_static_id->operand[i].type == OP_OUT
4293 || (curr_static_id->operand[i].type == OP_INOUT
4294 && (operands_match_p
4295 (*curr_id->operand_loc[i],
4296 *curr_id->operand_loc[goal_alt_matched[i][0]],
4297 -1))))
4298 && (curr_static_id->operand[goal_alt_matched[i][0]].type
4299 == OP_IN))
4300 /* Generate reloads for output and matched inputs. */
4301 match_reload (i, goal_alt_matched[i], outputs, goal_alt[i], &before,
4302 &after, curr_static_id->operand_alternative
4303 [goal_alt_number * n_operands + i].earlyclobber);
4304 else if (curr_static_id->operand[i].type == OP_IN
4305 && (curr_static_id->operand[goal_alt_matched[i][0]].type
4306 == OP_IN))
4307 {
4308 /* Generate reloads for matched inputs. */
4309 match_inputs[0] = i;
4310 for (j = 0; (k = goal_alt_matched[i][j]) >= 0; j++)
4311 match_inputs[j + 1] = k;
4312 match_inputs[j + 1] = -1;
4313 match_reload (-1, match_inputs, outputs, goal_alt[i], &before,
4314 &after, false);
4315 }
4316 else
4317 /* We must generate code in any case when function
4318 process_alt_operands decides that it is possible. */
4319 gcc_unreachable ();
4320
4321 /* Memorise processed outputs so that output remaining to be processed
4322 can avoid using the same register value (see match_reload). */
4323 if (curr_static_id->operand[i].type == OP_OUT)
4324 {
4325 outputs[n_outputs++] = i;
4326 outputs[n_outputs] = -1;
4327 }
4328
4329 if (optional_p)
4330 {
4331 rtx reg = op;
4332
4333 lra_assert (REG_P (reg));
4334 regno = REGNO (reg);
4335 op = *curr_id->operand_loc[i]; /* Substitution. */
4336 if (GET_CODE (op) == SUBREG)
4337 op = SUBREG_REG (op);
4338 gcc_assert (REG_P (op) && (int) REGNO (op) >= new_regno_start);
4339 bitmap_set_bit (&lra_optional_reload_pseudos, REGNO (op));
4340 lra_reg_info[REGNO (op)].restore_rtx = reg;
4341 if (lra_dump_file != NULL)
4342 fprintf (lra_dump_file,
4343 " Making reload reg %d for reg %d optional\n",
4344 REGNO (op), regno);
4345 }
4346 }
4347 if (before != NULL_RTX || after != NULL_RTX
4348 || max_regno_before != max_reg_num ())
4349 change_p = true;
4350 if (change_p)
4351 {
4352 lra_update_operator_dups (curr_id);
4353 /* Something changes -- process the insn. */
4354 lra_update_insn_regno_info (curr_insn);
4355 }
4356 lra_process_new_insns (curr_insn, before, after, "Inserting insn reload");
4357 return change_p;
4358}
4359
4360/* Return true if INSN satisfies all constraints. In other words, no
4361 reload insns are needed. */
4362bool
4363lra_constrain_insn (rtx_insn *insn)
4364{
4365 int saved_new_regno_start = new_regno_start;
4366 int saved_new_insn_uid_start = new_insn_uid_start;
4367 bool change_p;
4368
4369 curr_insn = insn;
4370 curr_id = lra_get_insn_recog_data (curr_insn);
4371 curr_static_id = curr_id->insn_static_data;
4372 new_insn_uid_start = get_max_uid ();
4373 new_regno_start = max_reg_num ();
4374 change_p = curr_insn_transform (true);
4375 new_regno_start = saved_new_regno_start;
4376 new_insn_uid_start = saved_new_insn_uid_start;
4377 return ! change_p;
4378}
4379
4380/* Return true if X is in LIST. */
4381static bool
4382in_list_p (rtx x, rtx list)
4383{
4384 for (; list != NULL_RTX; list = XEXP (list, 1))
4385 if (XEXP (list, 0) == x)
4386 return true;
4387 return false;
4388}
4389
4390/* Return true if X contains an allocatable hard register (if
4391 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
4392static bool
4393contains_reg_p (rtx x, bool hard_reg_p, bool spilled_p)
4394{
4395 int i, j;
4396 const char *fmt;
4397 enum rtx_code code;
4398
4399 code = GET_CODE (x);
4400 if (REG_P (x))
4401 {
4402 int regno = REGNO (x);
4403 HARD_REG_SET alloc_regs;
4404
4405 if (hard_reg_p)
4406 {
4407 if (regno >= FIRST_PSEUDO_REGISTER)
4408 regno = lra_get_regno_hard_regno (regno);
4409 if (regno < 0)
4410 return false;
4411 COMPL_HARD_REG_SET (alloc_regs, lra_no_alloc_regs);
4412 return overlaps_hard_reg_set_p (alloc_regs, GET_MODE (x), regno);
4413 }
4414 else
4415 {
4416 if (regno < FIRST_PSEUDO_REGISTER)
4417 return false;
4418 if (! spilled_p)
4419 return true;
4420 return lra_get_regno_hard_regno (regno) < 0;
4421 }
4422 }
4423 fmt = GET_RTX_FORMAT (code);
4424 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4425 {
4426 if (fmt[i] == 'e')
4427 {
4428 if (contains_reg_p (XEXP (x, i), hard_reg_p, spilled_p))
4429 return true;
4430 }
4431 else if (fmt[i] == 'E')
4432 {
4433 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4434 if (contains_reg_p (XVECEXP (x, i, j), hard_reg_p, spilled_p))
4435 return true;
4436 }
4437 }
4438 return false;
4439}
4440
4441/* Process all regs in location *LOC and change them on equivalent
4442 substitution. Return true if any change was done. */
4443static bool
4444loc_equivalence_change_p (rtx *loc)
4445{
4446 rtx subst, reg, x = *loc;
4447 bool result = false;
4448 enum rtx_code code = GET_CODE (x);
4449 const char *fmt;
4450 int i, j;
4451
4452 if (code == SUBREG)
4453 {
4454 reg = SUBREG_REG (x);
4455 if ((subst = get_equiv_with_elimination (reg, curr_insn)) != reg
4456 && <