1/* Change pseudos by memory.
2 Copyright (C) 2010-2017 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
4
5This file is part of GCC.
6
7GCC is free software; you can redistribute it and/or modify it under
8the terms of the GNU General Public License as published by the Free
9Software Foundation; either version 3, or (at your option) any later
10version.
11
12GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13WARRANTY; without even the implied warranty of MERCHANTABILITY or
14FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15for more details.
16
17You should have received a copy of the GNU General Public License
18along with GCC; see the file COPYING3. If not see
19<http://www.gnu.org/licenses/>. */
20
21
22/* This file contains code for a pass to change spilled pseudos into
23 memory.
24
25 The pass creates necessary stack slots and assigns spilled pseudos
26 to the stack slots in following way:
27
28 for all spilled pseudos P most frequently used first do
29 for all stack slots S do
30 if P doesn't conflict with pseudos assigned to S then
31 assign S to P and goto to the next pseudo process
32 end
33 end
34 create new stack slot S and assign P to S
35 end
36
37 The actual algorithm is bit more complicated because of different
38 pseudo sizes.
39
40 After that the code changes spilled pseudos (except ones created
41 from scratches) by corresponding stack slot memory in RTL.
42
43 If at least one stack slot was created, we need to run more passes
44 because we have new addresses which should be checked and because
45 the old address displacements might change and address constraints
46 (or insn memory constraints) might not be satisfied any more.
47
48 For some targets, the pass can spill some pseudos into hard
49 registers of different class (usually into vector registers)
50 instead of spilling them into memory if it is possible and
51 profitable. Spilling GENERAL_REGS pseudo into SSE registers for
52 Intel Corei7 is an example of such optimization. And this is
53 actually recommended by Intel optimization guide.
54
55 The file also contains code for final change of pseudos on hard
56 regs correspondingly assigned to them. */
57
58#include "config.h"
59#include "system.h"
60#include "coretypes.h"
61#include "backend.h"
62#include "target.h"
63#include "rtl.h"
64#include "df.h"
65#include "insn-config.h"
66#include "regs.h"
67#include "memmodel.h"
68#include "ira.h"
69#include "recog.h"
70#include "output.h"
71#include "cfgrtl.h"
72#include "lra.h"
73#include "lra-int.h"
74
75
76/* Max regno at the start of the pass. */
77static int regs_num;
78
79/* Map spilled regno -> hard regno used instead of memory for
80 spilling. */
81static rtx *spill_hard_reg;
82
83/* The structure describes stack slot of a spilled pseudo. */
84struct pseudo_slot
85{
86 /* Number (0, 1, ...) of the stack slot to which given pseudo
87 belongs. */
88 int slot_num;
89 /* First or next slot with the same slot number. */
90 struct pseudo_slot *next, *first;
91 /* Memory representing the spilled pseudo. */
92 rtx mem;
93};
94
95/* The stack slots for each spilled pseudo. Indexed by regnos. */
96static struct pseudo_slot *pseudo_slots;
97
98/* The structure describes a register or a stack slot which can be
99 used for several spilled pseudos. */
100struct slot
101{
102 /* First pseudo with given stack slot. */
103 int regno;
104 /* Hard reg into which the slot pseudos are spilled. The value is
105 negative for pseudos spilled into memory. */
106 int hard_regno;
107 /* Maximum alignment required by all users of the slot. */
108 unsigned int align;
109 /* Maximum size required by all users of the slot. */
110 HOST_WIDE_INT size;
111 /* Memory representing the all stack slot. It can be different from
112 memory representing a pseudo belonging to give stack slot because
113 pseudo can be placed in a part of the corresponding stack slot.
114 The value is NULL for pseudos spilled into a hard reg. */
115 rtx mem;
116 /* Combined live ranges of all pseudos belonging to given slot. It
117 is used to figure out that a new spilled pseudo can use given
118 stack slot. */
119 lra_live_range_t live_ranges;
120};
121
122/* Array containing info about the stack slots. The array element is
123 indexed by the stack slot number in the range [0..slots_num). */
124static struct slot *slots;
125/* The number of the stack slots currently existing. */
126static int slots_num;
127
128/* Set up memory of the spilled pseudo I. The function can allocate
129 the corresponding stack slot if it is not done yet. */
130static void
131assign_mem_slot (int i)
132{
133 rtx x = NULL_RTX;
134 machine_mode mode = GET_MODE (regno_reg_rtx[i]);
135 HOST_WIDE_INT inherent_size = PSEUDO_REGNO_BYTES (i);
136 machine_mode wider_mode
137 = wider_subreg_mode (mode, lra_reg_info[i].biggest_mode);
138 HOST_WIDE_INT total_size = GET_MODE_SIZE (wider_mode);
139 HOST_WIDE_INT adjust = 0;
140
141 lra_assert (regno_reg_rtx[i] != NULL_RTX && REG_P (regno_reg_rtx[i])
142 && lra_reg_info[i].nrefs != 0 && reg_renumber[i] < 0);
143
144 unsigned int slot_num = pseudo_slots[i].slot_num;
145 x = slots[slot_num].mem;
146 if (!x)
147 {
148 x = assign_stack_local (BLKmode, slots[slot_num].size,
149 slots[slot_num].align);
150 slots[slot_num].mem = x;
151 }
152
153 /* On a big endian machine, the "address" of the slot is the address
154 of the low part that fits its inherent mode. */
155 adjust += subreg_size_lowpart_offset (inherent_size, total_size);
156 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
157
158 /* Set all of the memory attributes as appropriate for a spill. */
159 set_mem_attrs_for_spill (x);
160 pseudo_slots[i].mem = x;
161}
162
163/* Sort pseudos according their usage frequencies. */
164static int
165regno_freq_compare (const void *v1p, const void *v2p)
166{
167 const int regno1 = *(const int *) v1p;
168 const int regno2 = *(const int *) v2p;
169 int diff;
170
171 if ((diff = lra_reg_info[regno2].freq - lra_reg_info[regno1].freq) != 0)
172 return diff;
173 return regno1 - regno2;
174}
175
176/* Sort pseudos according to their slots, putting the slots in the order
177 that they should be allocated. Slots with lower numbers have the highest
178 priority and should get the smallest displacement from the stack or
179 frame pointer (whichever is being used).
180
181 The first allocated slot is always closest to the frame pointer,
182 so prefer lower slot numbers when frame_pointer_needed. If the stack
183 and frame grow in the same direction, then the first allocated slot is
184 always closest to the initial stack pointer and furthest away from the
185 final stack pointer, so allocate higher numbers first when using the
186 stack pointer in that case. The reverse is true if the stack and
187 frame grow in opposite directions. */
188static int
189pseudo_reg_slot_compare (const void *v1p, const void *v2p)
190{
191 const int regno1 = *(const int *) v1p;
192 const int regno2 = *(const int *) v2p;
193 int diff, slot_num1, slot_num2;
194 int total_size1, total_size2;
195
196 slot_num1 = pseudo_slots[regno1].slot_num;
197 slot_num2 = pseudo_slots[regno2].slot_num;
198 if ((diff = slot_num1 - slot_num2) != 0)
199 return (frame_pointer_needed
200 || (!FRAME_GROWS_DOWNWARD) == STACK_GROWS_DOWNWARD ? diff : -diff);
201 total_size1 = GET_MODE_SIZE (lra_reg_info[regno1].biggest_mode);
202 total_size2 = GET_MODE_SIZE (lra_reg_info[regno2].biggest_mode);
203 if ((diff = total_size2 - total_size1) != 0)
204 return diff;
205 return regno1 - regno2;
206}
207
208/* Assign spill hard registers to N pseudos in PSEUDO_REGNOS which is
209 sorted in order of highest frequency first. Put the pseudos which
210 did not get a spill hard register at the beginning of array
211 PSEUDO_REGNOS. Return the number of such pseudos. */
212static int
213assign_spill_hard_regs (int *pseudo_regnos, int n)
214{
215 int i, k, p, regno, res, spill_class_size, hard_regno, nr;
216 enum reg_class rclass, spill_class;
217 machine_mode mode;
218 lra_live_range_t r;
219 rtx_insn *insn;
220 rtx set;
221 basic_block bb;
222 HARD_REG_SET conflict_hard_regs;
223 bitmap setjump_crosses = regstat_get_setjmp_crosses ();
224 /* Hard registers which can not be used for any purpose at given
225 program point because they are unallocatable or already allocated
226 for other pseudos. */
227 HARD_REG_SET *reserved_hard_regs;
228
229 if (! lra_reg_spill_p)
230 return n;
231 /* Set up reserved hard regs for every program point. */
232 reserved_hard_regs = XNEWVEC (HARD_REG_SET, lra_live_max_point);
233 for (p = 0; p < lra_live_max_point; p++)
234 COPY_HARD_REG_SET (reserved_hard_regs[p], lra_no_alloc_regs);
235 for (i = FIRST_PSEUDO_REGISTER; i < regs_num; i++)
236 if (lra_reg_info[i].nrefs != 0
237 && (hard_regno = lra_get_regno_hard_regno (i)) >= 0)
238 for (r = lra_reg_info[i].live_ranges; r != NULL; r = r->next)
239 for (p = r->start; p <= r->finish; p++)
240 add_to_hard_reg_set (&reserved_hard_regs[p],
241 lra_reg_info[i].biggest_mode, hard_regno);
242 auto_bitmap ok_insn_bitmap (&reg_obstack);
243 FOR_EACH_BB_FN (bb, cfun)
244 FOR_BB_INSNS (bb, insn)
245 if (DEBUG_INSN_P (insn)
246 || ((set = single_set (insn)) != NULL_RTX
247 && REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))))
248 bitmap_set_bit (ok_insn_bitmap, INSN_UID (insn));
249 for (res = i = 0; i < n; i++)
250 {
251 regno = pseudo_regnos[i];
252 rclass = lra_get_allocno_class (regno);
253 if (bitmap_bit_p (setjump_crosses, regno)
254 || (spill_class
255 = ((enum reg_class)
256 targetm.spill_class ((reg_class_t) rclass,
257 PSEUDO_REGNO_MODE (regno)))) == NO_REGS
258 || bitmap_intersect_compl_p (&lra_reg_info[regno].insn_bitmap,
259 ok_insn_bitmap))
260 {
261 pseudo_regnos[res++] = regno;
262 continue;
263 }
264 lra_assert (spill_class != NO_REGS);
265 COPY_HARD_REG_SET (conflict_hard_regs,
266 lra_reg_info[regno].conflict_hard_regs);
267 for (r = lra_reg_info[regno].live_ranges; r != NULL; r = r->next)
268 for (p = r->start; p <= r->finish; p++)
269 IOR_HARD_REG_SET (conflict_hard_regs, reserved_hard_regs[p]);
270 spill_class_size = ira_class_hard_regs_num[spill_class];
271 mode = lra_reg_info[regno].biggest_mode;
272 for (k = 0; k < spill_class_size; k++)
273 {
274 hard_regno = ira_class_hard_regs[spill_class][k];
275 if (! overlaps_hard_reg_set_p (conflict_hard_regs, mode, hard_regno))
276 break;
277 }
278 if (k >= spill_class_size)
279 {
280 /* There is no available regs -- assign memory later. */
281 pseudo_regnos[res++] = regno;
282 continue;
283 }
284 if (lra_dump_file != NULL)
285 fprintf (lra_dump_file, " Spill r%d into hr%d\n", regno, hard_regno);
286 /* Update reserved_hard_regs. */
287 for (r = lra_reg_info[regno].live_ranges; r != NULL; r = r->next)
288 for (p = r->start; p <= r->finish; p++)
289 add_to_hard_reg_set (&reserved_hard_regs[p],
290 lra_reg_info[regno].biggest_mode, hard_regno);
291 spill_hard_reg[regno]
292 = gen_raw_REG (PSEUDO_REGNO_MODE (regno), hard_regno);
293 for (nr = 0;
294 nr < hard_regno_nregs (hard_regno,
295 lra_reg_info[regno].biggest_mode);
296 nr++)
297 /* Just loop. */
298 df_set_regs_ever_live (hard_regno + nr, true);
299 }
300 free (reserved_hard_regs);
301 return res;
302}
303
304/* Add pseudo REGNO to slot SLOT_NUM. */
305static void
306add_pseudo_to_slot (int regno, int slot_num)
307{
308 struct pseudo_slot *first;
309
310 /* Each pseudo has an inherent size which comes from its own mode,
311 and a total size which provides room for paradoxical subregs.
312 We need to make sure the size and alignment of the slot are
313 sufficient for both. */
314 machine_mode mode = wider_subreg_mode (PSEUDO_REGNO_MODE (regno),
315 lra_reg_info[regno].biggest_mode);
316 unsigned int align = spill_slot_alignment (mode);
317 slots[slot_num].align = MAX (slots[slot_num].align, align);
318 slots[slot_num].size = MAX (slots[slot_num].size, GET_MODE_SIZE (mode));
319
320 if (slots[slot_num].regno < 0)
321 {
322 /* It is the first pseudo in the slot. */
323 slots[slot_num].regno = regno;
324 pseudo_slots[regno].first = &pseudo_slots[regno];
325 pseudo_slots[regno].next = NULL;
326 }
327 else
328 {
329 first = pseudo_slots[regno].first = &pseudo_slots[slots[slot_num].regno];
330 pseudo_slots[regno].next = first->next;
331 first->next = &pseudo_slots[regno];
332 }
333 pseudo_slots[regno].mem = NULL_RTX;
334 pseudo_slots[regno].slot_num = slot_num;
335 slots[slot_num].live_ranges
336 = lra_merge_live_ranges (slots[slot_num].live_ranges,
337 lra_copy_live_range_list
338 (lra_reg_info[regno].live_ranges));
339}
340
341/* Assign stack slot numbers to pseudos in array PSEUDO_REGNOS of
342 length N. Sort pseudos in PSEUDO_REGNOS for subsequent assigning
343 memory stack slots. */
344static void
345assign_stack_slot_num_and_sort_pseudos (int *pseudo_regnos, int n)
346{
347 int i, j, regno;
348
349 slots_num = 0;
350 /* Assign stack slot numbers to spilled pseudos, use smaller numbers
351 for most frequently used pseudos. */
352 for (i = 0; i < n; i++)
353 {
354 regno = pseudo_regnos[i];
355 if (! flag_ira_share_spill_slots)
356 j = slots_num;
357 else
358 {
359 for (j = 0; j < slots_num; j++)
360 if (slots[j].hard_regno < 0
361 && ! (lra_intersected_live_ranges_p
362 (slots[j].live_ranges,
363 lra_reg_info[regno].live_ranges)))
364 break;
365 }
366 if (j >= slots_num)
367 {
368 /* New slot. */
369 slots[j].live_ranges = NULL;
370 slots[j].size = 0;
371 slots[j].align = BITS_PER_UNIT;
372 slots[j].regno = slots[j].hard_regno = -1;
373 slots[j].mem = NULL_RTX;
374 slots_num++;
375 }
376 add_pseudo_to_slot (regno, j);
377 }
378 /* Sort regnos according to their slot numbers. */
379 qsort (pseudo_regnos, n, sizeof (int), pseudo_reg_slot_compare);
380}
381
382/* Recursively process LOC in INSN and change spilled pseudos to the
383 corresponding memory or spilled hard reg. Ignore spilled pseudos
384 created from the scratches. Return true if the pseudo nrefs equal
385 to 0 (don't change the pseudo in this case). Otherwise return false. */
386static bool
387remove_pseudos (rtx *loc, rtx_insn *insn)
388{
389 int i;
390 rtx hard_reg;
391 const char *fmt;
392 enum rtx_code code;
393 bool res = false;
394
395 if (*loc == NULL_RTX)
396 return res;
397 code = GET_CODE (*loc);
398 if (code == REG && (i = REGNO (*loc)) >= FIRST_PSEUDO_REGISTER
399 && lra_get_regno_hard_regno (i) < 0
400 /* We do not want to assign memory for former scratches because
401 it might result in an address reload for some targets. In
402 any case we transform such pseudos not getting hard registers
403 into scratches back. */
404 && ! lra_former_scratch_p (i))
405 {
406 if (lra_reg_info[i].nrefs == 0
407 && pseudo_slots[i].mem == NULL && spill_hard_reg[i] == NULL)
408 return true;
409 if ((hard_reg = spill_hard_reg[i]) != NULL_RTX)
410 *loc = copy_rtx (hard_reg);
411 else
412 {
413 rtx x = lra_eliminate_regs_1 (insn, pseudo_slots[i].mem,
414 GET_MODE (pseudo_slots[i].mem),
415 false, false, 0, true);
416 *loc = x != pseudo_slots[i].mem ? x : copy_rtx (x);
417 }
418 return res;
419 }
420
421 fmt = GET_RTX_FORMAT (code);
422 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
423 {
424 if (fmt[i] == 'e')
425 res = remove_pseudos (&XEXP (*loc, i), insn) || res;
426 else if (fmt[i] == 'E')
427 {
428 int j;
429
430 for (j = XVECLEN (*loc, i) - 1; j >= 0; j--)
431 res = remove_pseudos (&XVECEXP (*loc, i, j), insn) || res;
432 }
433 }
434 return res;
435}
436
437/* Convert spilled pseudos into their stack slots or spill hard regs,
438 put insns to process on the constraint stack (that is all insns in
439 which pseudos were changed to memory or spill hard regs). */
440static void
441spill_pseudos (void)
442{
443 basic_block bb;
444 rtx_insn *insn, *curr;
445 int i;
446
447 auto_bitmap spilled_pseudos (&reg_obstack);
448 auto_bitmap changed_insns (&reg_obstack);
449 for (i = FIRST_PSEUDO_REGISTER; i < regs_num; i++)
450 {
451 if (lra_reg_info[i].nrefs != 0 && lra_get_regno_hard_regno (i) < 0
452 && ! lra_former_scratch_p (i))
453 {
454 bitmap_set_bit (spilled_pseudos, i);
455 bitmap_ior_into (changed_insns, &lra_reg_info[i].insn_bitmap);
456 }
457 }
458 FOR_EACH_BB_FN (bb, cfun)
459 {
460 FOR_BB_INSNS_SAFE (bb, insn, curr)
461 {
462 bool removed_pseudo_p = false;
463
464 if (bitmap_bit_p (changed_insns, INSN_UID (insn)))
465 {
466 rtx *link_loc, link;
467
468 removed_pseudo_p = remove_pseudos (&PATTERN (insn), insn);
469 if (CALL_P (insn)
470 && remove_pseudos (&CALL_INSN_FUNCTION_USAGE (insn), insn))
471 removed_pseudo_p = true;
472 for (link_loc = &REG_NOTES (insn);
473 (link = *link_loc) != NULL_RTX;
474 link_loc = &XEXP (link, 1))
475 {
476 switch (REG_NOTE_KIND (link))
477 {
478 case REG_FRAME_RELATED_EXPR:
479 case REG_CFA_DEF_CFA:
480 case REG_CFA_ADJUST_CFA:
481 case REG_CFA_OFFSET:
482 case REG_CFA_REGISTER:
483 case REG_CFA_EXPRESSION:
484 case REG_CFA_RESTORE:
485 case REG_CFA_SET_VDRAP:
486 if (remove_pseudos (&XEXP (link, 0), insn))
487 removed_pseudo_p = true;
488 break;
489 default:
490 break;
491 }
492 }
493 if (lra_dump_file != NULL)
494 fprintf (lra_dump_file,
495 "Changing spilled pseudos to memory in insn #%u\n",
496 INSN_UID (insn));
497 lra_push_insn (insn);
498 if (lra_reg_spill_p || targetm.different_addr_displacement_p ())
499 lra_set_used_insn_alternative (insn, -1);
500 }
501 else if (CALL_P (insn)
502 /* Presence of any pseudo in CALL_INSN_FUNCTION_USAGE
503 does not affect value of insn_bitmap of the
504 corresponding lra_reg_info. That is because we
505 don't need to reload pseudos in
506 CALL_INSN_FUNCTION_USAGEs. So if we process only
507 insns in the insn_bitmap of given pseudo here, we
508 can miss the pseudo in some
509 CALL_INSN_FUNCTION_USAGEs. */
510 && remove_pseudos (&CALL_INSN_FUNCTION_USAGE (insn), insn))
511 removed_pseudo_p = true;
512 if (removed_pseudo_p)
513 {
514 lra_assert (DEBUG_INSN_P (insn));
515 lra_invalidate_insn_data (insn);
516 INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
517 if (lra_dump_file != NULL)
518 fprintf (lra_dump_file,
519 "Debug insn #%u is reset because it referenced "
520 "removed pseudo\n", INSN_UID (insn));
521 }
522 bitmap_and_compl_into (df_get_live_in (bb), spilled_pseudos);
523 bitmap_and_compl_into (df_get_live_out (bb), spilled_pseudos);
524 }
525 }
526}
527
528/* Return true if we need to change some pseudos into memory. */
529bool
530lra_need_for_spills_p (void)
531{
532 int i; max_regno = max_reg_num ();
533
534 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
535 if (lra_reg_info[i].nrefs != 0 && lra_get_regno_hard_regno (i) < 0
536 && ! lra_former_scratch_p (i))
537 return true;
538 return false;
539}
540
541/* Change spilled pseudos into memory or spill hard regs. Put changed
542 insns on the constraint stack (these insns will be considered on
543 the next constraint pass). The changed insns are all insns in
544 which pseudos were changed. */
545void
546lra_spill (void)
547{
548 int i, n, curr_regno;
549 int *pseudo_regnos;
550
551 regs_num = max_reg_num ();
552 spill_hard_reg = XNEWVEC (rtx, regs_num);
553 pseudo_regnos = XNEWVEC (int, regs_num);
554 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < regs_num; i++)
555 if (lra_reg_info[i].nrefs != 0 && lra_get_regno_hard_regno (i) < 0
556 /* We do not want to assign memory for former scratches. */
557 && ! lra_former_scratch_p (i))
558 pseudo_regnos[n++] = i;
559 lra_assert (n > 0);
560 pseudo_slots = XNEWVEC (struct pseudo_slot, regs_num);
561 for (i = FIRST_PSEUDO_REGISTER; i < regs_num; i++)
562 {
563 spill_hard_reg[i] = NULL_RTX;
564 pseudo_slots[i].mem = NULL_RTX;
565 }
566 slots = XNEWVEC (struct slot, regs_num);
567 /* Sort regnos according their usage frequencies. */
568 qsort (pseudo_regnos, n, sizeof (int), regno_freq_compare);
569 n = assign_spill_hard_regs (pseudo_regnos, n);
570 assign_stack_slot_num_and_sort_pseudos (pseudo_regnos, n);
571 for (i = 0; i < n; i++)
572 if (pseudo_slots[pseudo_regnos[i]].mem == NULL_RTX)
573 assign_mem_slot (pseudo_regnos[i]);
574 if (n > 0 && crtl->stack_alignment_needed)
575 /* If we have a stack frame, we must align it now. The stack size
576 may be a part of the offset computation for register
577 elimination. */
578 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
579 if (lra_dump_file != NULL)
580 {
581 for (i = 0; i < slots_num; i++)
582 {
583 fprintf (lra_dump_file, " Slot %d regnos (width = %d):", i,
584 GET_MODE_SIZE (GET_MODE (slots[i].mem)));
585 for (curr_regno = slots[i].regno;;
586 curr_regno = pseudo_slots[curr_regno].next - pseudo_slots)
587 {
588 fprintf (lra_dump_file, " %d", curr_regno);
589 if (pseudo_slots[curr_regno].next == NULL)
590 break;
591 }
592 fprintf (lra_dump_file, "\n");
593 }
594 }
595 spill_pseudos ();
596 free (slots);
597 free (pseudo_slots);
598 free (pseudo_regnos);
599 free (spill_hard_reg);
600}
601
602/* Apply alter_subreg for subregs of regs in *LOC. Use FINAL_P for
603 alter_subreg calls. Return true if any subreg of reg is
604 processed. */
605static bool
606alter_subregs (rtx *loc, bool final_p)
607{
608 int i;
609 rtx x = *loc;
610 bool res;
611 const char *fmt;
612 enum rtx_code code;
613
614 if (x == NULL_RTX)
615 return false;
616 code = GET_CODE (x);
617 if (code == SUBREG && REG_P (SUBREG_REG (x)))
618 {
619 lra_assert (REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER);
620 alter_subreg (loc, final_p);
621 return true;
622 }
623 fmt = GET_RTX_FORMAT (code);
624 res = false;
625 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
626 {
627 if (fmt[i] == 'e')
628 {
629 if (alter_subregs (&XEXP (x, i), final_p))
630 res = true;
631 }
632 else if (fmt[i] == 'E')
633 {
634 int j;
635
636 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
637 if (alter_subregs (&XVECEXP (x, i, j), final_p))
638 res = true;
639 }
640 }
641 return res;
642}
643
644/* Return true if REGNO is used for return in the current
645 function. */
646static bool
647return_regno_p (unsigned int regno)
648{
649 rtx outgoing = crtl->return_rtx;
650
651 if (! outgoing)
652 return false;
653
654 if (REG_P (outgoing))
655 return REGNO (outgoing) == regno;
656 else if (GET_CODE (outgoing) == PARALLEL)
657 {
658 int i;
659
660 for (i = 0; i < XVECLEN (outgoing, 0); i++)
661 {
662 rtx x = XEXP (XVECEXP (outgoing, 0, i), 0);
663
664 if (REG_P (x) && REGNO (x) == regno)
665 return true;
666 }
667 }
668 return false;
669}
670
671/* Return true if REGNO is in one of subsequent USE after INSN in the
672 same BB. */
673static bool
674regno_in_use_p (rtx_insn *insn, unsigned int regno)
675{
676 static lra_insn_recog_data_t id;
677 static struct lra_static_insn_data *static_id;
678 struct lra_insn_reg *reg;
679 int i, arg_regno;
680 basic_block bb = BLOCK_FOR_INSN (insn);
681
682 while ((insn = next_nondebug_insn (insn)) != NULL_RTX)
683 {
684 if (BARRIER_P (insn) || bb != BLOCK_FOR_INSN (insn))
685 return false;
686 if (! INSN_P (insn))
687 continue;
688 if (GET_CODE (PATTERN (insn)) == USE
689 && REG_P (XEXP (PATTERN (insn), 0))
690 && regno == REGNO (XEXP (PATTERN (insn), 0)))
691 return true;
692 /* Check that the regno is not modified. */
693 id = lra_get_insn_recog_data (insn);
694 for (reg = id->regs; reg != NULL; reg = reg->next)
695 if (reg->type != OP_IN && reg->regno == (int) regno)
696 return false;
697 static_id = id->insn_static_data;
698 for (reg = static_id->hard_regs; reg != NULL; reg = reg->next)
699 if (reg->type != OP_IN && reg->regno == (int) regno)
700 return false;
701 if (id->arg_hard_regs != NULL)
702 for (i = 0; (arg_regno = id->arg_hard_regs[i]) >= 0; i++)
703 if ((int) regno == (arg_regno >= FIRST_PSEUDO_REGISTER
704 ? arg_regno : arg_regno - FIRST_PSEUDO_REGISTER))
705 return false;
706 }
707 return false;
708}
709
710/* Final change of pseudos got hard registers into the corresponding
711 hard registers and removing temporary clobbers. */
712void
713lra_final_code_change (void)
714{
715 int i, hard_regno;
716 basic_block bb;
717 rtx_insn *insn, *curr;
718 int max_regno = max_reg_num ();
719
720 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
721 if (lra_reg_info[i].nrefs != 0
722 && (hard_regno = lra_get_regno_hard_regno (i)) >= 0)
723 SET_REGNO (regno_reg_rtx[i], hard_regno);
724 FOR_EACH_BB_FN (bb, cfun)
725 FOR_BB_INSNS_SAFE (bb, insn, curr)
726 if (INSN_P (insn))
727 {
728 rtx pat = PATTERN (insn);
729
730 if (GET_CODE (pat) == CLOBBER && LRA_TEMP_CLOBBER_P (pat))
731 {
732 /* Remove clobbers temporarily created in LRA. We don't
733 need them anymore and don't want to waste compiler
734 time processing them in a few subsequent passes. */
735 lra_invalidate_insn_data (insn);
736 delete_insn (insn);
737 continue;
738 }
739
740 /* IRA can generate move insns involving pseudos. It is
741 better remove them earlier to speed up compiler a bit.
742 It is also better to do it here as they might not pass
743 final RTL check in LRA, (e.g. insn moving a control
744 register into itself). So remove an useless move insn
745 unless next insn is USE marking the return reg (we should
746 save this as some subsequent optimizations assume that
747 such original insns are saved). */
748 if (NONJUMP_INSN_P (insn) && GET_CODE (pat) == SET
749 && REG_P (SET_SRC (pat)) && REG_P (SET_DEST (pat))
750 && REGNO (SET_SRC (pat)) == REGNO (SET_DEST (pat))
751 && (! return_regno_p (REGNO (SET_SRC (pat)))
752 || ! regno_in_use_p (insn, REGNO (SET_SRC (pat)))))
753 {
754 lra_invalidate_insn_data (insn);
755 delete_insn (insn);
756 continue;
757 }
758
759 lra_insn_recog_data_t id = lra_get_insn_recog_data (insn);
760 struct lra_insn_reg *reg;
761
762 for (reg = id->regs; reg != NULL; reg = reg->next)
763 if (reg->regno >= FIRST_PSEUDO_REGISTER
764 && lra_reg_info [reg->regno].nrefs == 0)
765 break;
766
767 if (reg != NULL)
768 {
769 /* Pseudos still can be in debug insns in some very rare
770 and complicated cases, e.g. the pseudo was removed by
771 inheritance and the debug insn is not EBBs where the
772 inheritance happened. It is difficult and time
773 consuming to find what hard register corresponds the
774 pseudo -- so just remove the debug insn. Another
775 solution could be assigning hard reg/memory but it
776 would be a misleading info. It is better not to have
777 info than have it wrong. */
778 lra_assert (DEBUG_INSN_P (insn));
779 lra_invalidate_insn_data (insn);
780 delete_insn (insn);
781 continue;
782 }
783
784 struct lra_static_insn_data *static_id = id->insn_static_data;
785 bool insn_change_p = false;
786
787 for (i = id->insn_static_data->n_operands - 1; i >= 0; i--)
788 if ((DEBUG_INSN_P (insn) || ! static_id->operand[i].is_operator)
789 && alter_subregs (id->operand_loc[i], ! DEBUG_INSN_P (insn)))
790 {
791 lra_update_dup (id, i);
792 insn_change_p = true;
793 }
794 if (insn_change_p)
795 lra_update_operator_dups (id);
796 }
797}
798