1/* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987-2017 Free Software Foundation, Inc.
3
4This file is part of GCC.
5
6GCC is free software; you can redistribute it and/or modify it under
7the terms of the GNU General Public License as published by the Free
8Software Foundation; either version 3, or (at your option) any later
9version.
10
11GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12WARRANTY; without even the implied warranty of MERCHANTABILITY or
13FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14for more details.
15
16You should have received a copy of the GNU General Public License
17along with GCC; see the file COPYING3. If not see
18<http://www.gnu.org/licenses/>. */
19
20
21#include "config.h"
22#include "system.h"
23#include "coretypes.h"
24#include "backend.h"
25#include "target.h"
26#include "rtl.h"
27#include "tree.h"
28#include "cfghooks.h"
29#include "df.h"
30#include "memmodel.h"
31#include "tm_p.h"
32#include "insn-config.h"
33#include "regs.h"
34#include "emit-rtl.h"
35#include "recog.h"
36#include "insn-attr.h"
37#include "addresses.h"
38#include "cfgrtl.h"
39#include "cfgbuild.h"
40#include "cfgcleanup.h"
41#include "reload.h"
42#include "tree-pass.h"
43
44#ifndef STACK_POP_CODE
45#if STACK_GROWS_DOWNWARD
46#define STACK_POP_CODE POST_INC
47#else
48#define STACK_POP_CODE POST_DEC
49#endif
50#endif
51
52static void validate_replace_rtx_1 (rtx *, rtx, rtx, rtx_insn *, bool);
53static void validate_replace_src_1 (rtx *, void *);
54static rtx_insn *split_insn (rtx_insn *);
55
56struct target_recog default_target_recog;
57#if SWITCHABLE_TARGET
58struct target_recog *this_target_recog = &default_target_recog;
59#endif
60
61/* Nonzero means allow operands to be volatile.
62 This should be 0 if you are generating rtl, such as if you are calling
63 the functions in optabs.c and expmed.c (most of the time).
64 This should be 1 if all valid insns need to be recognized,
65 such as in reginfo.c and final.c and reload.c.
66
67 init_recog and init_recog_no_volatile are responsible for setting this. */
68
69int volatile_ok;
70
71struct recog_data_d recog_data;
72
73/* Contains a vector of operand_alternative structures, such that
74 operand OP of alternative A is at index A * n_operands + OP.
75 Set up by preprocess_constraints. */
76const operand_alternative *recog_op_alt;
77
78/* Used to provide recog_op_alt for asms. */
79static operand_alternative asm_op_alt[MAX_RECOG_OPERANDS
80 * MAX_RECOG_ALTERNATIVES];
81
82/* On return from `constrain_operands', indicate which alternative
83 was satisfied. */
84
85int which_alternative;
86
87/* Nonzero after end of reload pass.
88 Set to 1 or 0 by toplev.c.
89 Controls the significance of (SUBREG (MEM)). */
90
91int reload_completed;
92
93/* Nonzero after thread_prologue_and_epilogue_insns has run. */
94int epilogue_completed;
95
96/* Initialize data used by the function `recog'.
97 This must be called once in the compilation of a function
98 before any insn recognition may be done in the function. */
99
100void
101init_recog_no_volatile (void)
102{
103 volatile_ok = 0;
104}
105
106void
107init_recog (void)
108{
109 volatile_ok = 1;
110}
111
112
113/* Return true if labels in asm operands BODY are LABEL_REFs. */
114
115static bool
116asm_labels_ok (rtx body)
117{
118 rtx asmop;
119 int i;
120
121 asmop = extract_asm_operands (body);
122 if (asmop == NULL_RTX)
123 return true;
124
125 for (i = 0; i < ASM_OPERANDS_LABEL_LENGTH (asmop); i++)
126 if (GET_CODE (ASM_OPERANDS_LABEL (asmop, i)) != LABEL_REF)
127 return false;
128
129 return true;
130}
131
132/* Check that X is an insn-body for an `asm' with operands
133 and that the operands mentioned in it are legitimate. */
134
135int
136check_asm_operands (rtx x)
137{
138 int noperands;
139 rtx *operands;
140 const char **constraints;
141 int i;
142
143 if (!asm_labels_ok (x))
144 return 0;
145
146 /* Post-reload, be more strict with things. */
147 if (reload_completed)
148 {
149 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
150 rtx_insn *insn = make_insn_raw (x);
151 extract_insn (insn);
152 constrain_operands (1, get_enabled_alternatives (insn));
153 return which_alternative >= 0;
154 }
155
156 noperands = asm_noperands (x);
157 if (noperands < 0)
158 return 0;
159 if (noperands == 0)
160 return 1;
161
162 operands = XALLOCAVEC (rtx, noperands);
163 constraints = XALLOCAVEC (const char *, noperands);
164
165 decode_asm_operands (x, operands, NULL, constraints, NULL, NULL);
166
167 for (i = 0; i < noperands; i++)
168 {
169 const char *c = constraints[i];
170 if (c[0] == '%')
171 c++;
172 if (! asm_operand_ok (operands[i], c, constraints))
173 return 0;
174 }
175
176 return 1;
177}
178
179/* Static data for the next two routines. */
180
181struct change_t
182{
183 rtx object;
184 int old_code;
185 bool unshare;
186 rtx *loc;
187 rtx old;
188};
189
190static change_t *changes;
191static int changes_allocated;
192
193static int num_changes = 0;
194
195/* Validate a proposed change to OBJECT. LOC is the location in the rtl
196 at which NEW_RTX will be placed. If OBJECT is zero, no validation is done,
197 the change is simply made.
198
199 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
200 will be called with the address and mode as parameters. If OBJECT is
201 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
202 the change in place.
203
204 IN_GROUP is nonzero if this is part of a group of changes that must be
205 performed as a group. In that case, the changes will be stored. The
206 function `apply_change_group' will validate and apply the changes.
207
208 If IN_GROUP is zero, this is a single change. Try to recognize the insn
209 or validate the memory reference with the change applied. If the result
210 is not valid for the machine, suppress the change and return zero.
211 Otherwise, perform the change and return 1. */
212
213static bool
214validate_change_1 (rtx object, rtx *loc, rtx new_rtx, bool in_group, bool unshare)
215{
216 rtx old = *loc;
217
218 if (old == new_rtx || rtx_equal_p (old, new_rtx))
219 return 1;
220
221 gcc_assert (in_group != 0 || num_changes == 0);
222
223 *loc = new_rtx;
224
225 /* Save the information describing this change. */
226 if (num_changes >= changes_allocated)
227 {
228 if (changes_allocated == 0)
229 /* This value allows for repeated substitutions inside complex
230 indexed addresses, or changes in up to 5 insns. */
231 changes_allocated = MAX_RECOG_OPERANDS * 5;
232 else
233 changes_allocated *= 2;
234
235 changes = XRESIZEVEC (change_t, changes, changes_allocated);
236 }
237
238 changes[num_changes].object = object;
239 changes[num_changes].loc = loc;
240 changes[num_changes].old = old;
241 changes[num_changes].unshare = unshare;
242
243 if (object && !MEM_P (object))
244 {
245 /* Set INSN_CODE to force rerecognition of insn. Save old code in
246 case invalid. */
247 changes[num_changes].old_code = INSN_CODE (object);
248 INSN_CODE (object) = -1;
249 }
250
251 num_changes++;
252
253 /* If we are making a group of changes, return 1. Otherwise, validate the
254 change group we made. */
255
256 if (in_group)
257 return 1;
258 else
259 return apply_change_group ();
260}
261
262/* Wrapper for validate_change_1 without the UNSHARE argument defaulting
263 UNSHARE to false. */
264
265bool
266validate_change (rtx object, rtx *loc, rtx new_rtx, bool in_group)
267{
268 return validate_change_1 (object, loc, new_rtx, in_group, false);
269}
270
271/* Wrapper for validate_change_1 without the UNSHARE argument defaulting
272 UNSHARE to true. */
273
274bool
275validate_unshare_change (rtx object, rtx *loc, rtx new_rtx, bool in_group)
276{
277 return validate_change_1 (object, loc, new_rtx, in_group, true);
278}
279
280
281/* Keep X canonicalized if some changes have made it non-canonical; only
282 modifies the operands of X, not (for example) its code. Simplifications
283 are not the job of this routine.
284
285 Return true if anything was changed. */
286bool
287canonicalize_change_group (rtx_insn *insn, rtx x)
288{
289 if (COMMUTATIVE_P (x)
290 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
291 {
292 /* Oops, the caller has made X no longer canonical.
293 Let's redo the changes in the correct order. */
294 rtx tem = XEXP (x, 0);
295 validate_unshare_change (insn, &XEXP (x, 0), XEXP (x, 1), 1);
296 validate_unshare_change (insn, &XEXP (x, 1), tem, 1);
297 return true;
298 }
299 else
300 return false;
301}
302
303
304/* This subroutine of apply_change_group verifies whether the changes to INSN
305 were valid; i.e. whether INSN can still be recognized.
306
307 If IN_GROUP is true clobbers which have to be added in order to
308 match the instructions will be added to the current change group.
309 Otherwise the changes will take effect immediately. */
310
311int
312insn_invalid_p (rtx_insn *insn, bool in_group)
313{
314 rtx pat = PATTERN (insn);
315 int num_clobbers = 0;
316 /* If we are before reload and the pattern is a SET, see if we can add
317 clobbers. */
318 int icode = recog (pat, insn,
319 (GET_CODE (pat) == SET
320 && ! reload_completed
321 && ! reload_in_progress)
322 ? &num_clobbers : 0);
323 int is_asm = icode < 0 && asm_noperands (PATTERN (insn)) >= 0;
324
325
326 /* If this is an asm and the operand aren't legal, then fail. Likewise if
327 this is not an asm and the insn wasn't recognized. */
328 if ((is_asm && ! check_asm_operands (PATTERN (insn)))
329 || (!is_asm && icode < 0))
330 return 1;
331
332 /* If we have to add CLOBBERs, fail if we have to add ones that reference
333 hard registers since our callers can't know if they are live or not.
334 Otherwise, add them. */
335 if (num_clobbers > 0)
336 {
337 rtx newpat;
338
339 if (added_clobbers_hard_reg_p (icode))
340 return 1;
341
342 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_clobbers + 1));
343 XVECEXP (newpat, 0, 0) = pat;
344 add_clobbers (newpat, icode);
345 if (in_group)
346 validate_change (insn, &PATTERN (insn), newpat, 1);
347 else
348 PATTERN (insn) = pat = newpat;
349 }
350
351 /* After reload, verify that all constraints are satisfied. */
352 if (reload_completed)
353 {
354 extract_insn (insn);
355
356 if (! constrain_operands (1, get_preferred_alternatives (insn)))
357 return 1;
358 }
359
360 INSN_CODE (insn) = icode;
361 return 0;
362}
363
364/* Return number of changes made and not validated yet. */
365int
366num_changes_pending (void)
367{
368 return num_changes;
369}
370
371/* Tentatively apply the changes numbered NUM and up.
372 Return 1 if all changes are valid, zero otherwise. */
373
374int
375verify_changes (int num)
376{
377 int i;
378 rtx last_validated = NULL_RTX;
379
380 /* The changes have been applied and all INSN_CODEs have been reset to force
381 rerecognition.
382
383 The changes are valid if we aren't given an object, or if we are
384 given a MEM and it still is a valid address, or if this is in insn
385 and it is recognized. In the latter case, if reload has completed,
386 we also require that the operands meet the constraints for
387 the insn. */
388
389 for (i = num; i < num_changes; i++)
390 {
391 rtx object = changes[i].object;
392
393 /* If there is no object to test or if it is the same as the one we
394 already tested, ignore it. */
395 if (object == 0 || object == last_validated)
396 continue;
397
398 if (MEM_P (object))
399 {
400 if (! memory_address_addr_space_p (GET_MODE (object),
401 XEXP (object, 0),
402 MEM_ADDR_SPACE (object)))
403 break;
404 }
405 else if (/* changes[i].old might be zero, e.g. when putting a
406 REG_FRAME_RELATED_EXPR into a previously empty list. */
407 changes[i].old
408 && REG_P (changes[i].old)
409 && asm_noperands (PATTERN (object)) > 0
410 && REG_EXPR (changes[i].old) != NULL_TREE
411 && HAS_DECL_ASSEMBLER_NAME_P (REG_EXPR (changes[i].old))
412 && DECL_ASSEMBLER_NAME_SET_P (REG_EXPR (changes[i].old))
413 && DECL_REGISTER (REG_EXPR (changes[i].old)))
414 {
415 /* Don't allow changes of hard register operands to inline
416 assemblies if they have been defined as register asm ("x"). */
417 break;
418 }
419 else if (DEBUG_INSN_P (object))
420 continue;
421 else if (insn_invalid_p (as_a <rtx_insn *> (object), true))
422 {
423 rtx pat = PATTERN (object);
424
425 /* Perhaps we couldn't recognize the insn because there were
426 extra CLOBBERs at the end. If so, try to re-recognize
427 without the last CLOBBER (later iterations will cause each of
428 them to be eliminated, in turn). But don't do this if we
429 have an ASM_OPERAND. */
430 if (GET_CODE (pat) == PARALLEL
431 && GET_CODE (XVECEXP (pat, 0, XVECLEN (pat, 0) - 1)) == CLOBBER
432 && asm_noperands (PATTERN (object)) < 0)
433 {
434 rtx newpat;
435
436 if (XVECLEN (pat, 0) == 2)
437 newpat = XVECEXP (pat, 0, 0);
438 else
439 {
440 int j;
441
442 newpat
443 = gen_rtx_PARALLEL (VOIDmode,
444 rtvec_alloc (XVECLEN (pat, 0) - 1));
445 for (j = 0; j < XVECLEN (newpat, 0); j++)
446 XVECEXP (newpat, 0, j) = XVECEXP (pat, 0, j);
447 }
448
449 /* Add a new change to this group to replace the pattern
450 with this new pattern. Then consider this change
451 as having succeeded. The change we added will
452 cause the entire call to fail if things remain invalid.
453
454 Note that this can lose if a later change than the one
455 we are processing specified &XVECEXP (PATTERN (object), 0, X)
456 but this shouldn't occur. */
457
458 validate_change (object, &PATTERN (object), newpat, 1);
459 continue;
460 }
461 else if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER
462 || GET_CODE (pat) == VAR_LOCATION)
463 /* If this insn is a CLOBBER or USE, it is always valid, but is
464 never recognized. */
465 continue;
466 else
467 break;
468 }
469 last_validated = object;
470 }
471
472 return (i == num_changes);
473}
474
475/* A group of changes has previously been issued with validate_change
476 and verified with verify_changes. Call df_insn_rescan for each of
477 the insn changed and clear num_changes. */
478
479void
480confirm_change_group (void)
481{
482 int i;
483 rtx last_object = NULL;
484
485 for (i = 0; i < num_changes; i++)
486 {
487 rtx object = changes[i].object;
488
489 if (changes[i].unshare)
490 *changes[i].loc = copy_rtx (*changes[i].loc);
491
492 /* Avoid unnecessary rescanning when multiple changes to same instruction
493 are made. */
494 if (object)
495 {
496 if (object != last_object && last_object && INSN_P (last_object))
497 df_insn_rescan (as_a <rtx_insn *> (last_object));
498 last_object = object;
499 }
500 }
501
502 if (last_object && INSN_P (last_object))
503 df_insn_rescan (as_a <rtx_insn *> (last_object));
504 num_changes = 0;
505}
506
507/* Apply a group of changes previously issued with `validate_change'.
508 If all changes are valid, call confirm_change_group and return 1,
509 otherwise, call cancel_changes and return 0. */
510
511int
512apply_change_group (void)
513{
514 if (verify_changes (0))
515 {
516 confirm_change_group ();
517 return 1;
518 }
519 else
520 {
521 cancel_changes (0);
522 return 0;
523 }
524}
525
526
527/* Return the number of changes so far in the current group. */
528
529int
530num_validated_changes (void)
531{
532 return num_changes;
533}
534
535/* Retract the changes numbered NUM and up. */
536
537void
538cancel_changes (int num)
539{
540 int i;
541
542 /* Back out all the changes. Do this in the opposite order in which
543 they were made. */
544 for (i = num_changes - 1; i >= num; i--)
545 {
546 *changes[i].loc = changes[i].old;
547 if (changes[i].object && !MEM_P (changes[i].object))
548 INSN_CODE (changes[i].object) = changes[i].old_code;
549 }
550 num_changes = num;
551}
552
553/* Reduce conditional compilation elsewhere. */
554/* A subroutine of validate_replace_rtx_1 that tries to simplify the resulting
555 rtx. */
556
557static void
558simplify_while_replacing (rtx *loc, rtx to, rtx_insn *object,
559 machine_mode op0_mode)
560{
561 rtx x = *loc;
562 enum rtx_code code = GET_CODE (x);
563 rtx new_rtx = NULL_RTX;
564 scalar_int_mode is_mode;
565
566 if (SWAPPABLE_OPERANDS_P (x)
567 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
568 {
569 validate_unshare_change (object, loc,
570 gen_rtx_fmt_ee (COMMUTATIVE_ARITH_P (x) ? code
571 : swap_condition (code),
572 GET_MODE (x), XEXP (x, 1),
573 XEXP (x, 0)), 1);
574 x = *loc;
575 code = GET_CODE (x);
576 }
577
578 /* Canonicalize arithmetics with all constant operands. */
579 switch (GET_RTX_CLASS (code))
580 {
581 case RTX_UNARY:
582 if (CONSTANT_P (XEXP (x, 0)))
583 new_rtx = simplify_unary_operation (code, GET_MODE (x), XEXP (x, 0),
584 op0_mode);
585 break;
586 case RTX_COMM_ARITH:
587 case RTX_BIN_ARITH:
588 if (CONSTANT_P (XEXP (x, 0)) && CONSTANT_P (XEXP (x, 1)))
589 new_rtx = simplify_binary_operation (code, GET_MODE (x), XEXP (x, 0),
590 XEXP (x, 1));
591 break;
592 case RTX_COMPARE:
593 case RTX_COMM_COMPARE:
594 if (CONSTANT_P (XEXP (x, 0)) && CONSTANT_P (XEXP (x, 1)))
595 new_rtx = simplify_relational_operation (code, GET_MODE (x), op0_mode,
596 XEXP (x, 0), XEXP (x, 1));
597 break;
598 default:
599 break;
600 }
601 if (new_rtx)
602 {
603 validate_change (object, loc, new_rtx, 1);
604 return;
605 }
606
607 switch (code)
608 {
609 case PLUS:
610 /* If we have a PLUS whose second operand is now a CONST_INT, use
611 simplify_gen_binary to try to simplify it.
612 ??? We may want later to remove this, once simplification is
613 separated from this function. */
614 if (CONST_INT_P (XEXP (x, 1)) && XEXP (x, 1) == to)
615 validate_change (object, loc,
616 simplify_gen_binary
617 (PLUS, GET_MODE (x), XEXP (x, 0), XEXP (x, 1)), 1);
618 break;
619 case MINUS:
620 if (CONST_SCALAR_INT_P (XEXP (x, 1)))
621 validate_change (object, loc,
622 simplify_gen_binary
623 (PLUS, GET_MODE (x), XEXP (x, 0),
624 simplify_gen_unary (NEG,
625 GET_MODE (x), XEXP (x, 1),
626 GET_MODE (x))), 1);
627 break;
628 case ZERO_EXTEND:
629 case SIGN_EXTEND:
630 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
631 {
632 new_rtx = simplify_gen_unary (code, GET_MODE (x), XEXP (x, 0),
633 op0_mode);
634 /* If any of the above failed, substitute in something that
635 we know won't be recognized. */
636 if (!new_rtx)
637 new_rtx = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
638 validate_change (object, loc, new_rtx, 1);
639 }
640 break;
641 case SUBREG:
642 /* All subregs possible to simplify should be simplified. */
643 new_rtx = simplify_subreg (GET_MODE (x), SUBREG_REG (x), op0_mode,
644 SUBREG_BYTE (x));
645
646 /* Subregs of VOIDmode operands are incorrect. */
647 if (!new_rtx && GET_MODE (SUBREG_REG (x)) == VOIDmode)
648 new_rtx = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
649 if (new_rtx)
650 validate_change (object, loc, new_rtx, 1);
651 break;
652 case ZERO_EXTRACT:
653 case SIGN_EXTRACT:
654 /* If we are replacing a register with memory, try to change the memory
655 to be the mode required for memory in extract operations (this isn't
656 likely to be an insertion operation; if it was, nothing bad will
657 happen, we might just fail in some cases). */
658
659 if (MEM_P (XEXP (x, 0))
660 && is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), &is_mode)
661 && CONST_INT_P (XEXP (x, 1))
662 && CONST_INT_P (XEXP (x, 2))
663 && !mode_dependent_address_p (XEXP (XEXP (x, 0), 0),
664 MEM_ADDR_SPACE (XEXP (x, 0)))
665 && !MEM_VOLATILE_P (XEXP (x, 0)))
666 {
667 int pos = INTVAL (XEXP (x, 2));
668 machine_mode new_mode = is_mode;
669 if (GET_CODE (x) == ZERO_EXTRACT && targetm.have_extzv ())
670 new_mode = insn_data[targetm.code_for_extzv].operand[1].mode;
671 else if (GET_CODE (x) == SIGN_EXTRACT && targetm.have_extv ())
672 new_mode = insn_data[targetm.code_for_extv].operand[1].mode;
673 scalar_int_mode wanted_mode = (new_mode == VOIDmode
674 ? word_mode
675 : as_a <scalar_int_mode> (new_mode));
676
677 /* If we have a narrower mode, we can do something. */
678 if (GET_MODE_SIZE (wanted_mode) < GET_MODE_SIZE (is_mode))
679 {
680 int offset = pos / BITS_PER_UNIT;
681 rtx newmem;
682
683 /* If the bytes and bits are counted differently, we
684 must adjust the offset. */
685 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN)
686 offset =
687 (GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (wanted_mode) -
688 offset);
689
690 gcc_assert (GET_MODE_PRECISION (wanted_mode)
691 == GET_MODE_BITSIZE (wanted_mode));
692 pos %= GET_MODE_BITSIZE (wanted_mode);
693
694 newmem = adjust_address_nv (XEXP (x, 0), wanted_mode, offset);
695
696 validate_change (object, &XEXP (x, 2), GEN_INT (pos), 1);
697 validate_change (object, &XEXP (x, 0), newmem, 1);
698 }
699 }
700
701 break;
702
703 default:
704 break;
705 }
706}
707
708/* Replace every occurrence of FROM in X with TO. Mark each change with
709 validate_change passing OBJECT. */
710
711static void
712validate_replace_rtx_1 (rtx *loc, rtx from, rtx to, rtx_insn *object,
713 bool simplify)
714{
715 int i, j;
716 const char *fmt;
717 rtx x = *loc;
718 enum rtx_code code;
719 machine_mode op0_mode = VOIDmode;
720 int prev_changes = num_changes;
721
722 if (!x)
723 return;
724
725 code = GET_CODE (x);
726 fmt = GET_RTX_FORMAT (code);
727 if (fmt[0] == 'e')
728 op0_mode = GET_MODE (XEXP (x, 0));
729
730 /* X matches FROM if it is the same rtx or they are both referring to the
731 same register in the same mode. Avoid calling rtx_equal_p unless the
732 operands look similar. */
733
734 if (x == from
735 || (REG_P (x) && REG_P (from)
736 && GET_MODE (x) == GET_MODE (from)
737 && REGNO (x) == REGNO (from))
738 || (GET_CODE (x) == GET_CODE (from) && GET_MODE (x) == GET_MODE (from)
739 && rtx_equal_p (x, from)))
740 {
741 validate_unshare_change (object, loc, to, 1);
742 return;
743 }
744
745 /* Call ourself recursively to perform the replacements.
746 We must not replace inside already replaced expression, otherwise we
747 get infinite recursion for replacements like (reg X)->(subreg (reg X))
748 so we must special case shared ASM_OPERANDS. */
749
750 if (GET_CODE (x) == PARALLEL)
751 {
752 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
753 {
754 if (j && GET_CODE (XVECEXP (x, 0, j)) == SET
755 && GET_CODE (SET_SRC (XVECEXP (x, 0, j))) == ASM_OPERANDS)
756 {
757 /* Verify that operands are really shared. */
758 gcc_assert (ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (x, 0, 0)))
759 == ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP
760 (x, 0, j))));
761 validate_replace_rtx_1 (&SET_DEST (XVECEXP (x, 0, j)),
762 from, to, object, simplify);
763 }
764 else
765 validate_replace_rtx_1 (&XVECEXP (x, 0, j), from, to, object,
766 simplify);
767 }
768 }
769 else
770 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
771 {
772 if (fmt[i] == 'e')
773 validate_replace_rtx_1 (&XEXP (x, i), from, to, object, simplify);
774 else if (fmt[i] == 'E')
775 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
776 validate_replace_rtx_1 (&XVECEXP (x, i, j), from, to, object,
777 simplify);
778 }
779
780 /* If we didn't substitute, there is nothing more to do. */
781 if (num_changes == prev_changes)
782 return;
783
784 /* ??? The regmove is no more, so is this aberration still necessary? */
785 /* Allow substituted expression to have different mode. This is used by
786 regmove to change mode of pseudo register. */
787 if (fmt[0] == 'e' && GET_MODE (XEXP (x, 0)) != VOIDmode)
788 op0_mode = GET_MODE (XEXP (x, 0));
789
790 /* Do changes needed to keep rtx consistent. Don't do any other
791 simplifications, as it is not our job. */
792 if (simplify)
793 simplify_while_replacing (loc, to, object, op0_mode);
794}
795
796/* Try replacing every occurrence of FROM in subexpression LOC of INSN
797 with TO. After all changes have been made, validate by seeing
798 if INSN is still valid. */
799
800int
801validate_replace_rtx_subexp (rtx from, rtx to, rtx_insn *insn, rtx *loc)
802{
803 validate_replace_rtx_1 (loc, from, to, insn, true);
804 return apply_change_group ();
805}
806
807/* Try replacing every occurrence of FROM in INSN with TO. After all
808 changes have been made, validate by seeing if INSN is still valid. */
809
810int
811validate_replace_rtx (rtx from, rtx to, rtx_insn *insn)
812{
813 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn, true);
814 return apply_change_group ();
815}
816
817/* Try replacing every occurrence of FROM in WHERE with TO. Assume that WHERE
818 is a part of INSN. After all changes have been made, validate by seeing if
819 INSN is still valid.
820 validate_replace_rtx (from, to, insn) is equivalent to
821 validate_replace_rtx_part (from, to, &PATTERN (insn), insn). */
822
823int
824validate_replace_rtx_part (rtx from, rtx to, rtx *where, rtx_insn *insn)
825{
826 validate_replace_rtx_1 (where, from, to, insn, true);
827 return apply_change_group ();
828}
829
830/* Same as above, but do not simplify rtx afterwards. */
831int
832validate_replace_rtx_part_nosimplify (rtx from, rtx to, rtx *where,
833 rtx_insn *insn)
834{
835 validate_replace_rtx_1 (where, from, to, insn, false);
836 return apply_change_group ();
837
838}
839
840/* Try replacing every occurrence of FROM in INSN with TO. This also
841 will replace in REG_EQUAL and REG_EQUIV notes. */
842
843void
844validate_replace_rtx_group (rtx from, rtx to, rtx_insn *insn)
845{
846 rtx note;
847 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn, true);
848 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
849 if (REG_NOTE_KIND (note) == REG_EQUAL
850 || REG_NOTE_KIND (note) == REG_EQUIV)
851 validate_replace_rtx_1 (&XEXP (note, 0), from, to, insn, true);
852}
853
854/* Function called by note_uses to replace used subexpressions. */
855struct validate_replace_src_data
856{
857 rtx from; /* Old RTX */
858 rtx to; /* New RTX */
859 rtx_insn *insn; /* Insn in which substitution is occurring. */
860};
861
862static void
863validate_replace_src_1 (rtx *x, void *data)
864{
865 struct validate_replace_src_data *d
866 = (struct validate_replace_src_data *) data;
867
868 validate_replace_rtx_1 (x, d->from, d->to, d->insn, true);
869}
870
871/* Try replacing every occurrence of FROM in INSN with TO, avoiding
872 SET_DESTs. */
873
874void
875validate_replace_src_group (rtx from, rtx to, rtx_insn *insn)
876{
877 struct validate_replace_src_data d;
878
879 d.from = from;
880 d.to = to;
881 d.insn = insn;
882 note_uses (&PATTERN (insn), validate_replace_src_1, &d);
883}
884
885/* Try simplify INSN.
886 Invoke simplify_rtx () on every SET_SRC and SET_DEST inside the INSN's
887 pattern and return true if something was simplified. */
888
889bool
890validate_simplify_insn (rtx_insn *insn)
891{
892 int i;
893 rtx pat = NULL;
894 rtx newpat = NULL;
895
896 pat = PATTERN (insn);
897
898 if (GET_CODE (pat) == SET)
899 {
900 newpat = simplify_rtx (SET_SRC (pat));
901 if (newpat && !rtx_equal_p (SET_SRC (pat), newpat))
902 validate_change (insn, &SET_SRC (pat), newpat, 1);
903 newpat = simplify_rtx (SET_DEST (pat));
904 if (newpat && !rtx_equal_p (SET_DEST (pat), newpat))
905 validate_change (insn, &SET_DEST (pat), newpat, 1);
906 }
907 else if (GET_CODE (pat) == PARALLEL)
908 for (i = 0; i < XVECLEN (pat, 0); i++)
909 {
910 rtx s = XVECEXP (pat, 0, i);
911
912 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
913 {
914 newpat = simplify_rtx (SET_SRC (s));
915 if (newpat && !rtx_equal_p (SET_SRC (s), newpat))
916 validate_change (insn, &SET_SRC (s), newpat, 1);
917 newpat = simplify_rtx (SET_DEST (s));
918 if (newpat && !rtx_equal_p (SET_DEST (s), newpat))
919 validate_change (insn, &SET_DEST (s), newpat, 1);
920 }
921 }
922 return ((num_changes_pending () > 0) && (apply_change_group () > 0));
923}
924
925/* Return 1 if the insn using CC0 set by INSN does not contain
926 any ordered tests applied to the condition codes.
927 EQ and NE tests do not count. */
928
929int
930next_insn_tests_no_inequality (rtx_insn *insn)
931{
932 rtx_insn *next = next_cc0_user (insn);
933
934 /* If there is no next insn, we have to take the conservative choice. */
935 if (next == 0)
936 return 0;
937
938 return (INSN_P (next)
939 && ! inequality_comparisons_p (PATTERN (next)));
940}
941
942/* Return 1 if OP is a valid general operand for machine mode MODE.
943 This is either a register reference, a memory reference,
944 or a constant. In the case of a memory reference, the address
945 is checked for general validity for the target machine.
946
947 Register and memory references must have mode MODE in order to be valid,
948 but some constants have no machine mode and are valid for any mode.
949
950 If MODE is VOIDmode, OP is checked for validity for whatever mode
951 it has.
952
953 The main use of this function is as a predicate in match_operand
954 expressions in the machine description. */
955
956int
957general_operand (rtx op, machine_mode mode)
958{
959 enum rtx_code code = GET_CODE (op);
960
961 if (mode == VOIDmode)
962 mode = GET_MODE (op);
963
964 /* Don't accept CONST_INT or anything similar
965 if the caller wants something floating. */
966 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
967 && GET_MODE_CLASS (mode) != MODE_INT
968 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
969 return 0;
970
971 if (CONST_INT_P (op)
972 && mode != VOIDmode
973 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op))
974 return 0;
975
976 if (CONSTANT_P (op))
977 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode
978 || mode == VOIDmode)
979 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
980 && targetm.legitimate_constant_p (mode == VOIDmode
981 ? GET_MODE (op)
982 : mode, op));
983
984 /* Except for certain constants with VOIDmode, already checked for,
985 OP's mode must match MODE if MODE specifies a mode. */
986
987 if (GET_MODE (op) != mode)
988 return 0;
989
990 if (code == SUBREG)
991 {
992 rtx sub = SUBREG_REG (op);
993
994#ifdef INSN_SCHEDULING
995 /* On machines that have insn scheduling, we want all memory
996 reference to be explicit, so outlaw paradoxical SUBREGs.
997 However, we must allow them after reload so that they can
998 get cleaned up by cleanup_subreg_operands. */
999 if (!reload_completed && MEM_P (sub)
1000 && paradoxical_subreg_p (op))
1001 return 0;
1002#endif
1003 /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory
1004 may result in incorrect reference. We should simplify all valid
1005 subregs of MEM anyway. But allow this after reload because we
1006 might be called from cleanup_subreg_operands.
1007
1008 ??? This is a kludge. */
1009 if (!reload_completed && SUBREG_BYTE (op) != 0
1010 && MEM_P (sub))
1011 return 0;
1012
1013 if (REG_P (sub)
1014 && REGNO (sub) < FIRST_PSEUDO_REGISTER
1015 && !REG_CAN_CHANGE_MODE_P (REGNO (sub), GET_MODE (sub), mode)
1016 && GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_INT
1017 && GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_FLOAT
1018 /* LRA can generate some invalid SUBREGS just for matched
1019 operand reload presentation. LRA needs to treat them as
1020 valid. */
1021 && ! LRA_SUBREG_P (op))
1022 return 0;
1023
1024 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
1025 create such rtl, and we must reject it. */
1026 if (SCALAR_FLOAT_MODE_P (GET_MODE (op))
1027 /* LRA can use subreg to store a floating point value in an
1028 integer mode. Although the floating point and the
1029 integer modes need the same number of hard registers, the
1030 size of floating point mode can be less than the integer
1031 mode. */
1032 && ! lra_in_progress
1033 && paradoxical_subreg_p (op))
1034 return 0;
1035
1036 op = sub;
1037 code = GET_CODE (op);
1038 }
1039
1040 if (code == REG)
1041 return (REGNO (op) >= FIRST_PSEUDO_REGISTER
1042 || in_hard_reg_set_p (operand_reg_set, GET_MODE (op), REGNO (op)));
1043
1044 if (code == MEM)
1045 {
1046 rtx y = XEXP (op, 0);
1047
1048 if (! volatile_ok && MEM_VOLATILE_P (op))
1049 return 0;
1050
1051 /* Use the mem's mode, since it will be reloaded thus. LRA can
1052 generate move insn with invalid addresses which is made valid
1053 and efficiently calculated by LRA through further numerous
1054 transformations. */
1055 if (lra_in_progress
1056 || memory_address_addr_space_p (GET_MODE (op), y, MEM_ADDR_SPACE (op)))
1057 return 1;
1058 }
1059
1060 return 0;
1061}
1062
1063/* Return 1 if OP is a valid memory address for a memory reference
1064 of mode MODE.
1065
1066 The main use of this function is as a predicate in match_operand
1067 expressions in the machine description. */
1068
1069int
1070address_operand (rtx op, machine_mode mode)
1071{
1072 return memory_address_p (mode, op);
1073}
1074
1075/* Return 1 if OP is a register reference of mode MODE.
1076 If MODE is VOIDmode, accept a register in any mode.
1077
1078 The main use of this function is as a predicate in match_operand
1079 expressions in the machine description. */
1080
1081int
1082register_operand (rtx op, machine_mode mode)
1083{
1084 if (GET_CODE (op) == SUBREG)
1085 {
1086 rtx sub = SUBREG_REG (op);
1087
1088 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1089 because it is guaranteed to be reloaded into one.
1090 Just make sure the MEM is valid in itself.
1091 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1092 but currently it does result from (SUBREG (REG)...) where the
1093 reg went on the stack.) */
1094 if (!REG_P (sub) && (reload_completed || !MEM_P (sub)))
1095 return 0;
1096 }
1097 else if (!REG_P (op))
1098 return 0;
1099 return general_operand (op, mode);
1100}
1101
1102/* Return 1 for a register in Pmode; ignore the tested mode. */
1103
1104int
1105pmode_register_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
1106{
1107 return register_operand (op, Pmode);
1108}
1109
1110/* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1111 or a hard register. */
1112
1113int
1114scratch_operand (rtx op, machine_mode mode)
1115{
1116 if (GET_MODE (op) != mode && mode != VOIDmode)
1117 return 0;
1118
1119 return (GET_CODE (op) == SCRATCH
1120 || (REG_P (op)
1121 && (lra_in_progress
1122 || (REGNO (op) < FIRST_PSEUDO_REGISTER
1123 && REGNO_REG_CLASS (REGNO (op)) != NO_REGS))));
1124}
1125
1126/* Return 1 if OP is a valid immediate operand for mode MODE.
1127
1128 The main use of this function is as a predicate in match_operand
1129 expressions in the machine description. */
1130
1131int
1132immediate_operand (rtx op, machine_mode mode)
1133{
1134 /* Don't accept CONST_INT or anything similar
1135 if the caller wants something floating. */
1136 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1137 && GET_MODE_CLASS (mode) != MODE_INT
1138 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1139 return 0;
1140
1141 if (CONST_INT_P (op)
1142 && mode != VOIDmode
1143 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op))
1144 return 0;
1145
1146 return (CONSTANT_P (op)
1147 && (GET_MODE (op) == mode || mode == VOIDmode
1148 || GET_MODE (op) == VOIDmode)
1149 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1150 && targetm.legitimate_constant_p (mode == VOIDmode
1151 ? GET_MODE (op)
1152 : mode, op));
1153}
1154
1155/* Returns 1 if OP is an operand that is a CONST_INT of mode MODE. */
1156
1157int
1158const_int_operand (rtx op, machine_mode mode)
1159{
1160 if (!CONST_INT_P (op))
1161 return 0;
1162
1163 if (mode != VOIDmode
1164 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op))
1165 return 0;
1166
1167 return 1;
1168}
1169
1170#if TARGET_SUPPORTS_WIDE_INT
1171/* Returns 1 if OP is an operand that is a CONST_INT or CONST_WIDE_INT
1172 of mode MODE. */
1173int
1174const_scalar_int_operand (rtx op, machine_mode mode)
1175{
1176 if (!CONST_SCALAR_INT_P (op))
1177 return 0;
1178
1179 if (CONST_INT_P (op))
1180 return const_int_operand (op, mode);
1181
1182 if (mode != VOIDmode)
1183 {
1184 scalar_int_mode int_mode = as_a <scalar_int_mode> (mode);
1185 int prec = GET_MODE_PRECISION (int_mode);
1186 int bitsize = GET_MODE_BITSIZE (int_mode);
1187
1188 if (CONST_WIDE_INT_NUNITS (op) * HOST_BITS_PER_WIDE_INT > bitsize)
1189 return 0;
1190
1191 if (prec == bitsize)
1192 return 1;
1193 else
1194 {
1195 /* Multiword partial int. */
1196 HOST_WIDE_INT x
1197 = CONST_WIDE_INT_ELT (op, CONST_WIDE_INT_NUNITS (op) - 1);
1198 return (sext_hwi (x, prec & (HOST_BITS_PER_WIDE_INT - 1)) == x);
1199 }
1200 }
1201 return 1;
1202}
1203
1204/* Returns 1 if OP is an operand that is a constant integer or constant
1205 floating-point number of MODE. */
1206
1207int
1208const_double_operand (rtx op, machine_mode mode)
1209{
1210 return (GET_CODE (op) == CONST_DOUBLE)
1211 && (GET_MODE (op) == mode || mode == VOIDmode);
1212}
1213#else
1214/* Returns 1 if OP is an operand that is a constant integer or constant
1215 floating-point number of MODE. */
1216
1217int
1218const_double_operand (rtx op, machine_mode mode)
1219{
1220 /* Don't accept CONST_INT or anything similar
1221 if the caller wants something floating. */
1222 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1223 && GET_MODE_CLASS (mode) != MODE_INT
1224 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1225 return 0;
1226
1227 return ((CONST_DOUBLE_P (op) || CONST_INT_P (op))
1228 && (mode == VOIDmode || GET_MODE (op) == mode
1229 || GET_MODE (op) == VOIDmode));
1230}
1231#endif
1232/* Return 1 if OP is a general operand that is not an immediate
1233 operand of mode MODE. */
1234
1235int
1236nonimmediate_operand (rtx op, machine_mode mode)
1237{
1238 return (general_operand (op, mode) && ! CONSTANT_P (op));
1239}
1240
1241/* Return 1 if OP is a register reference or immediate value of mode MODE. */
1242
1243int
1244nonmemory_operand (rtx op, machine_mode mode)
1245{
1246 if (CONSTANT_P (op))
1247 return immediate_operand (op, mode);
1248 return register_operand (op, mode);
1249}
1250
1251/* Return 1 if OP is a valid operand that stands for pushing a
1252 value of mode MODE onto the stack.
1253
1254 The main use of this function is as a predicate in match_operand
1255 expressions in the machine description. */
1256
1257int
1258push_operand (rtx op, machine_mode mode)
1259{
1260 unsigned int rounded_size = GET_MODE_SIZE (mode);
1261
1262#ifdef PUSH_ROUNDING
1263 rounded_size = PUSH_ROUNDING (rounded_size);
1264#endif
1265
1266 if (!MEM_P (op))
1267 return 0;
1268
1269 if (mode != VOIDmode && GET_MODE (op) != mode)
1270 return 0;
1271
1272 op = XEXP (op, 0);
1273
1274 if (rounded_size == GET_MODE_SIZE (mode))
1275 {
1276 if (GET_CODE (op) != STACK_PUSH_CODE)
1277 return 0;
1278 }
1279 else
1280 {
1281 if (GET_CODE (op) != PRE_MODIFY
1282 || GET_CODE (XEXP (op, 1)) != PLUS
1283 || XEXP (XEXP (op, 1), 0) != XEXP (op, 0)
1284 || !CONST_INT_P (XEXP (XEXP (op, 1), 1))
1285 || INTVAL (XEXP (XEXP (op, 1), 1))
1286 != ((STACK_GROWS_DOWNWARD ? -1 : 1) * (int) rounded_size))
1287 return 0;
1288 }
1289
1290 return XEXP (op, 0) == stack_pointer_rtx;
1291}
1292
1293/* Return 1 if OP is a valid operand that stands for popping a
1294 value of mode MODE off the stack.
1295
1296 The main use of this function is as a predicate in match_operand
1297 expressions in the machine description. */
1298
1299int
1300pop_operand (rtx op, machine_mode mode)
1301{
1302 if (!MEM_P (op))
1303 return 0;
1304
1305 if (mode != VOIDmode && GET_MODE (op) != mode)
1306 return 0;
1307
1308 op = XEXP (op, 0);
1309
1310 if (GET_CODE (op) != STACK_POP_CODE)
1311 return 0;
1312
1313 return XEXP (op, 0) == stack_pointer_rtx;
1314}
1315
1316/* Return 1 if ADDR is a valid memory address
1317 for mode MODE in address space AS. */
1318
1319int
1320memory_address_addr_space_p (machine_mode mode ATTRIBUTE_UNUSED,
1321 rtx addr, addr_space_t as)
1322{
1323#ifdef GO_IF_LEGITIMATE_ADDRESS
1324 gcc_assert (ADDR_SPACE_GENERIC_P (as));
1325 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
1326 return 0;
1327
1328 win:
1329 return 1;
1330#else
1331 return targetm.addr_space.legitimate_address_p (mode, addr, 0, as);
1332#endif
1333}
1334
1335/* Return 1 if OP is a valid memory reference with mode MODE,
1336 including a valid address.
1337
1338 The main use of this function is as a predicate in match_operand
1339 expressions in the machine description. */
1340
1341int
1342memory_operand (rtx op, machine_mode mode)
1343{
1344 rtx inner;
1345
1346 if (! reload_completed)
1347 /* Note that no SUBREG is a memory operand before end of reload pass,
1348 because (SUBREG (MEM...)) forces reloading into a register. */
1349 return MEM_P (op) && general_operand (op, mode);
1350
1351 if (mode != VOIDmode && GET_MODE (op) != mode)
1352 return 0;
1353
1354 inner = op;
1355 if (GET_CODE (inner) == SUBREG)
1356 inner = SUBREG_REG (inner);
1357
1358 return (MEM_P (inner) && general_operand (op, mode));
1359}
1360
1361/* Return 1 if OP is a valid indirect memory reference with mode MODE;
1362 that is, a memory reference whose address is a general_operand. */
1363
1364int
1365indirect_operand (rtx op, machine_mode mode)
1366{
1367 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1368 if (! reload_completed
1369 && GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))
1370 {
1371 int offset = SUBREG_BYTE (op);
1372 rtx inner = SUBREG_REG (op);
1373
1374 if (mode != VOIDmode && GET_MODE (op) != mode)
1375 return 0;
1376
1377 /* The only way that we can have a general_operand as the resulting
1378 address is if OFFSET is zero and the address already is an operand
1379 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1380 operand. */
1381
1382 return ((offset == 0 && general_operand (XEXP (inner, 0), Pmode))
1383 || (GET_CODE (XEXP (inner, 0)) == PLUS
1384 && CONST_INT_P (XEXP (XEXP (inner, 0), 1))
1385 && INTVAL (XEXP (XEXP (inner, 0), 1)) == -offset
1386 && general_operand (XEXP (XEXP (inner, 0), 0), Pmode)));
1387 }
1388
1389 return (MEM_P (op)
1390 && memory_operand (op, mode)
1391 && general_operand (XEXP (op, 0), Pmode));
1392}
1393
1394/* Return 1 if this is an ordered comparison operator (not including
1395 ORDERED and UNORDERED). */
1396
1397int
1398ordered_comparison_operator (rtx op, machine_mode mode)
1399{
1400 if (mode != VOIDmode && GET_MODE (op) != mode)
1401 return false;
1402 switch (GET_CODE (op))
1403 {
1404 case EQ:
1405 case NE:
1406 case LT:
1407 case LTU:
1408 case LE:
1409 case LEU:
1410 case GT:
1411 case GTU:
1412 case GE:
1413 case GEU:
1414 return true;
1415 default:
1416 return false;
1417 }
1418}
1419
1420/* Return 1 if this is a comparison operator. This allows the use of
1421 MATCH_OPERATOR to recognize all the branch insns. */
1422
1423int
1424comparison_operator (rtx op, machine_mode mode)
1425{
1426 return ((mode == VOIDmode || GET_MODE (op) == mode)
1427 && COMPARISON_P (op));
1428}
1429
1430/* If BODY is an insn body that uses ASM_OPERANDS, return it. */
1431
1432rtx
1433extract_asm_operands (rtx body)
1434{
1435 rtx tmp;
1436 switch (GET_CODE (body))
1437 {
1438 case ASM_OPERANDS:
1439 return body;
1440
1441 case SET:
1442 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1443 tmp = SET_SRC (body);
1444 if (GET_CODE (tmp) == ASM_OPERANDS)
1445 return tmp;
1446 break;
1447
1448 case PARALLEL:
1449 tmp = XVECEXP (body, 0, 0);
1450 if (GET_CODE (tmp) == ASM_OPERANDS)
1451 return tmp;
1452 if (GET_CODE (tmp) == SET)
1453 {
1454 tmp = SET_SRC (tmp);
1455 if (GET_CODE (tmp) == ASM_OPERANDS)
1456 return tmp;
1457 }
1458 break;
1459
1460 default:
1461 break;
1462 }
1463 return NULL;
1464}
1465
1466/* If BODY is an insn body that uses ASM_OPERANDS,
1467 return the number of operands (both input and output) in the insn.
1468 If BODY is an insn body that uses ASM_INPUT with CLOBBERS in PARALLEL,
1469 return 0.
1470 Otherwise return -1. */
1471
1472int
1473asm_noperands (const_rtx body)
1474{
1475 rtx asm_op = extract_asm_operands (CONST_CAST_RTX (body));
1476 int i, n_sets = 0;
1477
1478 if (asm_op == NULL)
1479 {
1480 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) >= 2
1481 && GET_CODE (XVECEXP (body, 0, 0)) == ASM_INPUT)
1482 {
1483 /* body is [(asm_input ...) (clobber (reg ...))...]. */
1484 for (i = XVECLEN (body, 0) - 1; i > 0; i--)
1485 if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER)
1486 return -1;
1487 return 0;
1488 }
1489 return -1;
1490 }
1491
1492 if (GET_CODE (body) == SET)
1493 n_sets = 1;
1494 else if (GET_CODE (body) == PARALLEL)
1495 {
1496 if (GET_CODE (XVECEXP (body, 0, 0)) == SET)
1497 {
1498 /* Multiple output operands, or 1 output plus some clobbers:
1499 body is
1500 [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1501 /* Count backwards through CLOBBERs to determine number of SETs. */
1502 for (i = XVECLEN (body, 0); i > 0; i--)
1503 {
1504 if (GET_CODE (XVECEXP (body, 0, i - 1)) == SET)
1505 break;
1506 if (GET_CODE (XVECEXP (body, 0, i - 1)) != CLOBBER)
1507 return -1;
1508 }
1509
1510 /* N_SETS is now number of output operands. */
1511 n_sets = i;
1512
1513 /* Verify that all the SETs we have
1514 came from a single original asm_operands insn
1515 (so that invalid combinations are blocked). */
1516 for (i = 0; i < n_sets; i++)
1517 {
1518 rtx elt = XVECEXP (body, 0, i);
1519 if (GET_CODE (elt) != SET)
1520 return -1;
1521 if (GET_CODE (SET_SRC (elt)) != ASM_OPERANDS)
1522 return -1;
1523 /* If these ASM_OPERANDS rtx's came from different original insns
1524 then they aren't allowed together. */
1525 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt))
1526 != ASM_OPERANDS_INPUT_VEC (asm_op))
1527 return -1;
1528 }
1529 }
1530 else
1531 {
1532 /* 0 outputs, but some clobbers:
1533 body is [(asm_operands ...) (clobber (reg ...))...]. */
1534 /* Make sure all the other parallel things really are clobbers. */
1535 for (i = XVECLEN (body, 0) - 1; i > 0; i--)
1536 if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER)
1537 return -1;
1538 }
1539 }
1540
1541 return (ASM_OPERANDS_INPUT_LENGTH (asm_op)
1542 + ASM_OPERANDS_LABEL_LENGTH (asm_op) + n_sets);
1543}
1544
1545/* Assuming BODY is an insn body that uses ASM_OPERANDS,
1546 copy its operands (both input and output) into the vector OPERANDS,
1547 the locations of the operands within the insn into the vector OPERAND_LOCS,
1548 and the constraints for the operands into CONSTRAINTS.
1549 Write the modes of the operands into MODES.
1550 Write the location info into LOC.
1551 Return the assembler-template.
1552 If BODY is an insn body that uses ASM_INPUT with CLOBBERS in PARALLEL,
1553 return the basic assembly string.
1554
1555 If LOC, MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1556 we don't store that info. */
1557
1558const char *
1559decode_asm_operands (rtx body, rtx *operands, rtx **operand_locs,
1560 const char **constraints, machine_mode *modes,
1561 location_t *loc)
1562{
1563 int nbase = 0, n, i;
1564 rtx asmop;
1565
1566 switch (GET_CODE (body))
1567 {
1568 case ASM_OPERANDS:
1569 /* Zero output asm: BODY is (asm_operands ...). */
1570 asmop = body;
1571 break;
1572
1573 case SET:
1574 /* Single output asm: BODY is (set OUTPUT (asm_operands ...)). */
1575 asmop = SET_SRC (body);
1576
1577 /* The output is in the SET.
1578 Its constraint is in the ASM_OPERANDS itself. */
1579 if (operands)
1580 operands[0] = SET_DEST (body);
1581 if (operand_locs)
1582 operand_locs[0] = &SET_DEST (body);
1583 if (constraints)
1584 constraints[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop);
1585 if (modes)
1586 modes[0] = GET_MODE (SET_DEST (body));
1587 nbase = 1;
1588 break;
1589
1590 case PARALLEL:
1591 {
1592 int nparallel = XVECLEN (body, 0); /* Includes CLOBBERs. */
1593
1594 asmop = XVECEXP (body, 0, 0);
1595 if (GET_CODE (asmop) == SET)
1596 {
1597 asmop = SET_SRC (asmop);
1598
1599 /* At least one output, plus some CLOBBERs. The outputs are in
1600 the SETs. Their constraints are in the ASM_OPERANDS itself. */
1601 for (i = 0; i < nparallel; i++)
1602 {
1603 if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER)
1604 break; /* Past last SET */
1605 if (operands)
1606 operands[i] = SET_DEST (XVECEXP (body, 0, i));
1607 if (operand_locs)
1608 operand_locs[i] = &SET_DEST (XVECEXP (body, 0, i));
1609 if (constraints)
1610 constraints[i] = XSTR (SET_SRC (XVECEXP (body, 0, i)), 1);
1611 if (modes)
1612 modes[i] = GET_MODE (SET_DEST (XVECEXP (body, 0, i)));
1613 }
1614 nbase = i;
1615 }
1616 else if (GET_CODE (asmop) == ASM_INPUT)
1617 {
1618 if (loc)
1619 *loc = ASM_INPUT_SOURCE_LOCATION (asmop);
1620 return XSTR (asmop, 0);
1621 }
1622 break;
1623 }
1624
1625 default:
1626 gcc_unreachable ();
1627 }
1628
1629 n = ASM_OPERANDS_INPUT_LENGTH (asmop);
1630 for (i = 0; i < n; i++)
1631 {
1632 if (operand_locs)
1633 operand_locs[nbase + i] = &ASM_OPERANDS_INPUT (asmop, i);
1634 if (operands)
1635 operands[nbase + i] = ASM_OPERANDS_INPUT (asmop, i);
1636 if (constraints)
1637 constraints[nbase + i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i);
1638 if (modes)
1639 modes[nbase + i] = ASM_OPERANDS_INPUT_MODE (asmop, i);
1640 }
1641 nbase += n;
1642
1643 n = ASM_OPERANDS_LABEL_LENGTH (asmop);
1644 for (i = 0; i < n; i++)
1645 {
1646 if (operand_locs)
1647 operand_locs[nbase + i] = &ASM_OPERANDS_LABEL (asmop, i);
1648 if (operands)
1649 operands[nbase + i] = ASM_OPERANDS_LABEL (asmop, i);
1650 if (constraints)
1651 constraints[nbase + i] = "";
1652 if (modes)
1653 modes[nbase + i] = Pmode;
1654 }
1655
1656 if (loc)
1657 *loc = ASM_OPERANDS_SOURCE_LOCATION (asmop);
1658
1659 return ASM_OPERANDS_TEMPLATE (asmop);
1660}
1661
1662/* Parse inline assembly string STRING and determine which operands are
1663 referenced by % markers. For the first NOPERANDS operands, set USED[I]
1664 to true if operand I is referenced.
1665
1666 This is intended to distinguish barrier-like asms such as:
1667
1668 asm ("" : "=m" (...));
1669
1670 from real references such as:
1671
1672 asm ("sw\t$0, %0" : "=m" (...)); */
1673
1674void
1675get_referenced_operands (const char *string, bool *used,
1676 unsigned int noperands)
1677{
1678 memset (used, 0, sizeof (bool) * noperands);
1679 const char *p = string;
1680 while (*p)
1681 switch (*p)
1682 {
1683 case '%':
1684 p += 1;
1685 /* A letter followed by a digit indicates an operand number. */
1686 if (ISALPHA (p[0]) && ISDIGIT (p[1]))
1687 p += 1;
1688 if (ISDIGIT (*p))
1689 {
1690 char *endptr;
1691 unsigned long opnum = strtoul (p, &endptr, 10);
1692 if (endptr != p && opnum < noperands)
1693 used[opnum] = true;
1694 p = endptr;
1695 }
1696 else
1697 p += 1;
1698 break;
1699
1700 default:
1701 p++;
1702 break;
1703 }
1704}
1705
1706/* Check if an asm_operand matches its constraints.
1707 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1708
1709int
1710asm_operand_ok (rtx op, const char *constraint, const char **constraints)
1711{
1712 int result = 0;
1713 bool incdec_ok = false;
1714
1715 /* Use constrain_operands after reload. */
1716 gcc_assert (!reload_completed);
1717
1718 /* Empty constraint string is the same as "X,...,X", i.e. X for as
1719 many alternatives as required to match the other operands. */
1720 if (*constraint == '\0')
1721 result = 1;
1722
1723 while (*constraint)
1724 {
1725 enum constraint_num cn;
1726 char c = *constraint;
1727 int len;
1728 switch (c)
1729 {
1730 case ',':
1731 constraint++;
1732 continue;
1733
1734 case '0': case '1': case '2': case '3': case '4':
1735 case '5': case '6': case '7': case '8': case '9':
1736 /* If caller provided constraints pointer, look up
1737 the matching constraint. Otherwise, our caller should have
1738 given us the proper matching constraint, but we can't
1739 actually fail the check if they didn't. Indicate that
1740 results are inconclusive. */
1741 if (constraints)
1742 {
1743 char *end;
1744 unsigned long match;
1745
1746 match = strtoul (constraint, &end, 10);
1747 if (!result)
1748 result = asm_operand_ok (op, constraints[match], NULL);
1749 constraint = (const char *) end;
1750 }
1751 else
1752 {
1753 do
1754 constraint++;
1755 while (ISDIGIT (*constraint));
1756 if (! result)
1757 result = -1;
1758 }
1759 continue;
1760
1761 /* The rest of the compiler assumes that reloading the address
1762 of a MEM into a register will make it fit an 'o' constraint.
1763 That is, if it sees a MEM operand for an 'o' constraint,
1764 it assumes that (mem (base-reg)) will fit.
1765
1766 That assumption fails on targets that don't have offsettable
1767 addresses at all. We therefore need to treat 'o' asm
1768 constraints as a special case and only accept operands that
1769 are already offsettable, thus proving that at least one
1770 offsettable address exists. */
1771 case 'o': /* offsettable */
1772 if (offsettable_nonstrict_memref_p (op))
1773 result = 1;
1774 break;
1775
1776 case 'g':
1777 if (general_operand (op, VOIDmode))
1778 result = 1;
1779 break;
1780
1781 case '<':
1782 case '>':
1783 /* ??? Before auto-inc-dec, auto inc/dec insns are not supposed
1784 to exist, excepting those that expand_call created. Further,
1785 on some machines which do not have generalized auto inc/dec,
1786 an inc/dec is not a memory_operand.
1787
1788 Match any memory and hope things are resolved after reload. */
1789 incdec_ok = true;
1790 /* FALLTHRU */
1791 default:
1792 cn = lookup_constraint (constraint);
1793 switch (get_constraint_type (cn))
1794 {
1795 case CT_REGISTER:
1796 if (!result
1797 && reg_class_for_constraint (cn) != NO_REGS
1798 && GET_MODE (op) != BLKmode
1799 && register_operand (op, VOIDmode))
1800 result = 1;
1801 break;
1802
1803 case CT_CONST_INT:
1804 if (!result
1805 && CONST_INT_P (op)
1806 && insn_const_int_ok_for_constraint (INTVAL (op), cn))
1807 result = 1;
1808 break;
1809
1810 case CT_MEMORY:
1811 case CT_SPECIAL_MEMORY:
1812 /* Every memory operand can be reloaded to fit. */
1813 result = result || memory_operand (op, VOIDmode);
1814 break;
1815
1816 case CT_ADDRESS:
1817 /* Every address operand can be reloaded to fit. */
1818 result = result || address_operand (op, VOIDmode);
1819 break;
1820
1821 case CT_FIXED_FORM:
1822 result = result || constraint_satisfied_p (op, cn);
1823 break;
1824 }
1825 break;
1826 }
1827 len = CONSTRAINT_LEN (c, constraint);
1828 do
1829 constraint++;
1830 while (--len && *constraint);
1831 if (len)
1832 return 0;
1833 }
1834
1835 /* For operands without < or > constraints reject side-effects. */
1836 if (AUTO_INC_DEC && !incdec_ok && result && MEM_P (op))
1837 switch (GET_CODE (XEXP (op, 0)))
1838 {
1839 case PRE_INC:
1840 case POST_INC:
1841 case PRE_DEC:
1842 case POST_DEC:
1843 case PRE_MODIFY:
1844 case POST_MODIFY:
1845 return 0;
1846 default:
1847 break;
1848 }
1849
1850 return result;
1851}
1852
1853/* Given an rtx *P, if it is a sum containing an integer constant term,
1854 return the location (type rtx *) of the pointer to that constant term.
1855 Otherwise, return a null pointer. */
1856
1857rtx *
1858find_constant_term_loc (rtx *p)
1859{
1860 rtx *tem;
1861 enum rtx_code code = GET_CODE (*p);
1862
1863 /* If *P IS such a constant term, P is its location. */
1864
1865 if (code == CONST_INT || code == SYMBOL_REF || code == LABEL_REF
1866 || code == CONST)
1867 return p;
1868
1869 /* Otherwise, if not a sum, it has no constant term. */
1870
1871 if (GET_CODE (*p) != PLUS)
1872 return 0;
1873
1874 /* If one of the summands is constant, return its location. */
1875
1876 if (XEXP (*p, 0) && CONSTANT_P (XEXP (*p, 0))
1877 && XEXP (*p, 1) && CONSTANT_P (XEXP (*p, 1)))
1878 return p;
1879
1880 /* Otherwise, check each summand for containing a constant term. */
1881
1882 if (XEXP (*p, 0) != 0)
1883 {
1884 tem = find_constant_term_loc (&XEXP (*p, 0));
1885 if (tem != 0)
1886 return tem;
1887 }
1888
1889 if (XEXP (*p, 1) != 0)
1890 {
1891 tem = find_constant_term_loc (&XEXP (*p, 1));
1892 if (tem != 0)
1893 return tem;
1894 }
1895
1896 return 0;
1897}
1898
1899/* Return 1 if OP is a memory reference
1900 whose address contains no side effects
1901 and remains valid after the addition
1902 of a positive integer less than the
1903 size of the object being referenced.
1904
1905 We assume that the original address is valid and do not check it.
1906
1907 This uses strict_memory_address_p as a subroutine, so
1908 don't use it before reload. */
1909
1910int
1911offsettable_memref_p (rtx op)
1912{
1913 return ((MEM_P (op))
1914 && offsettable_address_addr_space_p (1, GET_MODE (op), XEXP (op, 0),
1915 MEM_ADDR_SPACE (op)));
1916}
1917
1918/* Similar, but don't require a strictly valid mem ref:
1919 consider pseudo-regs valid as index or base regs. */
1920
1921int
1922offsettable_nonstrict_memref_p (rtx op)
1923{
1924 return ((MEM_P (op))
1925 && offsettable_address_addr_space_p (0, GET_MODE (op), XEXP (op, 0),
1926 MEM_ADDR_SPACE (op)));
1927}
1928
1929/* Return 1 if Y is a memory address which contains no side effects
1930 and would remain valid for address space AS after the addition of
1931 a positive integer less than the size of that mode.
1932
1933 We assume that the original address is valid and do not check it.
1934 We do check that it is valid for narrower modes.
1935
1936 If STRICTP is nonzero, we require a strictly valid address,
1937 for the sake of use in reload.c. */
1938
1939int
1940offsettable_address_addr_space_p (int strictp, machine_mode mode, rtx y,
1941 addr_space_t as)
1942{
1943 enum rtx_code ycode = GET_CODE (y);
1944 rtx z;
1945 rtx y1 = y;
1946 rtx *y2;
1947 int (*addressp) (machine_mode, rtx, addr_space_t) =
1948 (strictp ? strict_memory_address_addr_space_p
1949 : memory_address_addr_space_p);
1950 unsigned int mode_sz = GET_MODE_SIZE (mode);
1951
1952 if (CONSTANT_ADDRESS_P (y))
1953 return 1;
1954
1955 /* Adjusting an offsettable address involves changing to a narrower mode.
1956 Make sure that's OK. */
1957
1958 if (mode_dependent_address_p (y, as))
1959 return 0;
1960
1961 machine_mode address_mode = GET_MODE (y);
1962 if (address_mode == VOIDmode)
1963 address_mode = targetm.addr_space.address_mode (as);
1964#ifdef POINTERS_EXTEND_UNSIGNED
1965 machine_mode pointer_mode = targetm.addr_space.pointer_mode (as);
1966#endif
1967
1968 /* ??? How much offset does an offsettable BLKmode reference need?
1969 Clearly that depends on the situation in which it's being used.
1970 However, the current situation in which we test 0xffffffff is
1971 less than ideal. Caveat user. */
1972 if (mode_sz == 0)
1973 mode_sz = BIGGEST_ALIGNMENT / BITS_PER_UNIT;
1974
1975 /* If the expression contains a constant term,
1976 see if it remains valid when max possible offset is added. */
1977
1978 if ((ycode == PLUS) && (y2 = find_constant_term_loc (&y1)))
1979 {
1980 int good;
1981
1982 y1 = *y2;
1983 *y2 = plus_constant (address_mode, *y2, mode_sz - 1);
1984 /* Use QImode because an odd displacement may be automatically invalid
1985 for any wider mode. But it should be valid for a single byte. */
1986 good = (*addressp) (QImode, y, as);
1987
1988 /* In any case, restore old contents of memory. */
1989 *y2 = y1;
1990 return good;
1991 }
1992
1993 if (GET_RTX_CLASS (ycode) == RTX_AUTOINC)
1994 return 0;
1995
1996 /* The offset added here is chosen as the maximum offset that
1997 any instruction could need to add when operating on something
1998 of the specified mode. We assume that if Y and Y+c are
1999 valid addresses then so is Y+d for all 0<d<c. adjust_address will
2000 go inside a LO_SUM here, so we do so as well. */
2001 if (GET_CODE (y) == LO_SUM
2002 && mode != BLKmode
2003 && mode_sz <= GET_MODE_ALIGNMENT (mode) / BITS_PER_UNIT)
2004 z = gen_rtx_LO_SUM (address_mode, XEXP (y, 0),
2005 plus_constant (address_mode, XEXP (y, 1),
2006 mode_sz - 1));
2007#ifdef POINTERS_EXTEND_UNSIGNED
2008 /* Likewise for a ZERO_EXTEND from pointer_mode. */
2009 else if (POINTERS_EXTEND_UNSIGNED > 0
2010 && GET_CODE (y) == ZERO_EXTEND
2011 && GET_MODE (XEXP (y, 0)) == pointer_mode)
2012 z = gen_rtx_ZERO_EXTEND (address_mode,
2013 plus_constant (pointer_mode, XEXP (y, 0),
2014 mode_sz - 1));
2015#endif
2016 else
2017 z = plus_constant (address_mode, y, mode_sz - 1);
2018
2019 /* Use QImode because an odd displacement may be automatically invalid
2020 for any wider mode. But it should be valid for a single byte. */
2021 return (*addressp) (QImode, z, as);
2022}
2023
2024/* Return 1 if ADDR is an address-expression whose effect depends
2025 on the mode of the memory reference it is used in.
2026
2027 ADDRSPACE is the address space associated with the address.
2028
2029 Autoincrement addressing is a typical example of mode-dependence
2030 because the amount of the increment depends on the mode. */
2031
2032bool
2033mode_dependent_address_p (rtx addr, addr_space_t addrspace)
2034{
2035 /* Auto-increment addressing with anything other than post_modify
2036 or pre_modify always introduces a mode dependency. Catch such
2037 cases now instead of deferring to the target. */
2038 if (GET_CODE (addr) == PRE_INC
2039 || GET_CODE (addr) == POST_INC
2040 || GET_CODE (addr) == PRE_DEC
2041 || GET_CODE (addr) == POST_DEC)
2042 return true;
2043
2044 return targetm.mode_dependent_address_p (addr, addrspace);
2045}
2046
2047/* Return true if boolean attribute ATTR is supported. */
2048
2049static bool
2050have_bool_attr (bool_attr attr)
2051{
2052 switch (attr)
2053 {
2054 case BA_ENABLED:
2055 return HAVE_ATTR_enabled;
2056 case BA_PREFERRED_FOR_SIZE:
2057 return HAVE_ATTR_enabled || HAVE_ATTR_preferred_for_size;
2058 case BA_PREFERRED_FOR_SPEED:
2059 return HAVE_ATTR_enabled || HAVE_ATTR_preferred_for_speed;
2060 }
2061 gcc_unreachable ();
2062}
2063
2064/* Return the value of ATTR for instruction INSN. */
2065
2066static bool
2067get_bool_attr (rtx_insn *insn, bool_attr attr)
2068{
2069 switch (attr)
2070 {
2071 case BA_ENABLED:
2072 return get_attr_enabled (insn);
2073 case BA_PREFERRED_FOR_SIZE:
2074 return get_attr_enabled (insn) && get_attr_preferred_for_size (insn);
2075 case BA_PREFERRED_FOR_SPEED:
2076 return get_attr_enabled (insn) && get_attr_preferred_for_speed (insn);
2077 }
2078 gcc_unreachable ();
2079}
2080
2081/* Like get_bool_attr_mask, but don't use the cache. */
2082
2083static alternative_mask
2084get_bool_attr_mask_uncached (rtx_insn *insn, bool_attr attr)
2085{
2086 /* Temporarily install enough information for get_attr_<foo> to assume
2087 that the insn operands are already cached. As above, the attribute
2088 mustn't depend on the values of operands, so we don't provide their
2089 real values here. */
2090 rtx_insn *old_insn = recog_data.insn;
2091 int old_alternative = which_alternative;
2092
2093 recog_data.insn = insn;
2094 alternative_mask mask = ALL_ALTERNATIVES;
2095 int n_alternatives = insn_data[INSN_CODE (insn)].n_alternatives;
2096 for (int i = 0; i < n_alternatives; i++)
2097 {
2098 which_alternative = i;
2099 if (!get_bool_attr (insn, attr))
2100 mask &= ~ALTERNATIVE_BIT (i);
2101 }
2102
2103 recog_data.insn = old_insn;
2104 which_alternative = old_alternative;
2105 return mask;
2106}
2107
2108/* Return the mask of operand alternatives that are allowed for INSN
2109 by boolean attribute ATTR. This mask depends only on INSN and on
2110 the current target; it does not depend on things like the values of
2111 operands. */
2112
2113static alternative_mask
2114get_bool_attr_mask (rtx_insn *insn, bool_attr attr)
2115{
2116 /* Quick exit for asms and for targets that don't use these attributes. */
2117 int code = INSN_CODE (insn);
2118 if (code < 0 || !have_bool_attr (attr))
2119 return ALL_ALTERNATIVES;
2120
2121 /* Calling get_attr_<foo> can be expensive, so cache the mask
2122 for speed. */
2123 if (!this_target_recog->x_bool_attr_masks[code][attr])
2124 this_target_recog->x_bool_attr_masks[code][attr]
2125 = get_bool_attr_mask_uncached (insn, attr);
2126 return this_target_recog->x_bool_attr_masks[code][attr];
2127}
2128
2129/* Return the set of alternatives of INSN that are allowed by the current
2130 target. */
2131
2132alternative_mask
2133get_enabled_alternatives (rtx_insn *insn)
2134{
2135 return get_bool_attr_mask (insn, BA_ENABLED);
2136}
2137
2138/* Return the set of alternatives of INSN that are allowed by the current
2139 target and are preferred for the current size/speed optimization
2140 choice. */
2141
2142alternative_mask
2143get_preferred_alternatives (rtx_insn *insn)
2144{
2145 if (optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)))
2146 return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SPEED);
2147 else
2148 return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SIZE);
2149}
2150
2151/* Return the set of alternatives of INSN that are allowed by the current
2152 target and are preferred for the size/speed optimization choice
2153 associated with BB. Passing a separate BB is useful if INSN has not
2154 been emitted yet or if we are considering moving it to a different
2155 block. */
2156
2157alternative_mask
2158get_preferred_alternatives (rtx_insn *insn, basic_block bb)
2159{
2160 if (optimize_bb_for_speed_p (bb))
2161 return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SPEED);
2162 else
2163 return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SIZE);
2164}
2165
2166/* Assert that the cached boolean attributes for INSN are still accurate.
2167 The backend is required to define these attributes in a way that only
2168 depends on the current target (rather than operands, compiler phase,
2169 etc.). */
2170
2171bool
2172check_bool_attrs (rtx_insn *insn)
2173{
2174 int code = INSN_CODE (insn);
2175 if (code >= 0)
2176 for (int i = 0; i <= BA_LAST; ++i)
2177 {
2178 enum bool_attr attr = (enum bool_attr) i;
2179 if (this_target_recog->x_bool_attr_masks[code][attr])
2180 gcc_assert (this_target_recog->x_bool_attr_masks[code][attr]
2181 == get_bool_attr_mask_uncached (insn, attr));
2182 }
2183 return true;
2184}
2185
2186/* Like extract_insn, but save insn extracted and don't extract again, when
2187 called again for the same insn expecting that recog_data still contain the
2188 valid information. This is used primary by gen_attr infrastructure that
2189 often does extract insn again and again. */
2190void
2191extract_insn_cached (rtx_insn *insn)
2192{
2193 if (recog_data.insn == insn && INSN_CODE (insn) >= 0)
2194 return;
2195 extract_insn (insn);
2196 recog_data.insn = insn;
2197}
2198
2199/* Do uncached extract_insn, constrain_operands and complain about failures.
2200 This should be used when extracting a pre-existing constrained instruction
2201 if the caller wants to know which alternative was chosen. */
2202void
2203extract_constrain_insn (rtx_insn *insn)
2204{
2205 extract_insn (insn);
2206 if (!constrain_operands (reload_completed, get_enabled_alternatives (insn)))
2207 fatal_insn_not_found (insn);
2208}
2209
2210/* Do cached extract_insn, constrain_operands and complain about failures.
2211 Used by insn_attrtab. */
2212void
2213extract_constrain_insn_cached (rtx_insn *insn)
2214{
2215 extract_insn_cached (insn);
2216 if (which_alternative == -1
2217 && !constrain_operands (reload_completed,
2218 get_enabled_alternatives (insn)))
2219 fatal_insn_not_found (insn);
2220}
2221
2222/* Do cached constrain_operands on INSN and complain about failures. */
2223int
2224constrain_operands_cached (rtx_insn *insn, int strict)
2225{
2226 if (which_alternative == -1)
2227 return constrain_operands (strict, get_enabled_alternatives (insn));
2228 else
2229 return 1;
2230}
2231
2232/* Analyze INSN and fill in recog_data. */
2233
2234void
2235extract_insn (rtx_insn *insn)
2236{
2237 int i;
2238 int icode;
2239 int noperands;
2240 rtx body = PATTERN (insn);
2241
2242 recog_data.n_operands = 0;
2243 recog_data.n_alternatives = 0;
2244 recog_data.n_dups = 0;
2245 recog_data.is_asm = false;
2246
2247 switch (GET_CODE (body))
2248 {
2249 case USE:
2250 case CLOBBER:
2251 case ASM_INPUT:
2252 case ADDR_VEC:
2253 case ADDR_DIFF_VEC:
2254 case VAR_LOCATION:
2255 case DEBUG_MARKER:
2256 return;
2257
2258 case SET:
2259 if (GET_CODE (SET_SRC (body)) == ASM_OPERANDS)
2260 goto asm_insn;
2261 else
2262 goto normal_insn;
2263 case PARALLEL:
2264 if ((GET_CODE (XVECEXP (body, 0, 0)) == SET
2265 && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS)
2266 || GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS
2267 || GET_CODE (XVECEXP (body, 0, 0)) == ASM_INPUT)
2268 goto asm_insn;
2269 else
2270 goto normal_insn;
2271 case ASM_OPERANDS:
2272 asm_insn:
2273 recog_data.n_operands = noperands = asm_noperands (body);
2274 if (noperands >= 0)
2275 {
2276 /* This insn is an `asm' with operands. */
2277
2278 /* expand_asm_operands makes sure there aren't too many operands. */
2279 gcc_assert (noperands <= MAX_RECOG_OPERANDS);
2280
2281 /* Now get the operand values and constraints out of the insn. */
2282 decode_asm_operands (body, recog_data.operand,
2283 recog_data.operand_loc,
2284 recog_data.constraints,
2285 recog_data.operand_mode, NULL);
2286 memset (recog_data.is_operator, 0, sizeof recog_data.is_operator);
2287 if (noperands > 0)
2288 {
2289 const char *p = recog_data.constraints[0];
2290 recog_data.n_alternatives = 1;
2291 while (*p)
2292 recog_data.n_alternatives += (*p++ == ',');
2293 }
2294 recog_data.is_asm = true;
2295 break;
2296 }
2297 fatal_insn_not_found (insn);
2298
2299 default:
2300 normal_insn:
2301 /* Ordinary insn: recognize it, get the operands via insn_extract
2302 and get the constraints. */
2303
2304 icode = recog_memoized (insn);
2305 if (icode < 0)
2306 fatal_insn_not_found (insn);
2307
2308 recog_data.n_operands = noperands = insn_data[icode].n_operands;
2309 recog_data.n_alternatives = insn_data[icode].n_alternatives;
2310 recog_data.n_dups = insn_data[icode].n_dups;
2311
2312 insn_extract (insn);
2313
2314 for (i = 0; i < noperands; i++)
2315 {
2316 recog_data.constraints[i] = insn_data[icode].operand[i].constraint;
2317 recog_data.is_operator[i] = insn_data[icode].operand[i].is_operator;
2318 recog_data.operand_mode[i] = insn_data[icode].operand[i].mode;
2319 /* VOIDmode match_operands gets mode from their real operand. */
2320 if (recog_data.operand_mode[i] == VOIDmode)
2321 recog_data.operand_mode[i] = GET_MODE (recog_data.operand[i]);
2322 }
2323 }
2324 for (i = 0; i < noperands; i++)
2325 recog_data.operand_type[i]
2326 = (recog_data.constraints[i][0] == '=' ? OP_OUT
2327 : recog_data.constraints[i][0] == '+' ? OP_INOUT
2328 : OP_IN);
2329
2330 gcc_assert (recog_data.n_alternatives <= MAX_RECOG_ALTERNATIVES);
2331
2332 recog_data.insn = NULL;
2333 which_alternative = -1;
2334}
2335
2336/* Fill in OP_ALT_BASE for an instruction that has N_OPERANDS operands,
2337 N_ALTERNATIVES alternatives and constraint strings CONSTRAINTS.
2338 OP_ALT_BASE has N_ALTERNATIVES * N_OPERANDS entries and CONSTRAINTS
2339 has N_OPERANDS entries. */
2340
2341void
2342preprocess_constraints (int n_operands, int n_alternatives,
2343 const char **constraints,
2344 operand_alternative *op_alt_base)
2345{
2346 for (int i = 0; i < n_operands; i++)
2347 {
2348 int j;
2349 struct operand_alternative *op_alt;
2350 const char *p = constraints[i];
2351
2352 op_alt = op_alt_base;
2353
2354 for (j = 0; j < n_alternatives; j++, op_alt += n_operands)
2355 {
2356 op_alt[i].cl = NO_REGS;
2357 op_alt[i].constraint = p;
2358 op_alt[i].matches = -1;
2359 op_alt[i].matched = -1;
2360
2361 if (*p == '\0' || *p == ',')
2362 {
2363 op_alt[i].anything_ok = 1;
2364 continue;
2365 }
2366
2367 for (;;)
2368 {
2369 char c = *p;
2370 if (c == '#')
2371 do
2372 c = *++p;
2373 while (c != ',' && c != '\0');
2374 if (c == ',' || c == '\0')
2375 {
2376 p++;
2377 break;
2378 }
2379
2380 switch (c)
2381 {
2382 case '?':
2383 op_alt[i].reject += 6;
2384 break;
2385 case '!':
2386 op_alt[i].reject += 600;
2387 break;
2388 case '&':
2389 op_alt[i].earlyclobber = 1;
2390 break;
2391
2392 case '0': case '1': case '2': case '3': case '4':
2393 case '5': case '6': case '7': case '8': case '9':
2394 {
2395 char *end;
2396 op_alt[i].matches = strtoul (p, &end, 10);
2397 op_alt[op_alt[i].matches].matched = i;
2398 p = end;
2399 }
2400 continue;
2401
2402 case 'X':
2403 op_alt[i].anything_ok = 1;
2404 break;
2405
2406 case 'g':
2407 op_alt[i].cl =
2408 reg_class_subunion[(int) op_alt[i].cl][(int) GENERAL_REGS];
2409 break;
2410
2411 default:
2412 enum constraint_num cn = lookup_constraint (p);
2413 enum reg_class cl;
2414 switch (get_constraint_type (cn))
2415 {
2416 case CT_REGISTER:
2417 cl = reg_class_for_constraint (cn);
2418 if (cl != NO_REGS)
2419 op_alt[i].cl = reg_class_subunion[op_alt[i].cl][cl];
2420 break;
2421
2422 case CT_CONST_INT:
2423 break;
2424
2425 case CT_MEMORY:
2426 case CT_SPECIAL_MEMORY:
2427 op_alt[i].memory_ok = 1;
2428 break;
2429
2430 case CT_ADDRESS:
2431 op_alt[i].is_address = 1;
2432 op_alt[i].cl
2433 = (reg_class_subunion
2434 [(int) op_alt[i].cl]
2435 [(int) base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
2436 ADDRESS, SCRATCH)]);
2437 break;
2438
2439 case CT_FIXED_FORM:
2440 break;
2441 }
2442 break;
2443 }
2444 p += CONSTRAINT_LEN (c, p);
2445 }
2446 }
2447 }
2448}
2449
2450/* Return an array of operand_alternative instructions for
2451 instruction ICODE. */
2452
2453const operand_alternative *
2454preprocess_insn_constraints (unsigned int icode)
2455{
2456 gcc_checking_assert (IN_RANGE (icode, 0, NUM_INSN_CODES - 1));
2457 if (this_target_recog->x_op_alt[icode])
2458 return this_target_recog->x_op_alt[icode];
2459
2460 int n_operands = insn_data[icode].n_operands;
2461 if (n_operands == 0)
2462 return 0;
2463 /* Always provide at least one alternative so that which_op_alt ()
2464 works correctly. If the instruction has 0 alternatives (i.e. all
2465 constraint strings are empty) then each operand in this alternative
2466 will have anything_ok set. */
2467 int n_alternatives = MAX (insn_data[icode].n_alternatives, 1);
2468 int n_entries = n_operands * n_alternatives;
2469
2470 operand_alternative *op_alt = XCNEWVEC (operand_alternative, n_entries);
2471 const char **constraints = XALLOCAVEC (const char *, n_operands);
2472
2473 for (int i = 0; i < n_operands; ++i)
2474 constraints[i] = insn_data[icode].operand[i].constraint;
2475 preprocess_constraints (n_operands, n_alternatives, constraints, op_alt);
2476
2477 this_target_recog->x_op_alt[icode] = op_alt;
2478 return op_alt;
2479}
2480
2481/* After calling extract_insn, you can use this function to extract some
2482 information from the constraint strings into a more usable form.
2483 The collected data is stored in recog_op_alt. */
2484
2485void
2486preprocess_constraints (rtx_insn *insn)
2487{
2488 int icode = INSN_CODE (insn);
2489 if (icode >= 0)
2490 recog_op_alt = preprocess_insn_constraints (icode);
2491 else
2492 {
2493 int n_operands = recog_data.n_operands;
2494 int n_alternatives = recog_data.n_alternatives;
2495 int n_entries = n_operands * n_alternatives;
2496 memset (asm_op_alt, 0, n_entries * sizeof (operand_alternative));
2497 preprocess_constraints (n_operands, n_alternatives,
2498 recog_data.constraints, asm_op_alt);
2499 recog_op_alt = asm_op_alt;
2500 }
2501}
2502
2503/* Check the operands of an insn against the insn's operand constraints
2504 and return 1 if they match any of the alternatives in ALTERNATIVES.
2505
2506 The information about the insn's operands, constraints, operand modes
2507 etc. is obtained from the global variables set up by extract_insn.
2508
2509 WHICH_ALTERNATIVE is set to a number which indicates which
2510 alternative of constraints was matched: 0 for the first alternative,
2511 1 for the next, etc.
2512
2513 In addition, when two operands are required to match
2514 and it happens that the output operand is (reg) while the
2515 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2516 make the output operand look like the input.
2517 This is because the output operand is the one the template will print.
2518
2519 This is used in final, just before printing the assembler code and by
2520 the routines that determine an insn's attribute.
2521
2522 If STRICT is a positive nonzero value, it means that we have been
2523 called after reload has been completed. In that case, we must
2524 do all checks strictly. If it is zero, it means that we have been called
2525 before reload has completed. In that case, we first try to see if we can
2526 find an alternative that matches strictly. If not, we try again, this
2527 time assuming that reload will fix up the insn. This provides a "best
2528 guess" for the alternative and is used to compute attributes of insns prior
2529 to reload. A negative value of STRICT is used for this internal call. */
2530
2531struct funny_match
2532{
2533 int this_op, other;
2534};
2535
2536int
2537constrain_operands (int strict, alternative_mask alternatives)
2538{
2539 const char *constraints[MAX_RECOG_OPERANDS];
2540 int matching_operands[MAX_RECOG_OPERANDS];
2541 int earlyclobber[MAX_RECOG_OPERANDS];
2542 int c;
2543
2544 struct funny_match funny_match[MAX_RECOG_OPERANDS];
2545 int funny_match_index;
2546
2547 which_alternative = 0;
2548 if (recog_data.n_operands == 0 || recog_data.n_alternatives == 0)
2549 return 1;
2550
2551 for (c = 0; c < recog_data.n_operands; c++)
2552 {
2553 constraints[c] = recog_data.constraints[c];
2554 matching_operands[c] = -1;
2555 }
2556
2557 do
2558 {
2559 int seen_earlyclobber_at = -1;
2560 int opno;
2561 int lose = 0;
2562 funny_match_index = 0;
2563
2564 if (!TEST_BIT (alternatives, which_alternative))
2565 {
2566 int i;
2567
2568 for (i = 0; i < recog_data.n_operands; i++)
2569 constraints[i] = skip_alternative (constraints[i]);
2570
2571 which_alternative++;
2572 continue;
2573 }
2574
2575 for (opno = 0; opno < recog_data.n_operands; opno++)
2576 {
2577 rtx op = recog_data.operand[opno];
2578 machine_mode mode = GET_MODE (op);
2579 const char *p = constraints[opno];
2580 int offset = 0;
2581 int win = 0;
2582 int val;
2583 int len;
2584
2585 earlyclobber[opno] = 0;
2586
2587 /* A unary operator may be accepted by the predicate, but it
2588 is irrelevant for matching constraints. */
2589 if (UNARY_P (op))
2590 op = XEXP (op, 0);
2591
2592 if (GET_CODE (op) == SUBREG)
2593 {
2594 if (REG_P (SUBREG_REG (op))
2595 && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER)
2596 offset = subreg_regno_offset (REGNO (SUBREG_REG (op)),
2597 GET_MODE (SUBREG_REG (op)),
2598 SUBREG_BYTE (op),
2599 GET_MODE (op));
2600 op = SUBREG_REG (op);
2601 }
2602
2603 /* An empty constraint or empty alternative
2604 allows anything which matched the pattern. */
2605 if (*p == 0 || *p == ',')
2606 win = 1;
2607
2608 do
2609 switch (c = *p, len = CONSTRAINT_LEN (c, p), c)
2610 {
2611 case '\0':
2612 len = 0;
2613 break;
2614 case ',':
2615 c = '\0';
2616 break;
2617
2618 case '#':
2619 /* Ignore rest of this alternative as far as
2620 constraint checking is concerned. */
2621 do
2622 p++;
2623 while (*p && *p != ',');
2624 len = 0;
2625 break;
2626
2627 case '&':
2628 earlyclobber[opno] = 1;
2629 if (seen_earlyclobber_at < 0)
2630 seen_earlyclobber_at = opno;
2631 break;
2632
2633 case '0': case '1': case '2': case '3': case '4':
2634 case '5': case '6': case '7': case '8': case '9':
2635 {
2636 /* This operand must be the same as a previous one.
2637 This kind of constraint is used for instructions such
2638 as add when they take only two operands.
2639
2640 Note that the lower-numbered operand is passed first.
2641
2642 If we are not testing strictly, assume that this
2643 constraint will be satisfied. */
2644
2645 char *end;
2646 int match;
2647
2648 match = strtoul (p, &end, 10);
2649 p = end;
2650
2651 if (strict < 0)
2652 val = 1;
2653 else
2654 {
2655 rtx op1 = recog_data.operand[match];
2656 rtx op2 = recog_data.operand[opno];
2657
2658 /* A unary operator may be accepted by the predicate,
2659 but it is irrelevant for matching constraints. */
2660 if (UNARY_P (op1))
2661 op1 = XEXP (op1, 0);
2662 if (UNARY_P (op2))
2663 op2 = XEXP (op2, 0);
2664
2665 val = operands_match_p (op1, op2);
2666 }
2667
2668 matching_operands[opno] = match;
2669 matching_operands[match] = opno;
2670
2671 if (val != 0)
2672 win = 1;
2673
2674 /* If output is *x and input is *--x, arrange later
2675 to change the output to *--x as well, since the
2676 output op is the one that will be printed. */
2677 if (val == 2 && strict > 0)
2678 {
2679 funny_match[funny_match_index].this_op = opno;
2680 funny_match[funny_match_index++].other = match;
2681 }
2682 }
2683 len = 0;
2684 break;
2685
2686 case 'p':
2687 /* p is used for address_operands. When we are called by
2688 gen_reload, no one will have checked that the address is
2689 strictly valid, i.e., that all pseudos requiring hard regs
2690 have gotten them. */
2691 if (strict <= 0
2692 || (strict_memory_address_p (recog_data.operand_mode[opno],
2693 op)))
2694 win = 1;
2695 break;
2696
2697 /* No need to check general_operand again;
2698 it was done in insn-recog.c. Well, except that reload
2699 doesn't check the validity of its replacements, but
2700 that should only matter when there's a bug. */
2701 case 'g':
2702 /* Anything goes unless it is a REG and really has a hard reg
2703 but the hard reg is not in the class GENERAL_REGS. */
2704 if (REG_P (op))
2705 {
2706 if (strict < 0
2707 || GENERAL_REGS == ALL_REGS
2708 || (reload_in_progress
2709 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2710 || reg_fits_class_p (op, GENERAL_REGS, offset, mode))
2711 win = 1;
2712 }
2713 else if (strict < 0 || general_operand (op, mode))
2714 win = 1;
2715 break;
2716
2717 default:
2718 {
2719 enum constraint_num cn = lookup_constraint (p);
2720 enum reg_class cl = reg_class_for_constraint (cn);
2721 if (cl != NO_REGS)
2722 {
2723 if (strict < 0
2724 || (strict == 0
2725 && REG_P (op)
2726 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2727 || (strict == 0 && GET_CODE (op) == SCRATCH)
2728 || (REG_P (op)
2729 && reg_fits_class_p (op, cl, offset, mode)))
2730 win = 1;
2731 }
2732
2733 else if (constraint_satisfied_p (op, cn))
2734 win = 1;
2735
2736 else if (insn_extra_memory_constraint (cn)
2737 /* Every memory operand can be reloaded to fit. */
2738 && ((strict < 0 && MEM_P (op))
2739 /* Before reload, accept what reload can turn
2740 into a mem. */
2741 || (strict < 0 && CONSTANT_P (op))
2742 /* Before reload, accept a pseudo,
2743 since LRA can turn it into a mem. */
2744 || (strict < 0 && targetm.lra_p () && REG_P (op)
2745 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2746 /* During reload, accept a pseudo */
2747 || (reload_in_progress && REG_P (op)
2748 && REGNO (op) >= FIRST_PSEUDO_REGISTER)))
2749 win = 1;
2750 else if (insn_extra_address_constraint (cn)
2751 /* Every address operand can be reloaded to fit. */
2752 && strict < 0)
2753 win = 1;
2754 /* Cater to architectures like IA-64 that define extra memory
2755 constraints without using define_memory_constraint. */
2756 else if (reload_in_progress
2757 && REG_P (op)
2758 && REGNO (op) >= FIRST_PSEUDO_REGISTER
2759 && reg_renumber[REGNO (op)] < 0
2760 && reg_equiv_mem (REGNO (op)) != 0
2761 && constraint_satisfied_p
2762 (reg_equiv_mem (REGNO (op)), cn))
2763 win = 1;
2764 break;
2765 }
2766 }
2767 while (p += len, c);
2768
2769 constraints[opno] = p;
2770 /* If this operand did not win somehow,
2771 this alternative loses. */
2772 if (! win)
2773 lose = 1;
2774 }
2775 /* This alternative won; the operands are ok.
2776 Change whichever operands this alternative says to change. */
2777 if (! lose)
2778 {
2779 int opno, eopno;
2780
2781 /* See if any earlyclobber operand conflicts with some other
2782 operand. */
2783
2784 if (strict > 0 && seen_earlyclobber_at >= 0)
2785 for (eopno = seen_earlyclobber_at;
2786 eopno < recog_data.n_operands;
2787 eopno++)
2788 /* Ignore earlyclobber operands now in memory,
2789 because we would often report failure when we have
2790 two memory operands, one of which was formerly a REG. */
2791 if (earlyclobber[eopno]
2792 && REG_P (recog_data.operand[eopno]))
2793 for (opno = 0; opno < recog_data.n_operands; opno++)
2794 if ((MEM_P (recog_data.operand[opno])
2795 || recog_data.operand_type[opno] != OP_OUT)
2796 && opno != eopno
2797 /* Ignore things like match_operator operands. */
2798 && *recog_data.constraints[opno] != 0
2799 && ! (matching_operands[opno] == eopno
2800 && operands_match_p (recog_data.operand[opno],
2801 recog_data.operand[eopno]))
2802 && ! safe_from_earlyclobber (recog_data.operand[opno],
2803 recog_data.operand[eopno]))
2804 lose = 1;
2805
2806 if (! lose)
2807 {
2808 while (--funny_match_index >= 0)
2809 {
2810 recog_data.operand[funny_match[funny_match_index].other]
2811 = recog_data.operand[funny_match[funny_match_index].this_op];
2812 }
2813
2814 /* For operands without < or > constraints reject side-effects. */
2815 if (AUTO_INC_DEC && recog_data.is_asm)
2816 {
2817 for (opno = 0; opno < recog_data.n_operands; opno++)
2818 if (MEM_P (recog_data.operand[opno]))
2819 switch (GET_CODE (XEXP (recog_data.operand[opno], 0)))
2820 {
2821 case PRE_INC:
2822 case POST_INC:
2823 case PRE_DEC:
2824 case POST_DEC:
2825 case PRE_MODIFY:
2826 case POST_MODIFY:
2827 if (strchr (recog_data.constraints[opno], '<') == NULL
2828 && strchr (recog_data.constraints[opno], '>')
2829 == NULL)
2830 return 0;
2831 break;
2832 default:
2833 break;
2834 }
2835 }
2836
2837 return 1;
2838 }
2839 }
2840
2841 which_alternative++;
2842 }
2843 while (which_alternative < recog_data.n_alternatives);
2844
2845 which_alternative = -1;
2846 /* If we are about to reject this, but we are not to test strictly,
2847 try a very loose test. Only return failure if it fails also. */
2848 if (strict == 0)
2849 return constrain_operands (-1, alternatives);
2850 else
2851 return 0;
2852}
2853
2854/* Return true iff OPERAND (assumed to be a REG rtx)
2855 is a hard reg in class CLASS when its regno is offset by OFFSET
2856 and changed to mode MODE.
2857 If REG occupies multiple hard regs, all of them must be in CLASS. */
2858
2859bool
2860reg_fits_class_p (const_rtx operand, reg_class_t cl, int offset,
2861 machine_mode mode)
2862{
2863 unsigned int regno = REGNO (operand);
2864
2865 if (cl == NO_REGS)
2866 return false;
2867
2868 /* Regno must not be a pseudo register. Offset may be negative. */
2869 return (HARD_REGISTER_NUM_P (regno)
2870 && HARD_REGISTER_NUM_P (regno + offset)
2871 && in_hard_reg_set_p (reg_class_contents[(int) cl], mode,
2872 regno + offset));
2873}
2874
2875/* Split single instruction. Helper function for split_all_insns and
2876 split_all_insns_noflow. Return last insn in the sequence if successful,
2877 or NULL if unsuccessful. */
2878
2879static rtx_insn *
2880split_insn (rtx_insn *insn)
2881{
2882 /* Split insns here to get max fine-grain parallelism. */
2883 rtx_insn *first = PREV_INSN (insn);
2884 rtx_insn *last = try_split (PATTERN (insn), insn, 1);
2885 rtx insn_set, last_set, note;
2886
2887 if (last == insn)
2888 return NULL;
2889
2890 /* If the original instruction was a single set that was known to be
2891 equivalent to a constant, see if we can say the same about the last
2892 instruction in the split sequence. The two instructions must set
2893 the same destination. */
2894 insn_set = single_set (insn);
2895 if (insn_set)
2896 {
2897 last_set = single_set (last);
2898 if (last_set && rtx_equal_p (SET_DEST (last_set), SET_DEST (insn_set)))
2899 {
2900 note = find_reg_equal_equiv_note (insn);
2901 if (note && CONSTANT_P (XEXP (note, 0)))
2902 set_unique_reg_note (last, REG_EQUAL, XEXP (note, 0));
2903 else if (CONSTANT_P (SET_SRC (insn_set)))
2904 set_unique_reg_note (last, REG_EQUAL,
2905 copy_rtx (SET_SRC (insn_set)));
2906 }
2907 }
2908
2909 /* try_split returns the NOTE that INSN became. */
2910 SET_INSN_DELETED (insn);
2911
2912 /* ??? Coddle to md files that generate subregs in post-reload
2913 splitters instead of computing the proper hard register. */
2914 if (reload_completed && first != last)
2915 {
2916 first = NEXT_INSN (first);
2917 for (;;)
2918 {
2919 if (INSN_P (first))
2920 cleanup_subreg_operands (first);
2921 if (first == last)
2922 break;
2923 first = NEXT_INSN (first);
2924 }
2925 }
2926
2927 return last;
2928}
2929
2930/* Split all insns in the function. If UPD_LIFE, update life info after. */
2931
2932void
2933split_all_insns (void)
2934{
2935 bool changed;
2936 basic_block bb;
2937
2938 auto_sbitmap blocks (last_basic_block_for_fn (cfun));
2939 bitmap_clear (blocks);
2940 changed = false;
2941
2942 FOR_EACH_BB_REVERSE_FN (bb, cfun)
2943 {
2944 rtx_insn *insn, *next;
2945 bool finish = false;
2946
2947 rtl_profile_for_bb (bb);
2948 for (insn = BB_HEAD (bb); !finish ; insn = next)
2949 {
2950 /* Can't use `next_real_insn' because that might go across
2951 CODE_LABELS and short-out basic blocks. */
2952 next = NEXT_INSN (insn);
2953 finish = (insn == BB_END (bb));
2954 if (INSN_P (insn))
2955 {
2956 rtx set = single_set (insn);
2957
2958 /* Don't split no-op move insns. These should silently
2959 disappear later in final. Splitting such insns would
2960 break the code that handles LIBCALL blocks. */
2961 if (set && set_noop_p (set))
2962 {
2963 /* Nops get in the way while scheduling, so delete them
2964 now if register allocation has already been done. It
2965 is too risky to try to do this before register
2966 allocation, and there are unlikely to be very many
2967 nops then anyways. */
2968 if (reload_completed)
2969 delete_insn_and_edges (insn);
2970 }
2971 else
2972 {
2973 if (split_insn (insn))
2974 {
2975 bitmap_set_bit (blocks, bb->index);
2976 changed = true;
2977 }
2978 }
2979 }
2980 }
2981 }
2982
2983 default_rtl_profile ();
2984 if (changed)
2985 find_many_sub_basic_blocks (blocks);
2986
2987 checking_verify_flow_info ();
2988}
2989
2990/* Same as split_all_insns, but do not expect CFG to be available.
2991 Used by machine dependent reorg passes. */
2992
2993unsigned int
2994split_all_insns_noflow (void)
2995{
2996 rtx_insn *next, *insn;
2997
2998 for (insn = get_insns (); insn; insn = next)
2999 {
3000 next = NEXT_INSN (insn);
3001 if (INSN_P (insn))
3002 {
3003 /* Don't split no-op move insns. These should silently
3004 disappear later in final. Splitting such insns would
3005 break the code that handles LIBCALL blocks. */
3006 rtx set = single_set (insn);
3007 if (set && set_noop_p (set))
3008 {
3009 /* Nops get in the way while scheduling, so delete them
3010 now if register allocation has already been done. It
3011 is too risky to try to do this before register
3012 allocation, and there are unlikely to be very many
3013 nops then anyways.
3014
3015 ??? Should we use delete_insn when the CFG isn't valid? */
3016 if (reload_completed)
3017 delete_insn_and_edges (insn);
3018 }
3019 else
3020 split_insn (insn);
3021 }
3022 }
3023 return 0;
3024}
3025
3026struct peep2_insn_data
3027{
3028 rtx_insn *insn;
3029 regset live_before;
3030};
3031
3032static struct peep2_insn_data peep2_insn_data[MAX_INSNS_PER_PEEP2 + 1];
3033static int peep2_current;
3034
3035static bool peep2_do_rebuild_jump_labels;
3036static bool peep2_do_cleanup_cfg;
3037
3038/* The number of instructions available to match a peep2. */
3039int peep2_current_count;
3040
3041/* A marker indicating the last insn of the block. The live_before regset
3042 for this element is correct, indicating DF_LIVE_OUT for the block. */
3043#define PEEP2_EOB invalid_insn_rtx
3044
3045/* Wrap N to fit into the peep2_insn_data buffer. */
3046
3047static int
3048peep2_buf_position (int n)
3049{
3050 if (n >= MAX_INSNS_PER_PEEP2 + 1)
3051 n -= MAX_INSNS_PER_PEEP2 + 1;
3052 return n;
3053}
3054
3055/* Return the Nth non-note insn after `current', or return NULL_RTX if it
3056 does not exist. Used by the recognizer to find the next insn to match
3057 in a multi-insn pattern. */
3058
3059rtx_insn *
3060peep2_next_insn (int n)
3061{
3062 gcc_assert (n <= peep2_current_count);
3063
3064 n = peep2_buf_position (peep2_current + n);
3065
3066 return peep2_insn_data[n].insn;
3067}
3068
3069/* Return true if REGNO is dead before the Nth non-note insn
3070 after `current'. */
3071
3072int
3073peep2_regno_dead_p (int ofs, int regno)
3074{
3075 gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1);
3076
3077 ofs = peep2_buf_position (peep2_current + ofs);
3078
3079 gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX);
3080
3081 return ! REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno);
3082}
3083
3084/* Similarly for a REG. */
3085
3086int
3087peep2_reg_dead_p (int ofs, rtx reg)
3088{
3089 gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1);
3090
3091 ofs = peep2_buf_position (peep2_current + ofs);
3092
3093 gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX);
3094
3095 unsigned int end_regno = END_REGNO (reg);
3096 for (unsigned int regno = REGNO (reg); regno < end_regno; ++regno)
3097 if (REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno))
3098 return 0;
3099 return 1;
3100}
3101
3102/* Regno offset to be used in the register search. */
3103static int search_ofs;
3104
3105/* Try to find a hard register of mode MODE, matching the register class in
3106 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
3107 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
3108 in which case the only condition is that the register must be available
3109 before CURRENT_INSN.
3110 Registers that already have bits set in REG_SET will not be considered.
3111
3112 If an appropriate register is available, it will be returned and the
3113 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
3114 returned. */
3115
3116rtx
3117peep2_find_free_register (int from, int to, const char *class_str,
3118 machine_mode mode, HARD_REG_SET *reg_set)
3119{
3120 enum reg_class cl;
3121 HARD_REG_SET live;
3122 df_ref def;
3123 int i;
3124
3125 gcc_assert (from < MAX_INSNS_PER_PEEP2 + 1);
3126 gcc_assert (to < MAX_INSNS_PER_PEEP2 + 1);
3127
3128 from = peep2_buf_position (peep2_current + from);
3129 to = peep2_buf_position (peep2_current + to);
3130
3131 gcc_assert (peep2_insn_data[from].insn != NULL_RTX);
3132 REG_SET_TO_HARD_REG_SET (live, peep2_insn_data[from].live_before);
3133
3134 while (from != to)
3135 {
3136 gcc_assert (peep2_insn_data[from].insn != NULL_RTX);
3137
3138 /* Don't use registers set or clobbered by the insn. */
3139 FOR_EACH_INSN_DEF (def, peep2_insn_data[from].insn)
3140 SET_HARD_REG_BIT (live, DF_REF_REGNO (def));
3141
3142 from = peep2_buf_position (from + 1);
3143 }
3144
3145 cl = reg_class_for_constraint (lookup_constraint (class_str));
3146
3147 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3148 {
3149 int raw_regno, regno, success, j;
3150
3151 /* Distribute the free registers as much as possible. */
3152 raw_regno = search_ofs + i;
3153 if (raw_regno >= FIRST_PSEUDO_REGISTER)
3154 raw_regno -= FIRST_PSEUDO_REGISTER;
3155#ifdef REG_ALLOC_ORDER
3156 regno = reg_alloc_order[raw_regno];
3157#else
3158 regno = raw_regno;
3159#endif
3160
3161 /* Can it support the mode we need? */
3162 if (!targetm.hard_regno_mode_ok (regno, mode))
3163 continue;
3164
3165 success = 1;
3166 for (j = 0; success && j < hard_regno_nregs (regno, mode); j++)
3167 {
3168 /* Don't allocate fixed registers. */
3169 if (fixed_regs[regno + j])
3170 {
3171 success = 0;
3172 break;
3173 }
3174 /* Don't allocate global registers. */
3175 if (global_regs[regno + j])
3176 {
3177 success = 0;
3178 break;
3179 }
3180 /* Make sure the register is of the right class. */
3181 if (! TEST_HARD_REG_BIT (reg_class_contents[cl], regno + j))
3182 {
3183 success = 0;
3184 break;
3185 }
3186 /* And that we don't create an extra save/restore. */
3187 if (! call_used_regs[regno + j] && ! df_regs_ever_live_p (regno + j))
3188 {
3189 success = 0;
3190 break;
3191 }
3192
3193 if (! targetm.hard_regno_scratch_ok (regno + j))
3194 {
3195 success = 0;
3196 break;
3197 }
3198
3199 /* And we don't clobber traceback for noreturn functions. */
3200 if ((regno + j == FRAME_POINTER_REGNUM
3201 || regno + j == HARD_FRAME_POINTER_REGNUM)
3202 && (! reload_completed || frame_pointer_needed))
3203 {
3204 success = 0;
3205 break;
3206 }
3207
3208 if (TEST_HARD_REG_BIT (*reg_set, regno + j)
3209 || TEST_HARD_REG_BIT (live, regno + j))
3210 {
3211 success = 0;
3212 break;
3213 }
3214 }
3215
3216 if (success)
3217 {
3218 add_to_hard_reg_set (reg_set, mode, regno);
3219
3220 /* Start the next search with the next register. */
3221 if (++raw_regno >= FIRST_PSEUDO_REGISTER)
3222 raw_regno = 0;
3223 search_ofs = raw_regno;
3224
3225 return gen_rtx_REG (mode, regno);
3226 }
3227 }
3228
3229 search_ofs = 0;
3230 return NULL_RTX;
3231}
3232
3233/* Forget all currently tracked instructions, only remember current
3234 LIVE regset. */
3235
3236static void
3237peep2_reinit_state (regset live)
3238{
3239 int i;
3240
3241 /* Indicate that all slots except the last holds invalid data. */
3242 for (i = 0; i < MAX_INSNS_PER_PEEP2; ++i)
3243 peep2_insn_data[i].insn = NULL;
3244 peep2_current_count = 0;
3245
3246 /* Indicate that the last slot contains live_after data. */
3247 peep2_insn_data[MAX_INSNS_PER_PEEP2].insn = PEEP2_EOB;
3248 peep2_current = MAX_INSNS_PER_PEEP2;
3249
3250 COPY_REG_SET (peep2_insn_data[MAX_INSNS_PER_PEEP2].live_before, live);
3251}
3252
3253/* While scanning basic block BB, we found a match of length MATCH_LEN,
3254 starting at INSN. Perform the replacement, removing the old insns and
3255 replacing them with ATTEMPT. Returns the last insn emitted, or NULL
3256 if the replacement is rejected. */
3257
3258static rtx_insn *
3259peep2_attempt (basic_block bb, rtx_insn *insn, int match_len, rtx_insn *attempt)
3260{
3261 int i;
3262 rtx_insn *last, *before_try, *x;
3263 rtx eh_note, as_note;
3264 rtx_insn *old_insn;
3265 rtx_insn *new_insn;
3266 bool was_call = false;
3267
3268 /* If we are splitting an RTX_FRAME_RELATED_P insn, do not allow it to
3269 match more than one insn, or to be split into more than one insn. */
3270 old_insn = peep2_insn_data[peep2_current].insn;
3271 if (RTX_FRAME_RELATED_P (old_insn))
3272 {
3273 bool any_note = false;
3274 rtx note;
3275
3276 if (match_len != 0)
3277 return NULL;
3278
3279 /* Look for one "active" insn. I.e. ignore any "clobber" insns that
3280 may be in the stream for the purpose of register allocation. */
3281 if (active_insn_p (attempt))
3282 new_insn = attempt;
3283 else
3284 new_insn = next_active_insn (attempt);
3285 if (next_active_insn (new_insn))
3286 return NULL;
3287
3288 /* We have a 1-1 replacement. Copy over any frame-related info. */
3289 RTX_FRAME_RELATED_P (new_insn) = 1;
3290
3291 /* Allow the backend to fill in a note during the split. */
3292 for (note = REG_NOTES (new_insn); note ; note = XEXP (note, 1))
3293 switch (REG_NOTE_KIND (note))
3294 {
3295 case REG_FRAME_RELATED_EXPR:
3296 case REG_CFA_DEF_CFA:
3297 case REG_CFA_ADJUST_CFA:
3298 case REG_CFA_OFFSET:
3299 case REG_CFA_REGISTER:
3300 case REG_CFA_EXPRESSION:
3301 case REG_CFA_RESTORE:
3302 case REG_CFA_SET_VDRAP:
3303 any_note = true;
3304 break;
3305 default:
3306 break;
3307 }
3308
3309 /* If the backend didn't supply a note, copy one over. */
3310 if (!any_note)
3311 for (note = REG_NOTES (old_insn); note ; note = XEXP (note, 1))
3312 switch (REG_NOTE_KIND (note))
3313 {
3314 case REG_FRAME_RELATED_EXPR:
3315 case REG_CFA_DEF_CFA:
3316 case REG_CFA_ADJUST_CFA:
3317 case REG_CFA_OFFSET:
3318 case REG_CFA_REGISTER:
3319 case REG_CFA_EXPRESSION:
3320 case REG_CFA_RESTORE:
3321 case REG_CFA_SET_VDRAP:
3322 add_reg_note (new_insn, REG_NOTE_KIND (note), XEXP (note, 0));
3323 any_note = true;
3324 break;
3325 default:
3326 break;
3327 }
3328
3329 /* If there still isn't a note, make sure the unwind info sees the
3330 same expression as before the split. */
3331 if (!any_note)
3332 {
3333 rtx old_set, new_set;
3334
3335 /* The old insn had better have been simple, or annotated. */
3336 old_set = single_set (old_insn);
3337 gcc_assert (old_set != NULL);
3338
3339 new_set = single_set (new_insn);
3340 if (!new_set || !rtx_equal_p (new_set, old_set))
3341 add_reg_note (new_insn, REG_FRAME_RELATED_EXPR, old_set);
3342 }
3343
3344 /* Copy prologue/epilogue status. This is required in order to keep
3345 proper placement of EPILOGUE_BEG and the DW_CFA_remember_state. */
3346 maybe_copy_prologue_epilogue_insn (old_insn, new_insn);
3347 }
3348
3349 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3350 in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other
3351 cfg-related call notes. */
3352 for (i = 0; i <= match_len; ++i)
3353 {
3354 int j;
3355 rtx note;
3356
3357 j = peep2_buf_position (peep2_current + i);
3358 old_insn = peep2_insn_data[j].insn;
3359 if (!CALL_P (old_insn))
3360 continue;
3361 was_call = true;
3362
3363 new_insn = attempt;
3364 while (new_insn != NULL_RTX)
3365 {
3366 if (CALL_P (new_insn))
3367 break;
3368 new_insn = NEXT_INSN (new_insn);
3369 }
3370
3371 gcc_assert (new_insn != NULL_RTX);
3372
3373 CALL_INSN_FUNCTION_USAGE (new_insn)
3374 = CALL_INSN_FUNCTION_USAGE (old_insn);
3375 SIBLING_CALL_P (new_insn) = SIBLING_CALL_P (old_insn);
3376
3377 for (note = REG_NOTES (old_insn);
3378 note;
3379 note = XEXP (note, 1))
3380 switch (REG_NOTE_KIND (note))
3381 {
3382 case REG_NORETURN:
3383 case REG_SETJMP:
3384 case REG_TM:
3385 case REG_CALL_NOCF_CHECK:
3386 add_reg_note (new_insn, REG_NOTE_KIND (note),
3387 XEXP (note, 0));
3388 break;
3389 default:
3390 /* Discard all other reg notes. */
3391 break;
3392 }
3393
3394 /* Croak if there is another call in the sequence. */
3395 while (++i <= match_len)
3396 {
3397 j = peep2_buf_position (peep2_current + i);
3398 old_insn = peep2_insn_data[j].insn;
3399 gcc_assert (!CALL_P (old_insn));
3400 }
3401 break;
3402 }
3403
3404 /* If we matched any instruction that had a REG_ARGS_SIZE, then
3405 move those notes over to the new sequence. */
3406 as_note = NULL;
3407 for (i = match_len; i >= 0; --i)
3408 {
3409 int j = peep2_buf_position (peep2_current + i);
3410 old_insn = peep2_insn_data[j].insn;
3411
3412 as_note = find_reg_note (old_insn, REG_ARGS_SIZE, NULL);
3413 if (as_note)
3414 break;
3415 }
3416
3417 i = peep2_buf_position (peep2_current + match_len);
3418 eh_note = find_reg_note (peep2_insn_data[i].insn, REG_EH_REGION, NULL_RTX);
3419
3420 /* Replace the old sequence with the new. */
3421 rtx_insn *peepinsn = peep2_insn_data[i].insn;
3422 last = emit_insn_after_setloc (attempt,
3423 peep2_insn_data[i].insn,
3424 INSN_LOCATION (peepinsn));
3425 before_try = PREV_INSN (insn);
3426 delete_insn_chain (insn, peep2_insn_data[i].insn, false);
3427
3428 /* Re-insert the EH_REGION notes. */
3429 if (eh_note || (was_call && nonlocal_goto_handler_labels))
3430 {
3431 edge eh_edge;
3432 edge_iterator ei;
3433
3434 FOR_EACH_EDGE (eh_edge, ei, bb->succs)
3435 if (eh_edge->flags & (EDGE_EH | EDGE_ABNORMAL_CALL))
3436 break;
3437
3438 if (eh_note)
3439 copy_reg_eh_region_note_backward (eh_note, last, before_try);
3440
3441 if (eh_edge)
3442 for (x = last; x != before_try; x = PREV_INSN (x))
3443 if (x != BB_END (bb)
3444 && (can_throw_internal (x)
3445 || can_nonlocal_goto (x)))
3446 {
3447 edge nfte, nehe;
3448 int flags;
3449
3450 nfte = split_block (bb, x);
3451 flags = (eh_edge->flags
3452 & (EDGE_EH | EDGE_ABNORMAL));
3453 if (CALL_P (x))
3454 flags |= EDGE_ABNORMAL_CALL;
3455 nehe = make_edge (nfte->src, eh_edge->dest,
3456 flags);
3457
3458 nehe->probability = eh_edge->probability;
3459 nfte->probability = nehe->probability.invert ();
3460
3461 peep2_do_cleanup_cfg |= purge_dead_edges (nfte->dest);
3462 bb = nfte->src;
3463 eh_edge = nehe;
3464 }
3465
3466 /* Converting possibly trapping insn to non-trapping is
3467 possible. Zap dummy outgoing edges. */
3468 peep2_do_cleanup_cfg |= purge_dead_edges (bb);
3469 }
3470
3471 /* Re-insert the ARGS_SIZE notes. */
3472 if (as_note)
3473 fixup_args_size_notes (before_try, last, INTVAL (XEXP (as_note, 0)));
3474
3475 /* If we generated a jump instruction, it won't have
3476 JUMP_LABEL set. Recompute after we're done. */
3477 for (x = last; x != before_try; x = PREV_INSN (x))
3478 if (JUMP_P (x))
3479 {
3480 peep2_do_rebuild_jump_labels = true;
3481 break;
3482 }
3483
3484 return last;
3485}
3486
3487/* After performing a replacement in basic block BB, fix up the life
3488 information in our buffer. LAST is the last of the insns that we
3489 emitted as a replacement. PREV is the insn before the start of
3490 the replacement. MATCH_LEN is the number of instructions that were
3491 matched, and which now need to be replaced in the buffer. */
3492
3493static void
3494peep2_update_life (basic_block bb, int match_len, rtx_insn *last,
3495 rtx_insn *prev)
3496{
3497 int i = peep2_buf_position (peep2_current + match_len + 1);
3498 rtx_insn *x;
3499 regset_head live;
3500
3501 INIT_REG_SET (&live);
3502 COPY_REG_SET (&live, peep2_insn_data[i].live_before);
3503
3504 gcc_assert (peep2_current_count >= match_len + 1);
3505 peep2_current_count -= match_len + 1;
3506
3507 x = last;
3508 do
3509 {
3510 if (INSN_P (x))
3511 {
3512 df_insn_rescan (x);
3513 if (peep2_current_count < MAX_INSNS_PER_PEEP2)
3514 {
3515 peep2_current_count++;
3516 if (--i < 0)
3517 i = MAX_INSNS_PER_PEEP2;
3518 peep2_insn_data[i].insn = x;
3519 df_simulate_one_insn_backwards (bb, x, &live);
3520 COPY_REG_SET (peep2_insn_data[i].live_before, &live);
3521 }
3522 }
3523 x = PREV_INSN (x);
3524 }
3525 while (x != prev);
3526 CLEAR_REG_SET (&live);
3527
3528 peep2_current = i;
3529}
3530
3531/* Add INSN, which is in BB, at the end of the peep2 insn buffer if possible.
3532 Return true if we added it, false otherwise. The caller will try to match
3533 peepholes against the buffer if we return false; otherwise it will try to
3534 add more instructions to the buffer. */
3535
3536static bool
3537peep2_fill_buffer (basic_block bb, rtx_insn *insn, regset live)
3538{
3539 int pos;
3540
3541 /* Once we have filled the maximum number of insns the buffer can hold,
3542 allow the caller to match the insns against peepholes. We wait until
3543 the buffer is full in case the target has similar peepholes of different
3544 length; we always want to match the longest if possible. */
3545 if (peep2_current_count == MAX_INSNS_PER_PEEP2)
3546 return false;
3547
3548 /* If an insn has RTX_FRAME_RELATED_P set, do not allow it to be matched with
3549 any other pattern, lest it change the semantics of the frame info. */
3550 if (RTX_FRAME_RELATED_P (insn))
3551 {
3552 /* Let the buffer drain first. */
3553 if (peep2_current_count > 0)
3554 return false;
3555 /* Now the insn will be the only thing in the buffer. */
3556 }
3557
3558 pos = peep2_buf_position (peep2_current + peep2_current_count);
3559 peep2_insn_data[pos].insn = insn;
3560 COPY_REG_SET (peep2_insn_data[pos].live_before, live);
3561 peep2_current_count++;
3562
3563 df_simulate_one_insn_forwards (bb, insn, live);
3564 return true;
3565}
3566
3567/* Perform the peephole2 optimization pass. */
3568
3569static void
3570peephole2_optimize (void)
3571{
3572 rtx_insn *insn;
3573 bitmap live;
3574 int i;
3575 basic_block bb;
3576
3577 peep2_do_cleanup_cfg = false;
3578 peep2_do_rebuild_jump_labels = false;
3579
3580 df_set_flags (DF_LR_RUN_DCE);
3581 df_note_add_problem ();
3582 df_analyze ();
3583
3584 /* Initialize the regsets we're going to use. */
3585 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
3586 peep2_insn_data[i].live_before = BITMAP_ALLOC (&reg_obstack);
3587 search_ofs = 0;
3588 live = BITMAP_ALLOC (&reg_obstack);
3589
3590 FOR_EACH_BB_REVERSE_FN (bb, cfun)
3591 {
3592 bool past_end = false;
3593 int pos;
3594
3595 rtl_profile_for_bb (bb);
3596
3597 /* Start up propagation. */
3598 bitmap_copy (live, DF_LR_IN (bb));
3599 df_simulate_initialize_forwards (bb, live);
3600 peep2_reinit_state (live);
3601
3602 insn = BB_HEAD (bb);
3603 for (;;)
3604 {
3605 rtx_insn *attempt, *head;
3606 int match_len;
3607
3608 if (!past_end && !NONDEBUG_INSN_P (insn))
3609 {
3610 next_insn:
3611 insn = NEXT_INSN (insn);
3612 if (insn == NEXT_INSN (BB_END (bb)))
3613 past_end = true;
3614 continue;
3615 }
3616 if (!past_end && peep2_fill_buffer (bb, insn, live))
3617 goto next_insn;
3618
3619 /* If we did not fill an empty buffer, it signals the end of the
3620 block. */
3621 if (peep2_current_count == 0)
3622 break;
3623
3624 /* The buffer filled to the current maximum, so try to match. */
3625
3626 pos = peep2_buf_position (peep2_current + peep2_current_count);
3627 peep2_insn_data[pos].insn = PEEP2_EOB;
3628 COPY_REG_SET (peep2_insn_data[pos].live_before, live);
3629
3630 /* Match the peephole. */
3631 head = peep2_insn_data[peep2_current].insn;
3632 attempt = peephole2_insns (PATTERN (head), head, &match_len);
3633 if (attempt != NULL)
3634 {
3635 rtx_insn *last = peep2_attempt (bb, head, match_len, attempt);
3636 if (last)
3637 {
3638 peep2_update_life (bb, match_len, last, PREV_INSN (attempt));
3639 continue;
3640 }
3641 }
3642
3643 /* No match: advance the buffer by one insn. */
3644 peep2_current = peep2_buf_position (peep2_current + 1);
3645 peep2_current_count--;
3646 }
3647 }
3648
3649 default_rtl_profile ();
3650 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
3651 BITMAP_FREE (peep2_insn_data[i].live_before);
3652 BITMAP_FREE (live);
3653 if (peep2_do_rebuild_jump_labels)
3654 rebuild_jump_labels (get_insns ());
3655 if (peep2_do_cleanup_cfg)
3656 cleanup_cfg (CLEANUP_CFG_CHANGED);
3657}
3658
3659/* Common predicates for use with define_bypass. */
3660
3661/* Helper function for store_data_bypass_p, handle just a single SET
3662 IN_SET. */
3663
3664static bool
3665store_data_bypass_p_1 (rtx_insn *out_insn, rtx in_set)
3666{
3667 if (!MEM_P (SET_DEST (in_set)))
3668 return false;
3669
3670 rtx out_set = single_set (out_insn);
3671 if (out_set)
3672 return !reg_mentioned_p (SET_DEST (out_set), SET_DEST (in_set));
3673
3674 rtx out_pat = PATTERN (out_insn);
3675 if (GET_CODE (out_pat) != PARALLEL)
3676 return false;
3677
3678 for (int i = 0; i < XVECLEN (out_pat, 0); i++)
3679 {
3680 rtx out_exp = XVECEXP (out_pat, 0, i);
3681
3682 if (GET_CODE (out_exp) == CLOBBER || GET_CODE (out_exp) == USE)
3683 continue;
3684
3685 gcc_assert (GET_CODE (out_exp) == SET);
3686
3687 if (reg_mentioned_p (SET_DEST (out_exp), SET_DEST (in_set)))
3688 return false;
3689 }
3690
3691 return true;
3692}
3693
3694/* True if the dependency between OUT_INSN and IN_INSN is on the store
3695 data not the address operand(s) of the store. IN_INSN and OUT_INSN
3696 must be either a single_set or a PARALLEL with SETs inside. */
3697
3698int
3699store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
3700{
3701 rtx in_set = single_set (in_insn);
3702 if (in_set)
3703 return store_data_bypass_p_1 (out_insn, in_set);
3704
3705 rtx in_pat = PATTERN (in_insn);
3706 if (GET_CODE (in_pat) != PARALLEL)
3707 return false;
3708
3709 for (int i = 0; i < XVECLEN (in_pat, 0); i++)
3710 {
3711 rtx in_exp = XVECEXP (in_pat, 0, i);
3712
3713 if (GET_CODE (in_exp) == CLOBBER || GET_CODE (in_exp) == USE)
3714 continue;
3715
3716 gcc_assert (GET_CODE (in_exp) == SET);
3717
3718 if (!store_data_bypass_p_1 (out_insn, in_exp))
3719 return false;
3720 }
3721
3722 return true;
3723}
3724
3725/* True if the dependency between OUT_INSN and IN_INSN is in the IF_THEN_ELSE
3726 condition, and not the THEN or ELSE branch. OUT_INSN may be either a single
3727 or multiple set; IN_INSN should be single_set for truth, but for convenience
3728 of insn categorization may be any JUMP or CALL insn. */
3729
3730int
3731if_test_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
3732{
3733 rtx out_set, in_set;
3734
3735 in_set = single_set (in_insn);
3736 if (! in_set)
3737 {
3738 gcc_assert (JUMP_P (in_insn) || CALL_P (in_insn));
3739 return false;
3740 }
3741
3742 if (GET_CODE (SET_SRC (in_set)) != IF_THEN_ELSE)
3743 return false;
3744 in_set = SET_SRC (in_set);
3745
3746 out_set = single_set (out_insn);
3747 if (out_set)
3748 {
3749 if (reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 1))
3750 || reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 2)))
3751 return false;
3752 }
3753 else
3754 {
3755 rtx out_pat;
3756 int i;
3757
3758 out_pat = PATTERN (out_insn);
3759 gcc_assert (GET_CODE (out_pat) == PARALLEL);
3760
3761 for (i = 0; i < XVECLEN (out_pat, 0); i++)
3762 {
3763 rtx exp = XVECEXP (out_pat, 0, i);
3764
3765 if (GET_CODE (exp) == CLOBBER)
3766 continue;
3767
3768 gcc_assert (GET_CODE (exp) == SET);
3769
3770 if (reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 1))
3771 || reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 2)))
3772 return false;
3773 }
3774 }
3775
3776 return true;
3777}
3778
3779static unsigned int
3780rest_of_handle_peephole2 (void)
3781{
3782 if (HAVE_peephole2)
3783 peephole2_optimize ();
3784
3785 return 0;
3786}
3787
3788namespace {
3789
3790const pass_data pass_data_peephole2 =
3791{
3792 RTL_PASS, /* type */
3793 "peephole2", /* name */
3794 OPTGROUP_NONE, /* optinfo_flags */
3795 TV_PEEPHOLE2, /* tv_id */
3796 0, /* properties_required */
3797 0, /* properties_provided */
3798 0, /* properties_destroyed */
3799 0, /* todo_flags_start */
3800 TODO_df_finish, /* todo_flags_finish */
3801};
3802
3803class pass_peephole2 : public rtl_opt_pass
3804{
3805public:
3806 pass_peephole2 (gcc::context *ctxt)
3807 : rtl_opt_pass (pass_data_peephole2, ctxt)
3808 {}
3809
3810 /* opt_pass methods: */
3811 /* The epiphany backend creates a second instance of this pass, so we need
3812 a clone method. */
3813 opt_pass * clone () { return new pass_peephole2 (m_ctxt); }
3814 virtual bool gate (function *) { return (optimize > 0 && flag_peephole2); }
3815 virtual unsigned int execute (function *)
3816 {
3817 return rest_of_handle_peephole2 ();
3818 }
3819
3820}; // class pass_peephole2
3821
3822} // anon namespace
3823
3824rtl_opt_pass *
3825make_pass_peephole2 (gcc::context *ctxt)
3826{
3827 return new pass_peephole2 (ctxt);
3828}
3829
3830namespace {
3831
3832const pass_data pass_data_split_all_insns =
3833{
3834 RTL_PASS, /* type */
3835 "split1", /* name */
3836 OPTGROUP_NONE, /* optinfo_flags */
3837 TV_NONE, /* tv_id */
3838 0, /* properties_required */
3839 PROP_rtl_split_insns, /* properties_provided */
3840 0, /* properties_destroyed */
3841 0, /* todo_flags_start */
3842 0, /* todo_flags_finish */
3843};
3844
3845class pass_split_all_insns : public rtl_opt_pass
3846{
3847public:
3848 pass_split_all_insns (gcc::context *ctxt)
3849 : rtl_opt_pass (pass_data_split_all_insns, ctxt)
3850 {}
3851
3852 /* opt_pass methods: */
3853 /* The epiphany backend creates a second instance of this pass, so
3854 we need a clone method. */
3855 opt_pass * clone () { return new pass_split_all_insns (m_ctxt); }
3856 virtual unsigned int execute (function *)
3857 {
3858 split_all_insns ();
3859 return 0;
3860 }
3861
3862}; // class pass_split_all_insns
3863
3864} // anon namespace
3865
3866rtl_opt_pass *
3867make_pass_split_all_insns (gcc::context *ctxt)
3868{
3869 return new pass_split_all_insns (ctxt);
3870}
3871
3872namespace {
3873
3874const pass_data pass_data_split_after_reload =
3875{
3876 RTL_PASS, /* type */
3877 "split2", /* name */
3878 OPTGROUP_NONE, /* optinfo_flags */
3879 TV_NONE, /* tv_id */
3880 0, /* properties_required */
3881 0, /* properties_provided */
3882 0, /* properties_destroyed */
3883 0, /* todo_flags_start */
3884 0, /* todo_flags_finish */
3885};
3886
3887class pass_split_after_reload : public rtl_opt_pass
3888{
3889public:
3890 pass_split_after_reload (gcc::context *ctxt)
3891 : rtl_opt_pass (pass_data_split_after_reload, ctxt)
3892 {}
3893
3894 /* opt_pass methods: */
3895 virtual bool gate (function *)
3896 {
3897 /* If optimizing, then go ahead and split insns now. */
3898 if (optimize > 0)
3899 return true;
3900
3901#ifdef STACK_REGS
3902 return true;
3903#else
3904 return false;
3905#endif
3906 }
3907
3908 virtual unsigned int execute (function *)
3909 {
3910 split_all_insns ();
3911 return 0;
3912 }
3913
3914}; // class pass_split_after_reload
3915
3916} // anon namespace
3917
3918rtl_opt_pass *
3919make_pass_split_after_reload (gcc::context *ctxt)
3920{
3921 return new pass_split_after_reload (ctxt);
3922}
3923
3924namespace {
3925
3926const pass_data pass_data_split_before_regstack =
3927{
3928 RTL_PASS, /* type */
3929 "split3", /* name */
3930 OPTGROUP_NONE, /* optinfo_flags */
3931 TV_NONE, /* tv_id */
3932 0, /* properties_required */
3933 0, /* properties_provided */
3934 0, /* properties_destroyed */
3935 0, /* todo_flags_start */
3936 0, /* todo_flags_finish */
3937};
3938
3939class pass_split_before_regstack : public rtl_opt_pass
3940{
3941public:
3942 pass_split_before_regstack (gcc::context *ctxt)
3943 : rtl_opt_pass (pass_data_split_before_regstack, ctxt)
3944 {}
3945
3946 /* opt_pass methods: */
3947 virtual bool gate (function *);
3948 virtual unsigned int execute (function *)
3949 {
3950 split_all_insns ();
3951 return 0;
3952 }
3953
3954}; // class pass_split_before_regstack
3955
3956bool
3957pass_split_before_regstack::gate (function *)
3958{
3959#if HAVE_ATTR_length && defined (STACK_REGS)
3960 /* If flow2 creates new instructions which need splitting
3961 and scheduling after reload is not done, they might not be
3962 split until final which doesn't allow splitting
3963 if HAVE_ATTR_length. */
3964# ifdef INSN_SCHEDULING
3965 return (optimize && !flag_schedule_insns_after_reload);
3966# else
3967 return (optimize);
3968# endif
3969#else
3970 return 0;
3971#endif
3972}
3973
3974} // anon namespace
3975
3976rtl_opt_pass *
3977make_pass_split_before_regstack (gcc::context *ctxt)
3978{
3979 return new pass_split_before_regstack (ctxt);
3980}
3981
3982static unsigned int
3983rest_of_handle_split_before_sched2 (void)
3984{
3985#ifdef INSN_SCHEDULING
3986 split_all_insns ();
3987#endif
3988 return 0;
3989}
3990
3991namespace {
3992
3993const pass_data pass_data_split_before_sched2 =
3994{
3995 RTL_PASS, /* type */
3996 "split4", /* name */
3997 OPTGROUP_NONE, /* optinfo_flags */
3998 TV_NONE, /* tv_id */
3999 0, /* properties_required */
4000 0, /* properties_provided */
4001 0, /* properties_destroyed */
4002 0, /* todo_flags_start */
4003 0, /* todo_flags_finish */
4004};
4005
4006class pass_split_before_sched2 : public rtl_opt_pass
4007{
4008public:
4009 pass_split_before_sched2 (gcc::context *ctxt)
4010 : rtl_opt_pass (pass_data_split_before_sched2, ctxt)
4011 {}
4012
4013 /* opt_pass methods: */
4014 virtual bool gate (function *)
4015 {
4016#ifdef INSN_SCHEDULING
4017 return optimize > 0 && flag_schedule_insns_after_reload;
4018#else
4019 return false;
4020#endif
4021 }
4022
4023 virtual unsigned int execute (function *)
4024 {
4025 return rest_of_handle_split_before_sched2 ();
4026 }
4027
4028}; // class pass_split_before_sched2
4029
4030} // anon namespace
4031
4032rtl_opt_pass *
4033make_pass_split_before_sched2 (gcc::context *ctxt)
4034{
4035 return new pass_split_before_sched2 (ctxt);
4036}
4037
4038namespace {
4039
4040const pass_data pass_data_split_for_shorten_branches =
4041{
4042 RTL_PASS, /* type */
4043 "split5", /* name */
4044 OPTGROUP_NONE, /* optinfo_flags */
4045 TV_NONE, /* tv_id */
4046 0, /* properties_required */
4047 0, /* properties_provided */
4048 0, /* properties_destroyed */
4049 0, /* todo_flags_start */
4050 0, /* todo_flags_finish */
4051};
4052
4053class pass_split_for_shorten_branches : public rtl_opt_pass
4054{
4055public:
4056 pass_split_for_shorten_branches (gcc::context *ctxt)
4057 : rtl_opt_pass (pass_data_split_for_shorten_branches, ctxt)
4058 {}
4059
4060 /* opt_pass methods: */
4061 virtual bool gate (function *)
4062 {
4063 /* The placement of the splitting that we do for shorten_branches
4064 depends on whether regstack is used by the target or not. */
4065#if HAVE_ATTR_length && !defined (STACK_REGS)
4066 return true;
4067#else
4068 return false;
4069#endif
4070 }
4071
4072 virtual unsigned int execute (function *)
4073 {
4074 return split_all_insns_noflow ();
4075 }
4076
4077}; // class pass_split_for_shorten_branches
4078
4079} // anon namespace
4080
4081rtl_opt_pass *
4082make_pass_split_for_shorten_branches (gcc::context *ctxt)
4083{
4084 return new pass_split_for_shorten_branches (ctxt);
4085}
4086
4087/* (Re)initialize the target information after a change in target. */
4088
4089void
4090recog_init ()
4091{
4092 /* The information is zero-initialized, so we don't need to do anything
4093 first time round. */
4094 if (!this_target_recog->x_initialized)
4095 {
4096 this_target_recog->x_initialized = true;
4097 return;
4098 }
4099 memset (this_target_recog->x_bool_attr_masks, 0,
4100 sizeof (this_target_recog->x_bool_attr_masks));
4101 for (unsigned int i = 0; i < NUM_INSN_CODES; ++i)
4102 if (this_target_recog->x_op_alt[i])
4103 {
4104 free (this_target_recog->x_op_alt[i]);
4105 this_target_recog->x_op_alt[i] = 0;
4106 }
4107}
4108