1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * OMAP4 Clock domains framework |
4 | * |
5 | * Copyright (C) 2009-2011 Texas Instruments, Inc. |
6 | * Copyright (C) 2009-2011 Nokia Corporation |
7 | * |
8 | * Abhijit Pagare (abhijitpagare@ti.com) |
9 | * Benoit Cousson (b-cousson@ti.com) |
10 | * Paul Walmsley (paul@pwsan.com) |
11 | * |
12 | * This file is automatically generated from the OMAP hardware databases. |
13 | * We respectfully ask that any modifications to this file be coordinated |
14 | * with the public linux-omap@vger.kernel.org mailing list and the |
15 | * authors above to ensure that the autogeneration scripts are kept |
16 | * up-to-date with the file contents. |
17 | */ |
18 | |
19 | #include <linux/kernel.h> |
20 | #include <linux/io.h> |
21 | |
22 | #include "clockdomain.h" |
23 | #include "cm1_44xx.h" |
24 | #include "cm2_44xx.h" |
25 | |
26 | #include "cm-regbits-44xx.h" |
27 | #include "prm44xx.h" |
28 | #include "prcm44xx.h" |
29 | #include "prcm_mpu44xx.h" |
30 | |
31 | /* Static Dependencies for OMAP4 Clock Domains */ |
32 | |
33 | static struct clkdm_dep d2d_wkup_sleep_deps[] = { |
34 | { .clkdm_name = "abe_clkdm" }, |
35 | { .clkdm_name = "ivahd_clkdm" }, |
36 | { .clkdm_name = "l3_1_clkdm" }, |
37 | { .clkdm_name = "l3_2_clkdm" }, |
38 | { .clkdm_name = "l3_emif_clkdm" }, |
39 | { .clkdm_name = "l3_init_clkdm" }, |
40 | { .clkdm_name = "l4_cfg_clkdm" }, |
41 | { .clkdm_name = "l4_per_clkdm" }, |
42 | { NULL }, |
43 | }; |
44 | |
45 | static struct clkdm_dep ducati_wkup_sleep_deps[] = { |
46 | { .clkdm_name = "abe_clkdm" }, |
47 | { .clkdm_name = "ivahd_clkdm" }, |
48 | { .clkdm_name = "l3_1_clkdm" }, |
49 | { .clkdm_name = "l3_2_clkdm" }, |
50 | { .clkdm_name = "l3_dss_clkdm" }, |
51 | { .clkdm_name = "l3_emif_clkdm" }, |
52 | { .clkdm_name = "l3_gfx_clkdm" }, |
53 | { .clkdm_name = "l3_init_clkdm" }, |
54 | { .clkdm_name = "l4_cfg_clkdm" }, |
55 | { .clkdm_name = "l4_per_clkdm" }, |
56 | { .clkdm_name = "l4_secure_clkdm" }, |
57 | { .clkdm_name = "l4_wkup_clkdm" }, |
58 | { .clkdm_name = "tesla_clkdm" }, |
59 | { NULL }, |
60 | }; |
61 | |
62 | static struct clkdm_dep iss_wkup_sleep_deps[] = { |
63 | { .clkdm_name = "ivahd_clkdm" }, |
64 | { .clkdm_name = "l3_1_clkdm" }, |
65 | { .clkdm_name = "l3_emif_clkdm" }, |
66 | { NULL }, |
67 | }; |
68 | |
69 | static struct clkdm_dep ivahd_wkup_sleep_deps[] = { |
70 | { .clkdm_name = "l3_1_clkdm" }, |
71 | { .clkdm_name = "l3_emif_clkdm" }, |
72 | { NULL }, |
73 | }; |
74 | |
75 | static struct clkdm_dep l3_dma_wkup_sleep_deps[] = { |
76 | { .clkdm_name = "abe_clkdm" }, |
77 | { .clkdm_name = "ducati_clkdm" }, |
78 | { .clkdm_name = "ivahd_clkdm" }, |
79 | { .clkdm_name = "l3_1_clkdm" }, |
80 | { .clkdm_name = "l3_dss_clkdm" }, |
81 | { .clkdm_name = "l3_emif_clkdm" }, |
82 | { .clkdm_name = "l3_init_clkdm" }, |
83 | { .clkdm_name = "l4_cfg_clkdm" }, |
84 | { .clkdm_name = "l4_per_clkdm" }, |
85 | { .clkdm_name = "l4_secure_clkdm" }, |
86 | { .clkdm_name = "l4_wkup_clkdm" }, |
87 | { NULL }, |
88 | }; |
89 | |
90 | static struct clkdm_dep l3_dss_wkup_sleep_deps[] = { |
91 | { .clkdm_name = "ivahd_clkdm" }, |
92 | { .clkdm_name = "l3_2_clkdm" }, |
93 | { .clkdm_name = "l3_emif_clkdm" }, |
94 | { NULL }, |
95 | }; |
96 | |
97 | static struct clkdm_dep l3_gfx_wkup_sleep_deps[] = { |
98 | { .clkdm_name = "ivahd_clkdm" }, |
99 | { .clkdm_name = "l3_1_clkdm" }, |
100 | { .clkdm_name = "l3_emif_clkdm" }, |
101 | { NULL }, |
102 | }; |
103 | |
104 | static struct clkdm_dep l3_init_wkup_sleep_deps[] = { |
105 | { .clkdm_name = "abe_clkdm" }, |
106 | { .clkdm_name = "ivahd_clkdm" }, |
107 | { .clkdm_name = "l3_emif_clkdm" }, |
108 | { .clkdm_name = "l4_cfg_clkdm" }, |
109 | { .clkdm_name = "l4_per_clkdm" }, |
110 | { .clkdm_name = "l4_secure_clkdm" }, |
111 | { .clkdm_name = "l4_wkup_clkdm" }, |
112 | { NULL }, |
113 | }; |
114 | |
115 | static struct clkdm_dep l4_secure_wkup_sleep_deps[] = { |
116 | { .clkdm_name = "l3_1_clkdm" }, |
117 | { .clkdm_name = "l3_emif_clkdm" }, |
118 | { .clkdm_name = "l4_per_clkdm" }, |
119 | { NULL }, |
120 | }; |
121 | |
122 | static struct clkdm_dep mpu_wkup_sleep_deps[] = { |
123 | { .clkdm_name = "abe_clkdm" }, |
124 | { .clkdm_name = "ducati_clkdm" }, |
125 | { .clkdm_name = "ivahd_clkdm" }, |
126 | { .clkdm_name = "l3_1_clkdm" }, |
127 | { .clkdm_name = "l3_2_clkdm" }, |
128 | { .clkdm_name = "l3_dss_clkdm" }, |
129 | { .clkdm_name = "l3_emif_clkdm" }, |
130 | { .clkdm_name = "l3_gfx_clkdm" }, |
131 | { .clkdm_name = "l3_init_clkdm" }, |
132 | { .clkdm_name = "l4_cfg_clkdm" }, |
133 | { .clkdm_name = "l4_per_clkdm" }, |
134 | { .clkdm_name = "l4_secure_clkdm" }, |
135 | { .clkdm_name = "l4_wkup_clkdm" }, |
136 | { .clkdm_name = "tesla_clkdm" }, |
137 | { NULL }, |
138 | }; |
139 | |
140 | static struct clkdm_dep tesla_wkup_sleep_deps[] = { |
141 | { .clkdm_name = "abe_clkdm" }, |
142 | { .clkdm_name = "ivahd_clkdm" }, |
143 | { .clkdm_name = "l3_1_clkdm" }, |
144 | { .clkdm_name = "l3_2_clkdm" }, |
145 | { .clkdm_name = "l3_emif_clkdm" }, |
146 | { .clkdm_name = "l3_init_clkdm" }, |
147 | { .clkdm_name = "l4_cfg_clkdm" }, |
148 | { .clkdm_name = "l4_per_clkdm" }, |
149 | { .clkdm_name = "l4_wkup_clkdm" }, |
150 | { NULL }, |
151 | }; |
152 | |
153 | static struct clockdomain l4_cefuse_44xx_clkdm = { |
154 | .name = "l4_cefuse_clkdm" , |
155 | .pwrdm = { .name = "cefuse_pwrdm" }, |
156 | .prcm_partition = OMAP4430_CM2_PARTITION, |
157 | .cm_inst = OMAP4430_CM2_CEFUSE_INST, |
158 | .clkdm_offs = OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS, |
159 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, |
160 | }; |
161 | |
162 | static struct clockdomain l4_cfg_44xx_clkdm = { |
163 | .name = "l4_cfg_clkdm" , |
164 | .pwrdm = { .name = "core_pwrdm" }, |
165 | .prcm_partition = OMAP4430_CM2_PARTITION, |
166 | .cm_inst = OMAP4430_CM2_CORE_INST, |
167 | .clkdm_offs = OMAP4430_CM2_CORE_L4CFG_CDOFFS, |
168 | .dep_bit = OMAP4430_L4CFG_STATDEP_SHIFT, |
169 | .flags = CLKDM_CAN_HWSUP, |
170 | }; |
171 | |
172 | static struct clockdomain tesla_44xx_clkdm = { |
173 | .name = "tesla_clkdm" , |
174 | .pwrdm = { .name = "tesla_pwrdm" }, |
175 | .prcm_partition = OMAP4430_CM1_PARTITION, |
176 | .cm_inst = OMAP4430_CM1_TESLA_INST, |
177 | .clkdm_offs = OMAP4430_CM1_TESLA_TESLA_CDOFFS, |
178 | .dep_bit = OMAP4430_TESLA_STATDEP_SHIFT, |
179 | .wkdep_srcs = tesla_wkup_sleep_deps, |
180 | .sleepdep_srcs = tesla_wkup_sleep_deps, |
181 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
182 | }; |
183 | |
184 | static struct clockdomain l3_gfx_44xx_clkdm = { |
185 | .name = "l3_gfx_clkdm" , |
186 | .pwrdm = { .name = "gfx_pwrdm" }, |
187 | .prcm_partition = OMAP4430_CM2_PARTITION, |
188 | .cm_inst = OMAP4430_CM2_GFX_INST, |
189 | .clkdm_offs = OMAP4430_CM2_GFX_GFX_CDOFFS, |
190 | .dep_bit = OMAP4430_GFX_STATDEP_SHIFT, |
191 | .wkdep_srcs = l3_gfx_wkup_sleep_deps, |
192 | .sleepdep_srcs = l3_gfx_wkup_sleep_deps, |
193 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
194 | }; |
195 | |
196 | static struct clockdomain ivahd_44xx_clkdm = { |
197 | .name = "ivahd_clkdm" , |
198 | .pwrdm = { .name = "ivahd_pwrdm" }, |
199 | .prcm_partition = OMAP4430_CM2_PARTITION, |
200 | .cm_inst = OMAP4430_CM2_IVAHD_INST, |
201 | .clkdm_offs = OMAP4430_CM2_IVAHD_IVAHD_CDOFFS, |
202 | .dep_bit = OMAP4430_IVAHD_STATDEP_SHIFT, |
203 | .wkdep_srcs = ivahd_wkup_sleep_deps, |
204 | .sleepdep_srcs = ivahd_wkup_sleep_deps, |
205 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
206 | }; |
207 | |
208 | static struct clockdomain l4_secure_44xx_clkdm = { |
209 | .name = "l4_secure_clkdm" , |
210 | .pwrdm = { .name = "l4per_pwrdm" }, |
211 | .prcm_partition = OMAP4430_CM2_PARTITION, |
212 | .cm_inst = OMAP4430_CM2_L4PER_INST, |
213 | .clkdm_offs = OMAP4430_CM2_L4PER_L4SEC_CDOFFS, |
214 | .dep_bit = OMAP4430_L4SEC_STATDEP_SHIFT, |
215 | .wkdep_srcs = l4_secure_wkup_sleep_deps, |
216 | .sleepdep_srcs = l4_secure_wkup_sleep_deps, |
217 | .flags = CLKDM_CAN_SWSUP, |
218 | }; |
219 | |
220 | static struct clockdomain l4_per_44xx_clkdm = { |
221 | .name = "l4_per_clkdm" , |
222 | .pwrdm = { .name = "l4per_pwrdm" }, |
223 | .prcm_partition = OMAP4430_CM2_PARTITION, |
224 | .cm_inst = OMAP4430_CM2_L4PER_INST, |
225 | .clkdm_offs = OMAP4430_CM2_L4PER_L4PER_CDOFFS, |
226 | .dep_bit = OMAP4430_L4PER_STATDEP_SHIFT, |
227 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
228 | }; |
229 | |
230 | static struct clockdomain abe_44xx_clkdm = { |
231 | .name = "abe_clkdm" , |
232 | .pwrdm = { .name = "abe_pwrdm" }, |
233 | .prcm_partition = OMAP4430_CM1_PARTITION, |
234 | .cm_inst = OMAP4430_CM1_ABE_INST, |
235 | .clkdm_offs = OMAP4430_CM1_ABE_ABE_CDOFFS, |
236 | .dep_bit = OMAP4430_ABE_STATDEP_SHIFT, |
237 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
238 | }; |
239 | |
240 | static struct clockdomain l3_instr_44xx_clkdm = { |
241 | .name = "l3_instr_clkdm" , |
242 | .pwrdm = { .name = "core_pwrdm" }, |
243 | .prcm_partition = OMAP4430_CM2_PARTITION, |
244 | .cm_inst = OMAP4430_CM2_CORE_INST, |
245 | .clkdm_offs = OMAP4430_CM2_CORE_L3INSTR_CDOFFS, |
246 | }; |
247 | |
248 | static struct clockdomain l3_init_44xx_clkdm = { |
249 | .name = "l3_init_clkdm" , |
250 | .pwrdm = { .name = "l3init_pwrdm" }, |
251 | .prcm_partition = OMAP4430_CM2_PARTITION, |
252 | .cm_inst = OMAP4430_CM2_L3INIT_INST, |
253 | .clkdm_offs = OMAP4430_CM2_L3INIT_L3INIT_CDOFFS, |
254 | .dep_bit = OMAP4430_L3INIT_STATDEP_SHIFT, |
255 | .wkdep_srcs = l3_init_wkup_sleep_deps, |
256 | .sleepdep_srcs = l3_init_wkup_sleep_deps, |
257 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
258 | }; |
259 | |
260 | static struct clockdomain d2d_44xx_clkdm = { |
261 | .name = "d2d_clkdm" , |
262 | .pwrdm = { .name = "core_pwrdm" }, |
263 | .prcm_partition = OMAP4430_CM2_PARTITION, |
264 | .cm_inst = OMAP4430_CM2_CORE_INST, |
265 | .clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS, |
266 | .wkdep_srcs = d2d_wkup_sleep_deps, |
267 | .sleepdep_srcs = d2d_wkup_sleep_deps, |
268 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, |
269 | }; |
270 | |
271 | static struct clockdomain mpu0_44xx_clkdm = { |
272 | .name = "mpu0_clkdm" , |
273 | .pwrdm = { .name = "cpu0_pwrdm" }, |
274 | .prcm_partition = OMAP4430_PRCM_MPU_PARTITION, |
275 | .cm_inst = OMAP4430_PRCM_MPU_CPU0_INST, |
276 | .clkdm_offs = OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS, |
277 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, |
278 | }; |
279 | |
280 | static struct clockdomain mpu1_44xx_clkdm = { |
281 | .name = "mpu1_clkdm" , |
282 | .pwrdm = { .name = "cpu1_pwrdm" }, |
283 | .prcm_partition = OMAP4430_PRCM_MPU_PARTITION, |
284 | .cm_inst = OMAP4430_PRCM_MPU_CPU1_INST, |
285 | .clkdm_offs = OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS, |
286 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, |
287 | }; |
288 | |
289 | static struct clockdomain l3_emif_44xx_clkdm = { |
290 | .name = "l3_emif_clkdm" , |
291 | .pwrdm = { .name = "core_pwrdm" }, |
292 | .prcm_partition = OMAP4430_CM2_PARTITION, |
293 | .cm_inst = OMAP4430_CM2_CORE_INST, |
294 | .clkdm_offs = OMAP4430_CM2_CORE_MEMIF_CDOFFS, |
295 | .dep_bit = OMAP4430_MEMIF_STATDEP_SHIFT, |
296 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, |
297 | }; |
298 | |
299 | static struct clockdomain l4_ao_44xx_clkdm = { |
300 | .name = "l4_ao_clkdm" , |
301 | .pwrdm = { .name = "always_on_core_pwrdm" }, |
302 | .prcm_partition = OMAP4430_CM2_PARTITION, |
303 | .cm_inst = OMAP4430_CM2_ALWAYS_ON_INST, |
304 | .clkdm_offs = OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS, |
305 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, |
306 | }; |
307 | |
308 | static struct clockdomain ducati_44xx_clkdm = { |
309 | .name = "ducati_clkdm" , |
310 | .pwrdm = { .name = "core_pwrdm" }, |
311 | .prcm_partition = OMAP4430_CM2_PARTITION, |
312 | .cm_inst = OMAP4430_CM2_CORE_INST, |
313 | .clkdm_offs = OMAP4430_CM2_CORE_DUCATI_CDOFFS, |
314 | .dep_bit = OMAP4430_DUCATI_STATDEP_SHIFT, |
315 | .wkdep_srcs = ducati_wkup_sleep_deps, |
316 | .sleepdep_srcs = ducati_wkup_sleep_deps, |
317 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
318 | }; |
319 | |
320 | static struct clockdomain mpu_44xx_clkdm = { |
321 | .name = "mpuss_clkdm" , |
322 | .pwrdm = { .name = "mpu_pwrdm" }, |
323 | .prcm_partition = OMAP4430_CM1_PARTITION, |
324 | .cm_inst = OMAP4430_CM1_MPU_INST, |
325 | .clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS, |
326 | .wkdep_srcs = mpu_wkup_sleep_deps, |
327 | .sleepdep_srcs = mpu_wkup_sleep_deps, |
328 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, |
329 | }; |
330 | |
331 | static struct clockdomain l3_2_44xx_clkdm = { |
332 | .name = "l3_2_clkdm" , |
333 | .pwrdm = { .name = "core_pwrdm" }, |
334 | .prcm_partition = OMAP4430_CM2_PARTITION, |
335 | .cm_inst = OMAP4430_CM2_CORE_INST, |
336 | .clkdm_offs = OMAP4430_CM2_CORE_L3_2_CDOFFS, |
337 | .dep_bit = OMAP4430_L3_2_STATDEP_SHIFT, |
338 | .flags = CLKDM_CAN_HWSUP, |
339 | }; |
340 | |
341 | static struct clockdomain l3_1_44xx_clkdm = { |
342 | .name = "l3_1_clkdm" , |
343 | .pwrdm = { .name = "core_pwrdm" }, |
344 | .prcm_partition = OMAP4430_CM2_PARTITION, |
345 | .cm_inst = OMAP4430_CM2_CORE_INST, |
346 | .clkdm_offs = OMAP4430_CM2_CORE_L3_1_CDOFFS, |
347 | .dep_bit = OMAP4430_L3_1_STATDEP_SHIFT, |
348 | .flags = CLKDM_CAN_HWSUP, |
349 | }; |
350 | |
351 | static struct clockdomain iss_44xx_clkdm = { |
352 | .name = "iss_clkdm" , |
353 | .pwrdm = { .name = "cam_pwrdm" }, |
354 | .prcm_partition = OMAP4430_CM2_PARTITION, |
355 | .cm_inst = OMAP4430_CM2_CAM_INST, |
356 | .clkdm_offs = OMAP4430_CM2_CAM_CAM_CDOFFS, |
357 | .wkdep_srcs = iss_wkup_sleep_deps, |
358 | .sleepdep_srcs = iss_wkup_sleep_deps, |
359 | .flags = CLKDM_CAN_SWSUP, |
360 | }; |
361 | |
362 | static struct clockdomain l3_dss_44xx_clkdm = { |
363 | .name = "l3_dss_clkdm" , |
364 | .pwrdm = { .name = "dss_pwrdm" }, |
365 | .prcm_partition = OMAP4430_CM2_PARTITION, |
366 | .cm_inst = OMAP4430_CM2_DSS_INST, |
367 | .clkdm_offs = OMAP4430_CM2_DSS_DSS_CDOFFS, |
368 | .dep_bit = OMAP4430_DSS_STATDEP_SHIFT, |
369 | .wkdep_srcs = l3_dss_wkup_sleep_deps, |
370 | .sleepdep_srcs = l3_dss_wkup_sleep_deps, |
371 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
372 | }; |
373 | |
374 | static struct clockdomain l4_wkup_44xx_clkdm = { |
375 | .name = "l4_wkup_clkdm" , |
376 | .pwrdm = { .name = "wkup_pwrdm" }, |
377 | .prcm_partition = OMAP4430_PRM_PARTITION, |
378 | .cm_inst = OMAP4430_PRM_WKUP_CM_INST, |
379 | .clkdm_offs = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS, |
380 | .dep_bit = OMAP4430_L4WKUP_STATDEP_SHIFT, |
381 | .flags = CLKDM_CAN_HWSUP | CLKDM_ACTIVE_WITH_MPU, |
382 | }; |
383 | |
384 | static struct clockdomain emu_sys_44xx_clkdm = { |
385 | .name = "emu_sys_clkdm" , |
386 | .pwrdm = { .name = "emu_pwrdm" }, |
387 | .prcm_partition = OMAP4430_PRM_PARTITION, |
388 | .cm_inst = OMAP4430_PRM_EMU_CM_INST, |
389 | .clkdm_offs = OMAP4430_PRM_EMU_CM_EMU_CDOFFS, |
390 | .flags = (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_FORCE_WAKEUP | |
391 | CLKDM_MISSING_IDLE_REPORTING), |
392 | }; |
393 | |
394 | static struct clockdomain l3_dma_44xx_clkdm = { |
395 | .name = "l3_dma_clkdm" , |
396 | .pwrdm = { .name = "core_pwrdm" }, |
397 | .prcm_partition = OMAP4430_CM2_PARTITION, |
398 | .cm_inst = OMAP4430_CM2_CORE_INST, |
399 | .clkdm_offs = OMAP4430_CM2_CORE_SDMA_CDOFFS, |
400 | .wkdep_srcs = l3_dma_wkup_sleep_deps, |
401 | .sleepdep_srcs = l3_dma_wkup_sleep_deps, |
402 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, |
403 | }; |
404 | |
405 | /* As clockdomains are added or removed above, this list must also be changed */ |
406 | static struct clockdomain *clockdomains_omap44xx[] __initdata = { |
407 | &l4_cefuse_44xx_clkdm, |
408 | &l4_cfg_44xx_clkdm, |
409 | &tesla_44xx_clkdm, |
410 | &l3_gfx_44xx_clkdm, |
411 | &ivahd_44xx_clkdm, |
412 | &l4_secure_44xx_clkdm, |
413 | &l4_per_44xx_clkdm, |
414 | &abe_44xx_clkdm, |
415 | &l3_instr_44xx_clkdm, |
416 | &l3_init_44xx_clkdm, |
417 | &d2d_44xx_clkdm, |
418 | &mpu0_44xx_clkdm, |
419 | &mpu1_44xx_clkdm, |
420 | &l3_emif_44xx_clkdm, |
421 | &l4_ao_44xx_clkdm, |
422 | &ducati_44xx_clkdm, |
423 | &mpu_44xx_clkdm, |
424 | &l3_2_44xx_clkdm, |
425 | &l3_1_44xx_clkdm, |
426 | &iss_44xx_clkdm, |
427 | &l3_dss_44xx_clkdm, |
428 | &l4_wkup_44xx_clkdm, |
429 | &emu_sys_44xx_clkdm, |
430 | &l3_dma_44xx_clkdm, |
431 | NULL |
432 | }; |
433 | |
434 | |
435 | void __init omap44xx_clockdomains_init(void) |
436 | { |
437 | clkdm_register_platform_funcs(co: &omap4_clkdm_operations); |
438 | clkdm_register_clkdms(c: clockdomains_omap44xx); |
439 | clkdm_complete_init(); |
440 | } |
441 | |