| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H |
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| 3 | #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H |
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| 4 | |
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| 5 | /* |
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| 6 | * OMAP3430 Clock Management register bits |
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| 7 | * |
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| 8 | * Copyright (C) 2007-2008 Texas Instruments, Inc. |
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| 9 | * Copyright (C) 2007-2008 Nokia Corporation |
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| 10 | * |
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| 11 | * Written by Paul Walmsley |
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| 12 | */ |
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| 13 | |
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| 14 | #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0) |
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| 15 | #define OMAP3430_ST_IVA2_SHIFT 0 |
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| 16 | #define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) |
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| 17 | #define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0) |
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| 18 | #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) |
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| 19 | #define OMAP3430_ST_AES2_SHIFT 28 |
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| 20 | #define OMAP3430_ST_SHA12_SHIFT 27 |
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| 21 | #define AM35XX_ST_UART4_SHIFT 23 |
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| 22 | #define OMAP3430_ST_HDQ_SHIFT 22 |
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| 23 | #define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8 |
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| 24 | #define OMAP3430_ST_MAILBOXES_SHIFT 7 |
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| 25 | #define OMAP3430_ST_SAD2D_SHIFT 3 |
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| 26 | #define OMAP3430_ST_SDMA_SHIFT 2 |
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| 27 | #define OMAP3430ES2_ST_USBTLL_SHIFT 2 |
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| 28 | #define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4) |
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| 29 | #define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2) |
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| 30 | #define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) |
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| 31 | #define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) |
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| 32 | #define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0) |
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| 33 | #define OMAP3430_ST_WDT2_SHIFT 5 |
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| 34 | #define OMAP3430_ST_32KSYNC_SHIFT 2 |
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| 35 | #define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3) |
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| 36 | #define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1 |
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| 37 | #define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) |
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| 38 | #define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) |
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| 39 | #define OMAP3430_ST_MCBSP4_SHIFT 2 |
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| 40 | #define OMAP3430_ST_MCBSP3_SHIFT 1 |
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| 41 | #define OMAP3430_ST_MCBSP2_SHIFT 0 |
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| 42 | #define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) |
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| 43 | #define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) |
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| 44 | #define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0) |
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| 45 | #define OMAP3430ES2_EN_USBHOST2_SHIFT 1 |
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| 46 | #define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1 |
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| 47 | #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) |
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| 48 | #define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0 |
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| 49 | #define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1 |
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| 50 | #define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2 |
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| 51 | #define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3 |
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| 52 | #endif |
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| 53 | |
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