| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * OMAP54xx Clock Management register bits |
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| 4 | * |
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| 5 | * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com |
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| 6 | * |
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| 7 | * Paul Walmsley (paul@pwsan.com) |
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| 8 | * Rajendra Nayak (rnayak@ti.com) |
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| 9 | * Benoit Cousson (b-cousson@ti.com) |
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| 10 | * |
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| 11 | * This file is automatically generated from the OMAP hardware databases. |
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| 12 | * We respectfully ask that any modifications to this file be coordinated |
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| 13 | * with the public linux-omap@vger.kernel.org mailing list and the |
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| 14 | * authors above to ensure that the autogeneration scripts are kept |
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| 15 | * up-to-date with the file contents. |
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| 16 | */ |
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| 17 | |
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| 18 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H |
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| 19 | #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H |
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| 20 | |
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| 21 | #define OMAP54XX_ABE_STATDEP_SHIFT 3 |
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| 22 | #define OMAP54XX_AUTO_DPLL_MODE_MASK (0x7 << 0) |
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| 23 | #define OMAP54XX_CLKSEL_SHIFT 24 |
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| 24 | #define OMAP54XX_CLKSEL_WIDTH 0x1 |
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| 25 | #define OMAP54XX_CLKSEL_0_0_SHIFT 0 |
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| 26 | #define OMAP54XX_CLKSEL_0_0_WIDTH 0x1 |
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| 27 | #define OMAP54XX_CLKSEL_AESS_FCLK_SHIFT 24 |
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| 28 | #define OMAP54XX_CLKSEL_AESS_FCLK_WIDTH 0x1 |
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| 29 | #define OMAP54XX_CLKSEL_DIV_SHIFT 25 |
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| 30 | #define OMAP54XX_CLKSEL_DIV_WIDTH 0x1 |
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| 31 | #define OMAP54XX_CLKSEL_FCLK_SHIFT 24 |
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| 32 | #define OMAP54XX_CLKSEL_FCLK_WIDTH 0x1 |
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| 33 | #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT 24 |
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| 34 | #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH 0x1 |
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| 35 | #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT 25 |
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| 36 | #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH 0x1 |
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| 37 | #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT 26 |
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| 38 | #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH 0x2 |
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| 39 | #define OMAP54XX_CLKSEL_OPP_SHIFT 0 |
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| 40 | #define OMAP54XX_CLKSEL_OPP_WIDTH 0x2 |
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| 41 | #define OMAP54XX_CLKSEL_SOURCE_SHIFT 24 |
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| 42 | #define OMAP54XX_CLKSEL_SOURCE_WIDTH 0x2 |
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| 43 | #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT 24 |
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| 44 | #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH 0x1 |
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| 45 | #define OMAP54XX_CLKSEL_UTMI_P1_SHIFT 24 |
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| 46 | #define OMAP54XX_CLKSEL_UTMI_P1_WIDTH 0x1 |
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| 47 | #define OMAP54XX_CLKSEL_UTMI_P2_SHIFT 25 |
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| 48 | #define OMAP54XX_CLKSEL_UTMI_P2_WIDTH 0x1 |
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| 49 | #define OMAP54XX_DIVHS_MASK (0x3f << 0) |
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| 50 | #define OMAP54XX_DIVHS_0_4_MASK (0x1f << 0) |
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| 51 | #define OMAP54XX_DIVHS_0_6_MASK (0x7f << 0) |
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| 52 | #define OMAP54XX_DPLL_DIV_MASK (0x7f << 0) |
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| 53 | #define OMAP54XX_DPLL_EN_MASK (0x7 << 0) |
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| 54 | #define OMAP54XX_DPLL_LPMODE_EN_MASK (1 << 10) |
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| 55 | #define OMAP54XX_DPLL_MULT_MASK (0x7ff << 8) |
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| 56 | #define OMAP54XX_DPLL_REGM4XEN_MASK (1 << 11) |
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| 57 | #define OMAP54XX_DPLL_SD_DIV_MASK (0xff << 24) |
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| 58 | #define OMAP54XX_DSP_STATDEP_SHIFT 1 |
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| 59 | #define OMAP54XX_DSS_STATDEP_SHIFT 8 |
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| 60 | #define OMAP54XX_EMIF_STATDEP_SHIFT 4 |
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| 61 | #define OMAP54XX_GPU_STATDEP_SHIFT 10 |
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| 62 | #define OMAP54XX_IPU_STATDEP_SHIFT 0 |
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| 63 | #define OMAP54XX_IVA_STATDEP_SHIFT 2 |
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| 64 | #define OMAP54XX_L3INIT_STATDEP_SHIFT 7 |
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| 65 | #define OMAP54XX_L3MAIN1_STATDEP_SHIFT 5 |
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| 66 | #define OMAP54XX_L3MAIN2_STATDEP_SHIFT 6 |
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| 67 | #define OMAP54XX_L4CFG_STATDEP_SHIFT 12 |
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| 68 | #define OMAP54XX_L4PER_STATDEP_SHIFT 13 |
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| 69 | #define OMAP54XX_L4SEC_STATDEP_SHIFT 14 |
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| 70 | #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT 11 |
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| 71 | #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT 8 |
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| 72 | #define OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT 9 |
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| 73 | #define OMAP54XX_OPTFCLKEN_CLK32K_SHIFT 8 |
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| 74 | #define OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT 8 |
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| 75 | #define OMAP54XX_OPTFCLKEN_DBCLK_SHIFT 8 |
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| 76 | #define OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT 8 |
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| 77 | #define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 |
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| 78 | #define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 |
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| 79 | #define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHIFT 7 |
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| 80 | #define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 |
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| 81 | #define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 |
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| 82 | #define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIFT 6 |
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| 83 | #define OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT 8 |
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| 84 | #define OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT 8 |
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| 85 | #define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT 11 |
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| 86 | #define OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT 10 |
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| 87 | #define OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT 8 |
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| 88 | #define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT 9 |
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| 89 | #define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 |
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| 90 | #define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 |
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| 91 | #define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 |
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| 92 | #define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 |
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| 93 | #define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 |
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| 94 | #define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 |
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| 95 | #define OMAP54XX_PAD_CLKS_GATE_SHIFT 8 |
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| 96 | #define OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT 10 |
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| 97 | #define OMAP54XX_ST_DPLL_CLK_MASK (1 << 0) |
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| 98 | #define OMAP54XX_SYS_CLKSEL_SHIFT 0 |
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| 99 | #define OMAP54XX_SYS_CLKSEL_WIDTH 0x3 |
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| 100 | #define OMAP54XX_WKUPAON_STATDEP_SHIFT 15 |
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| 101 | #endif |
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| 102 | |
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