1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * DRA7xx Clock Management register bits |
4 | * |
5 | * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com |
6 | * |
7 | * Generated by code originally written by: |
8 | * Paul Walmsley (paul@pwsan.com) |
9 | * Rajendra Nayak (rnayak@ti.com) |
10 | * Benoit Cousson (b-cousson@ti.com) |
11 | * |
12 | * This file is automatically generated from the OMAP hardware databases. |
13 | * We respectfully ask that any modifications to this file be coordinated |
14 | * with the public linux-omap@vger.kernel.org mailing list and the |
15 | * authors above to ensure that the autogeneration scripts are kept |
16 | * up-to-date with the file contents. |
17 | */ |
18 | |
19 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_7XX_H |
20 | #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_7XX_H |
21 | |
22 | #define DRA7XX_ATL_STATDEP_SHIFT 30 |
23 | #define DRA7XX_CAM_STATDEP_SHIFT 9 |
24 | #define DRA7XX_DSP1_STATDEP_SHIFT 1 |
25 | #define DRA7XX_DSP2_STATDEP_SHIFT 18 |
26 | #define DRA7XX_DSS_STATDEP_SHIFT 8 |
27 | #define DRA7XX_EMIF_STATDEP_SHIFT 4 |
28 | #define DRA7XX_EVE1_STATDEP_SHIFT 19 |
29 | #define DRA7XX_EVE2_STATDEP_SHIFT 20 |
30 | #define DRA7XX_EVE3_STATDEP_SHIFT 21 |
31 | #define DRA7XX_EVE4_STATDEP_SHIFT 22 |
32 | #define DRA7XX_GMAC_STATDEP_SHIFT 25 |
33 | #define DRA7XX_GPU_STATDEP_SHIFT 10 |
34 | #define DRA7XX_IPU1_STATDEP_SHIFT 23 |
35 | #define DRA7XX_IPU2_STATDEP_SHIFT 0 |
36 | #define DRA7XX_IPU_STATDEP_SHIFT 24 |
37 | #define DRA7XX_IVA_STATDEP_SHIFT 2 |
38 | #define DRA7XX_L3INIT_STATDEP_SHIFT 7 |
39 | #define DRA7XX_L3MAIN1_STATDEP_SHIFT 5 |
40 | #define DRA7XX_L4CFG_STATDEP_SHIFT 12 |
41 | #define DRA7XX_L4PER2_STATDEP_SHIFT 26 |
42 | #define DRA7XX_L4PER3_STATDEP_SHIFT 27 |
43 | #define DRA7XX_L4PER_STATDEP_SHIFT 13 |
44 | #define DRA7XX_L4SEC_STATDEP_SHIFT 14 |
45 | #define DRA7XX_PCIE_STATDEP_SHIFT 29 |
46 | #define DRA7XX_VPE_STATDEP_SHIFT 28 |
47 | #define DRA7XX_WKUPAON_STATDEP_SHIFT 15 |
48 | #endif |
49 | |