| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * AM33XX CM offset macros |
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| 4 | * |
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| 5 | * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/ |
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| 6 | * Vaibhav Hiremath <hvaibhav@ti.com> |
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| 7 | */ |
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| 8 | |
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| 9 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H |
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| 10 | #define __ARCH_ARM_MACH_OMAP2_CM_33XX_H |
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| 11 | |
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| 12 | #include "cm.h" |
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| 13 | #include "cm-regbits-33xx.h" |
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| 14 | #include "prcm-common.h" |
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| 15 | |
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| 16 | /* CM base address */ |
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| 17 | #define AM33XX_CM_BASE 0x44e00000 |
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| 18 | |
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| 19 | #define AM33XX_CM_REGADDR(inst, reg) \ |
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| 20 | AM33XX_L4_WK_IO_ADDRESS(AM33XX_CM_BASE + (inst) + (reg)) |
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| 21 | |
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| 22 | /* CM instances */ |
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| 23 | #define AM33XX_CM_PER_MOD 0x0000 |
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| 24 | #define AM33XX_CM_WKUP_MOD 0x0400 |
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| 25 | #define AM33XX_CM_DPLL_MOD 0x0500 |
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| 26 | #define AM33XX_CM_MPU_MOD 0x0600 |
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| 27 | #define AM33XX_CM_DEVICE_MOD 0x0700 |
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| 28 | #define AM33XX_CM_RTC_MOD 0x0800 |
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| 29 | #define AM33XX_CM_GFX_MOD 0x0900 |
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| 30 | #define AM33XX_CM_CEFUSE_MOD 0x0A00 |
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| 31 | |
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| 32 | /* CM.PER_CM register offsets */ |
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| 33 | #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000 |
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| 34 | #define AM33XX_CM_PER_L4LS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0000) |
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| 35 | #define AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET 0x0004 |
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| 36 | #define AM33XX_CM_PER_L3S_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0004) |
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| 37 | #define AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET 0x0008 |
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| 38 | #define AM33XX_CM_PER_L4FW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0008) |
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| 39 | #define AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET 0x000c |
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| 40 | #define AM33XX_CM_PER_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x000c) |
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| 41 | #define AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET 0x0028 |
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| 42 | #define AM33XX_CM_PER_EMIF_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0028) |
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| 43 | #define AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET 0x011c |
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| 44 | #define AM33XX_CM_PER_L4HS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x011c) |
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| 45 | #define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET 0x012c |
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| 46 | #define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x012c) |
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| 47 | #define AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET 0x0140 |
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| 48 | #define AM33XX_CM_PER_PRUSS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0140) |
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| 49 | #define AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET 0x0144 |
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| 50 | #define AM33XX_CM_PER_CPSW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0144) |
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| 51 | #define AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET 0x0148 |
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| 52 | #define AM33XX_CM_PER_LCDC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0148) |
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| 53 | #define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET 0x0150 |
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| 54 | #define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0150) |
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| 55 | |
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| 56 | /* CM.WKUP_CM register offsets */ |
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| 57 | #define AM33XX_CM_WKUP_CLKSTCTRL_OFFSET 0x0000 |
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| 58 | #define AM33XX_CM_WKUP_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0000) |
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| 59 | #define AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET 0x0018 |
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| 60 | #define AM33XX_CM_L3_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0018) |
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| 61 | #define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET 0x00cc |
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| 62 | #define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00cc) |
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| 63 | |
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| 64 | /* CM.DPLL_CM register offsets */ |
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| 65 | #define AM33XX_CLKSEL_GFX_FCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x002c) |
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| 66 | |
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| 67 | /* CM.MPU_CM register offsets */ |
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| 68 | #define AM33XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000 |
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| 69 | #define AM33XX_CM_MPU_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0000) |
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| 70 | #define AM33XX_CM_MPU_MPU_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0004) |
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| 71 | |
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| 72 | /* CM.DEVICE_CM register offsets */ |
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| 73 | |
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| 74 | /* CM.RTC_CM register offsets */ |
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| 75 | #define AM33XX_CM_RTC_CLKSTCTRL_OFFSET 0x0004 |
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| 76 | #define AM33XX_CM_RTC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0004) |
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| 77 | |
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| 78 | /* CM.GFX_CM register offsets */ |
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| 79 | #define AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET 0x0000 |
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| 80 | #define AM33XX_CM_GFX_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0000) |
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| 81 | #define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET 0x000c |
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| 82 | #define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1 AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x000c) |
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| 83 | |
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| 84 | /* CM.CEFUSE_CM register offsets */ |
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| 85 | #define AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000 |
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| 86 | #define AM33XX_CM_CEFUSE_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0000) |
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| 87 | |
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| 88 | |
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| 89 | #ifndef __ASSEMBLER__ |
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| 90 | int am33xx_cm_init(const struct omap_prcm_init_data *data); |
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| 91 | #endif /* ASSEMBLER */ |
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| 92 | #endif |
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| 93 | |
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