| 1 | /* |
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| 2 | * IO mappings for OMAP2+ |
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| 3 | * |
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| 4 | * IO definitions for TI OMAP processors and boards |
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| 5 | * |
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| 6 | * Copied from arch/arm/mach-sa1100/include/mach/io.h |
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| 7 | * Copyright (C) 1997-1999 Russell King |
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| 8 | * |
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| 9 | * Copyright (C) 2009-2012 Texas Instruments |
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| 10 | * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
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| 11 | * |
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| 12 | * This program is free software; you can redistribute it and/or modify it |
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| 13 | * under the terms of the GNU General Public License as published by the |
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| 14 | * Free Software Foundation; either version 2 of the License, or (at your |
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| 15 | * option) any later version. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
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| 18 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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| 19 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
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| 20 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
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| 23 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
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| 24 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | * |
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| 28 | * You should have received a copy of the GNU General Public License along |
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| 29 | * with this program; if not, write to the Free Software Foundation, Inc., |
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| 30 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
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| 31 | */ |
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| 32 | |
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| 33 | #define OMAP2_L3_IO_OFFSET 0x90000000 |
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| 34 | #define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */ |
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| 35 | |
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| 36 | #define OMAP2_L4_IO_OFFSET 0xb2000000 |
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| 37 | #define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */ |
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| 38 | |
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| 39 | #define OMAP4_L3_IO_OFFSET 0xb4000000 |
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| 40 | #define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */ |
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| 41 | |
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| 42 | #define AM33XX_L4_WK_IO_OFFSET 0xb5000000 |
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| 43 | #define AM33XX_L4_WK_IO_ADDRESS(pa) IOMEM((pa) + AM33XX_L4_WK_IO_OFFSET) |
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| 44 | |
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| 45 | #define OMAP4_L3_PER_IO_OFFSET 0xb1100000 |
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| 46 | #define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET) |
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| 47 | |
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| 48 | #define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */ |
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| 49 | #define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET) |
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| 50 | |
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| 51 | /* |
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| 52 | * ---------------------------------------------------------------------------- |
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| 53 | * Omap2 specific IO mapping |
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| 54 | * ---------------------------------------------------------------------------- |
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| 55 | */ |
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| 56 | |
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| 57 | /* We map both L3 and L4 on OMAP2 */ |
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| 58 | #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/ |
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| 59 | #define L3_24XX_VIRT (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET) |
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| 60 | #define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */ |
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| 61 | #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */ |
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| 62 | #define L4_24XX_VIRT (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET) |
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| 63 | #define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */ |
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| 64 | |
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| 65 | #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */ |
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| 66 | #define L4_WK_243X_VIRT (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET) |
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| 67 | #define L4_WK_243X_SIZE SZ_1M |
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| 68 | #define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE |
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| 69 | #define OMAP243X_GPMC_VIRT (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET) |
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| 70 | /* 0x6e000000 --> 0xfe000000 */ |
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| 71 | #define OMAP243X_GPMC_SIZE SZ_1M |
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| 72 | #define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE |
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| 73 | /* 0x6D000000 --> 0xfd000000 */ |
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| 74 | #define OMAP243X_SDRC_VIRT (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET) |
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| 75 | #define OMAP243X_SDRC_SIZE SZ_1M |
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| 76 | #define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE |
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| 77 | /* 0x6c000000 --> 0xfc000000 */ |
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| 78 | #define OMAP243X_SMS_VIRT (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET) |
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| 79 | #define OMAP243X_SMS_SIZE SZ_1M |
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| 80 | |
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| 81 | /* 2420 IVA */ |
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| 82 | #define DSP_MEM_2420_PHYS OMAP2420_DSP_MEM_BASE |
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| 83 | /* 0x58000000 --> 0xfc100000 */ |
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| 84 | #define DSP_MEM_2420_VIRT 0xfc100000 |
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| 85 | #define DSP_MEM_2420_SIZE 0x28000 |
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| 86 | #define DSP_IPI_2420_PHYS OMAP2420_DSP_IPI_BASE |
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| 87 | /* 0x59000000 --> 0xfc128000 */ |
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| 88 | #define DSP_IPI_2420_VIRT 0xfc128000 |
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| 89 | #define DSP_IPI_2420_SIZE SZ_4K |
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| 90 | #define DSP_MMU_2420_PHYS OMAP2420_DSP_MMU_BASE |
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| 91 | /* 0x5a000000 --> 0xfc129000 */ |
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| 92 | #define DSP_MMU_2420_VIRT 0xfc129000 |
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| 93 | #define DSP_MMU_2420_SIZE SZ_4K |
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| 94 | |
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| 95 | /* 2430 IVA2.1 - currently unmapped */ |
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| 96 | |
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| 97 | /* |
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| 98 | * ---------------------------------------------------------------------------- |
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| 99 | * Omap3 specific IO mapping |
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| 100 | * ---------------------------------------------------------------------------- |
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| 101 | */ |
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| 102 | |
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| 103 | /* We map both L3 and L4 on OMAP3 */ |
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| 104 | #define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 --> 0xf8000000 */ |
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| 105 | #define L3_34XX_VIRT (L3_34XX_PHYS + OMAP2_L3_IO_OFFSET) |
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| 106 | #define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */ |
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| 107 | |
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| 108 | #define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 --> 0xfa000000 */ |
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| 109 | #define L4_34XX_VIRT (L4_34XX_PHYS + OMAP2_L4_IO_OFFSET) |
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| 110 | #define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */ |
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| 111 | |
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| 112 | /* |
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| 113 | * ---------------------------------------------------------------------------- |
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| 114 | * AM33XX specific IO mapping |
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| 115 | * ---------------------------------------------------------------------------- |
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| 116 | */ |
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| 117 | #define L4_WK_AM33XX_PHYS L4_WK_AM33XX_BASE |
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| 118 | #define L4_WK_AM33XX_VIRT (L4_WK_AM33XX_PHYS + AM33XX_L4_WK_IO_OFFSET) |
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| 119 | #define L4_WK_AM33XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */ |
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| 120 | |
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| 121 | /* |
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| 122 | * Need to look at the Size 4M for L4. |
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| 123 | * VPOM3430 was not working for Int controller |
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| 124 | */ |
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| 125 | |
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| 126 | #define L4_PER_34XX_PHYS L4_PER_34XX_BASE |
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| 127 | /* 0x49000000 --> 0xfb000000 */ |
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| 128 | #define L4_PER_34XX_VIRT (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET) |
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| 129 | #define L4_PER_34XX_SIZE SZ_1M |
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| 130 | |
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| 131 | #define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE |
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| 132 | /* 0x54000000 --> 0xfe800000 */ |
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| 133 | #define L4_EMU_34XX_VIRT (L4_EMU_34XX_PHYS + OMAP2_EMU_IO_OFFSET) |
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| 134 | #define L4_EMU_34XX_SIZE SZ_8M |
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| 135 | |
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| 136 | #define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE |
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| 137 | /* 0x6e000000 --> 0xfe000000 */ |
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| 138 | #define OMAP34XX_GPMC_VIRT (OMAP34XX_GPMC_PHYS + OMAP2_L3_IO_OFFSET) |
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| 139 | #define OMAP34XX_GPMC_SIZE SZ_1M |
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| 140 | |
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| 141 | #define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE |
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| 142 | /* 0x6c000000 --> 0xfc000000 */ |
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| 143 | #define OMAP343X_SMS_VIRT (OMAP343X_SMS_PHYS + OMAP2_L3_IO_OFFSET) |
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| 144 | #define OMAP343X_SMS_SIZE SZ_1M |
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| 145 | |
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| 146 | #define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE |
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| 147 | /* 0x6D000000 --> 0xfd000000 */ |
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| 148 | #define OMAP343X_SDRC_VIRT (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET) |
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| 149 | #define OMAP343X_SDRC_SIZE SZ_1M |
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| 150 | |
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| 151 | /* 3430 IVA - currently unmapped */ |
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| 152 | |
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| 153 | /* |
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| 154 | * ---------------------------------------------------------------------------- |
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| 155 | * Omap4 specific IO mapping |
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| 156 | * ---------------------------------------------------------------------------- |
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| 157 | */ |
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| 158 | |
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| 159 | /* We map both L3 and L4 on OMAP4 */ |
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| 160 | #define L3_44XX_PHYS L3_44XX_BASE /* 0x44000000 --> 0xf8000000 */ |
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| 161 | #define L3_44XX_VIRT (L3_44XX_PHYS + OMAP4_L3_IO_OFFSET) |
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| 162 | #define L3_44XX_SIZE SZ_1M |
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| 163 | |
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| 164 | #define L4_44XX_PHYS L4_44XX_BASE /* 0x4a000000 --> 0xfc000000 */ |
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| 165 | #define L4_44XX_VIRT (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET) |
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| 166 | #define L4_44XX_SIZE SZ_4M |
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| 167 | |
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| 168 | #define L4_PER_44XX_PHYS L4_PER_44XX_BASE |
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| 169 | /* 0x48000000 --> 0xfa000000 */ |
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| 170 | #define L4_PER_44XX_VIRT (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET) |
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| 171 | #define L4_PER_44XX_SIZE SZ_4M |
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| 172 | |
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| 173 | #define L4_ABE_44XX_PHYS L4_ABE_44XX_BASE |
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| 174 | /* 0x49000000 --> 0xfb000000 */ |
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| 175 | #define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET) |
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| 176 | #define L4_ABE_44XX_SIZE SZ_1M |
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| 177 | /* |
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| 178 | * ---------------------------------------------------------------------------- |
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| 179 | * Omap5 specific IO mapping |
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| 180 | * ---------------------------------------------------------------------------- |
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| 181 | */ |
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| 182 | #define L3_54XX_PHYS L3_54XX_BASE /* 0x44000000 --> 0xf8000000 */ |
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| 183 | #define L3_54XX_VIRT (L3_54XX_PHYS + OMAP4_L3_IO_OFFSET) |
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| 184 | #define L3_54XX_SIZE SZ_1M |
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| 185 | |
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| 186 | #define L4_54XX_PHYS L4_54XX_BASE /* 0x4a000000 --> 0xfc000000 */ |
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| 187 | #define L4_54XX_VIRT (L4_54XX_PHYS + OMAP2_L4_IO_OFFSET) |
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| 188 | #define L4_54XX_SIZE SZ_4M |
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| 189 | |
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| 190 | #define L4_WK_54XX_PHYS L4_WK_54XX_BASE /* 0x4ae00000 --> 0xfce00000 */ |
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| 191 | #define L4_WK_54XX_VIRT (L4_WK_54XX_PHYS + OMAP2_L4_IO_OFFSET) |
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| 192 | #define L4_WK_54XX_SIZE SZ_2M |
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| 193 | |
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| 194 | #define L4_PER_54XX_PHYS L4_PER_54XX_BASE /* 0x48000000 --> 0xfa000000 */ |
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| 195 | #define L4_PER_54XX_VIRT (L4_PER_54XX_PHYS + OMAP2_L4_IO_OFFSET) |
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| 196 | #define L4_PER_54XX_SIZE SZ_4M |
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| 197 | |
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| 198 | /* |
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| 199 | * ---------------------------------------------------------------------------- |
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| 200 | * DRA7xx specific IO mapping |
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| 201 | * ---------------------------------------------------------------------------- |
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| 202 | */ |
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| 203 | /* |
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| 204 | * L3_MAIN_SN_DRA7XX_PHYS 0x44000000 --> 0xf8000000 |
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| 205 | * The overall space is 24MiB (0x4400_0000<->0x457F_FFFF), but mapping |
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| 206 | * everything is just inefficient, since, there are too many address holes. |
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| 207 | */ |
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| 208 | #define L3_MAIN_SN_DRA7XX_PHYS L3_MAIN_SN_DRA7XX_BASE |
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| 209 | #define L3_MAIN_SN_DRA7XX_VIRT (L3_MAIN_SN_DRA7XX_PHYS + OMAP4_L3_IO_OFFSET) |
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| 210 | #define L3_MAIN_SN_DRA7XX_SIZE SZ_1M |
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| 211 | |
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| 212 | /* |
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| 213 | * L4_PER1_DRA7XX_PHYS (0x4800_000<>0x480D_2FFF) -> 0.82MiB (alloc 1MiB) |
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| 214 | * (0x48000000<->0x48100000) <=> (0xFA000000<->0xFA100000) |
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| 215 | */ |
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| 216 | #define L4_PER1_DRA7XX_PHYS L4_PER1_DRA7XX_BASE |
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| 217 | #define L4_PER1_DRA7XX_VIRT (L4_PER1_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET) |
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| 218 | #define L4_PER1_DRA7XX_SIZE SZ_1M |
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| 219 | |
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| 220 | /* |
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| 221 | * L4_CFG_MPU_DRA7XX_PHYS (0x48210000<>0x482A_F2FF) -> 0.62MiB (alloc 1MiB) |
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| 222 | * (0x48210000<->0x48310000) <=> (0xFA210000<->0xFA310000) |
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| 223 | * NOTE: This is a bit of an orphan memory map sitting isolated in TRM |
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| 224 | */ |
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| 225 | #define L4_CFG_MPU_DRA7XX_PHYS L4_CFG_MPU_DRA7XX_BASE |
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| 226 | #define L4_CFG_MPU_DRA7XX_VIRT (L4_CFG_MPU_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET) |
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| 227 | #define L4_CFG_MPU_DRA7XX_SIZE SZ_1M |
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| 228 | |
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| 229 | /* |
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| 230 | * L4_PER2_DRA7XX_PHYS (0x4840_0000<>0x4848_8FFF) -> .53MiB (alloc 1MiB) |
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| 231 | * (0x48400000<->0x48500000) <=> (0xFA400000<->0xFA500000) |
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| 232 | */ |
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| 233 | #define L4_PER2_DRA7XX_PHYS L4_PER2_DRA7XX_BASE |
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| 234 | #define L4_PER2_DRA7XX_VIRT (L4_PER2_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET) |
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| 235 | #define L4_PER2_DRA7XX_SIZE SZ_1M |
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| 236 | |
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| 237 | /* |
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| 238 | * L4_PER3_DRA7XX_PHYS (0x4880_0000<>0x489E_0FFF) -> 1.87MiB (alloc 2MiB) |
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| 239 | * (0x48800000<->0x48A00000) <=> (0xFA800000<->0xFAA00000) |
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| 240 | */ |
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| 241 | #define L4_PER3_DRA7XX_PHYS L4_PER3_DRA7XX_BASE |
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| 242 | #define L4_PER3_DRA7XX_VIRT (L4_PER3_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET) |
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| 243 | #define L4_PER3_DRA7XX_SIZE SZ_2M |
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| 244 | |
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| 245 | /* |
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| 246 | * L4_CFG_DRA7XX_PHYS (0x4A00_0000<>0x4A22_BFFF) ->2.17MiB (alloc 3MiB)? |
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| 247 | * (0x4A000000<->0x4A300000) <=> (0xFC000000<->0xFC300000) |
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| 248 | */ |
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| 249 | #define L4_CFG_DRA7XX_PHYS L4_CFG_DRA7XX_BASE |
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| 250 | #define L4_CFG_DRA7XX_VIRT (L4_CFG_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET) |
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| 251 | #define L4_CFG_DRA7XX_SIZE (SZ_1M + SZ_2M) |
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| 252 | |
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| 253 | /* |
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| 254 | * L4_WKUP_DRA7XX_PHYS (0x4AE0_0000<>0x4AE3_EFFF) -> .24 mb (alloc 1MiB)? |
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| 255 | * (0x4AE00000<->4AF00000) <=> (0xFCE00000<->0xFCF00000) |
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| 256 | */ |
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| 257 | #define L4_WKUP_DRA7XX_PHYS L4_WKUP_DRA7XX_BASE |
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| 258 | #define L4_WKUP_DRA7XX_VIRT (L4_WKUP_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET) |
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| 259 | #define L4_WKUP_DRA7XX_SIZE SZ_1M |
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| 260 | |
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