| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * omap4-sar-layout.h: OMAP4 SAR RAM layout header file |
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| 4 | * |
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| 5 | * Copyright (C) 2011 Texas Instruments, Inc. |
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| 6 | * Santosh Shilimkar <santosh.shilimkar@ti.com> |
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| 7 | */ |
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| 8 | #ifndef OMAP_ARCH_OMAP4_SAR_LAYOUT_H |
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| 9 | #define OMAP_ARCH_OMAP4_SAR_LAYOUT_H |
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| 10 | |
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| 11 | /* |
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| 12 | * SAR BANK offsets from base address OMAP44XX/54XX_SAR_RAM_BASE |
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| 13 | */ |
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| 14 | #define SAR_BANK1_OFFSET 0x0000 |
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| 15 | #define SAR_BANK2_OFFSET 0x1000 |
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| 16 | #define SAR_BANK3_OFFSET 0x2000 |
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| 17 | #define SAR_BANK4_OFFSET 0x3000 |
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| 18 | |
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| 19 | /* Scratch pad memory offsets from SAR_BANK1 */ |
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| 20 | #define SCU_OFFSET0 0xfe4 |
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| 21 | #define SCU_OFFSET1 0xfe8 |
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| 22 | #define OMAP_TYPE_OFFSET 0xfec |
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| 23 | #define L2X0_SAVE_OFFSET0 0xff0 |
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| 24 | #define L2X0_SAVE_OFFSET1 0xff4 |
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| 25 | #define L2X0_AUXCTRL_OFFSET 0xff8 |
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| 26 | #define L2X0_PREFETCH_CTRL_OFFSET 0xffc |
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| 27 | |
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| 28 | /* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK1 */ |
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| 29 | #define CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xa04 |
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| 30 | #define CPU1_WAKEUP_NS_PA_ADDR_OFFSET 0xa08 |
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| 31 | #define OMAP5_CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xe00 |
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| 32 | #define OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET 0xe04 |
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| 33 | |
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| 34 | #define SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x500) |
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| 35 | #define SAR_SECURE_RAM_SIZE_OFFSET (SAR_BANK3_OFFSET + 0x504) |
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| 36 | #define SAR_SECRAM_SAVED_AT_OFFSET (SAR_BANK3_OFFSET + 0x508) |
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| 37 | |
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| 38 | /* WakeUpGen save restore offset from OMAP44XX_SAR_RAM_BASE */ |
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| 39 | #define WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x684) |
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| 40 | #define WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x694) |
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| 41 | #define WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x6a4) |
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| 42 | #define WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x6b4) |
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| 43 | #define AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0x6c4) |
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| 44 | #define AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x6c8) |
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| 45 | #define PTMSYNCREQ_MASK_OFFSET (SAR_BANK3_OFFSET + 0x6cc) |
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| 46 | #define PTMSYNCREQ_EN_OFFSET (SAR_BANK3_OFFSET + 0x6d0) |
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| 47 | #define SAR_BACKUP_STATUS_WAKEUPGEN 0x10 |
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| 48 | |
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| 49 | /* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */ |
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| 50 | #define OMAP5_WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x9dc) |
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| 51 | #define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x9f0) |
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| 52 | #define OMAP5_WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0xa04) |
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| 53 | #define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0xa18) |
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| 54 | #define OMAP5_AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0xa2c) |
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| 55 | #define OMAP5_AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x930) |
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| 56 | #define OMAP5_AMBA_IF_MODE_OFFSET (SAR_BANK3_OFFSET + 0xa34) |
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| 57 | #define OMAP5_SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x800) |
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| 58 | |
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| 59 | #endif |
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| 60 | |
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