| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /*: |
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| 3 | * Address mappings and base address for OMAP5 interconnects |
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| 4 | * and peripherals. |
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| 5 | * |
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| 6 | * Copyright (C) 2012 Texas Instruments |
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| 7 | * Santosh Shilimkar <santosh.shilimkar@ti.com> |
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| 8 | * Sricharan <r.sricharan@ti.com> |
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| 9 | */ |
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| 10 | #ifndef __ASM_SOC_OMAP54XX_H |
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| 11 | #define __ASM_SOC_OMAP54XX_H |
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| 12 | |
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| 13 | /* |
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| 14 | * Please place only base defines here and put the rest in device |
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| 15 | * specific headers. |
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| 16 | */ |
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| 17 | #define L4_54XX_BASE 0x4a000000 |
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| 18 | #define L4_WK_54XX_BASE 0x4ae00000 |
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| 19 | #define L4_PER_54XX_BASE 0x48000000 |
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| 20 | #define L3_54XX_BASE 0x44000000 |
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| 21 | #define OMAP54XX_32KSYNCT_BASE 0x4ae04000 |
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| 22 | #define OMAP54XX_CM_CORE_AON_BASE 0x4a004000 |
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| 23 | #define OMAP54XX_CM_CORE_BASE 0x4a008000 |
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| 24 | #define OMAP54XX_PRM_BASE 0x4ae06000 |
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| 25 | #define OMAP54XX_PRCM_MPU_BASE 0x48243000 |
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| 26 | #define OMAP54XX_SCM_BASE 0x4a002000 |
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| 27 | #define OMAP54XX_CTRL_BASE 0x4a002800 |
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| 28 | #define OMAP54XX_SAR_RAM_BASE 0x4ae26000 |
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| 29 | |
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| 30 | /* DRA7 specific base addresses */ |
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| 31 | #define L3_MAIN_SN_DRA7XX_BASE 0x44000000 |
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| 32 | #define L4_PER1_DRA7XX_BASE 0x48000000 |
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| 33 | #define L4_CFG_MPU_DRA7XX_BASE 0x48210000 |
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| 34 | #define L4_PER2_DRA7XX_BASE 0x48400000 |
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| 35 | #define L4_PER3_DRA7XX_BASE 0x48800000 |
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| 36 | #define L4_CFG_DRA7XX_BASE 0x4A000000 |
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| 37 | #define L4_WKUP_DRA7XX_BASE 0x4ae00000 |
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| 38 | #define DRA7XX_CM_CORE_AON_BASE 0x4a005000 |
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| 39 | #define DRA7XX_CTRL_BASE 0x4a003400 |
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| 40 | #define DRA7XX_TAP_BASE 0x4ae0c000 |
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| 41 | |
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| 42 | #endif /* __ASM_SOC_OMAP555554XX_H */ |
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| 43 | |
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