1	// SPDX-License-Identifier: GPL-2.0-only
2	/*
3	* omap_hwmod implementation for OMAP2/3/4
4	*
5	* Copyright (C) 2009-2011 Nokia Corporation
6	* Copyright (C) 2011-2012 Texas Instruments, Inc.
7	*
8	* Paul Walmsley, Benoît Cousson, Kevin Hilman
9	*
10	* Created in collaboration with (alphabetical order): Thara Gopinath,
11	* Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari Poussa, Anand
12	* Sawant, Santosh Shilimkar, Richard Woodruff
13	*
14	* Introduction
15	* ------------
16	* One way to view an OMAP SoC is as a collection of largely unrelated
17	* IP blocks connected by interconnects. The IP blocks include
18	* devices such as ARM processors, audio serial interfaces, UARTs,
19	* etc. Some of these devices, like the DSP, are created by TI;
20	* others, like the SGX, largely originate from external vendors. In
21	* TI's documentation, on-chip devices are referred to as "OMAP
22	* modules." Some of these IP blocks are identical across several
23	* OMAP versions. Others are revised frequently.
24	*
25	* These OMAP modules are tied together by various interconnects.
26	* Most of the address and data flow between modules is via OCP-based
27	* interconnects such as the L3 and L4 buses; but there are other
28	* interconnects that distribute the hardware clock tree, handle idle
29	* and reset signaling, supply power, and connect the modules to
30	* various pads or balls on the OMAP package.
31	*
32	* OMAP hwmod provides a consistent way to describe the on-chip
33	* hardware blocks and their integration into the rest of the chip.
34	* This description can be automatically generated from the TI
35	* hardware database. OMAP hwmod provides a standard, consistent API
36	* to reset, enable, idle, and disable these hardware blocks. And
37	* hwmod provides a way for other core code, such as the Linux device
38	* code or the OMAP power management and address space mapping code,
39	* to query the hardware database.
40	*
41	* Using hwmod
42	* -----------
43	* Drivers won't call hwmod functions directly. That is done by the
44	* omap_device code, and in rare occasions, by custom integration code
45	* in arch/arm/ *omap*. The omap_device code includes functions to
46	* build a struct platform_device using omap_hwmod data, and that is
47	* currently how hwmod data is communicated to drivers and to the
48	* Linux driver model. Most drivers will call omap_hwmod functions only
49	* indirectly, via pm_runtime*() functions.
50	*
51	* From a layering perspective, here is where the OMAP hwmod code
52	* fits into the kernel software stack:
53	*
54	* +-------------------------------+
55	* | Device driver code |
56	* | (e.g., drivers/) |
57	* +-------------------------------+
58	* | Linux driver model |
59	* | (platform_device / |
60	* | platform_driver data/code) |
61	* +-------------------------------+
62	* | OMAP core-driver integration |
63	* |(arch/arm/mach-omap2/devices.c)|
64	* +-------------------------------+
65	* | omap_device code |
66	* | (../plat-omap/omap_device.c) |
67	* +-------------------------------+
68	* ----> | omap_hwmod code/data | <-----
69	* | (../mach-omap2/omap_hwmod*) |
70	* +-------------------------------+
71	* | OMAP clock/PRCM/register fns |
72	* | ({read,write}l_relaxed, clk*) |
73	* +-------------------------------+
74	*
75	* Device drivers should not contain any OMAP-specific code or data in
76	* them. They should only contain code to operate the IP block that
77	* the driver is responsible for. This is because these IP blocks can
78	* also appear in other SoCs, either from TI (such as DaVinci) or from
79	* other manufacturers; and drivers should be reusable across other
80	* platforms.
81	*
82	* The OMAP hwmod code also will attempt to reset and idle all on-chip
83	* devices upon boot. The goal here is for the kernel to be
84	* completely self-reliant and independent from bootloaders. This is
85	* to ensure a repeatable configuration, both to ensure consistent
86	* runtime behavior, and to make it easier for others to reproduce
87	* bugs.
88	*
89	* OMAP module activity states
90	* ---------------------------
91	* The hwmod code considers modules to be in one of several activity
92	* states. IP blocks start out in an UNKNOWN state, then once they
93	* are registered via the hwmod code, proceed to the REGISTERED state.
94	* Once their clock names are resolved to clock pointers, the module
95	* enters the CLKS_INITED state; and finally, once the module has been
96	* reset and the integration registers programmed, the INITIALIZED state
97	* is entered. The hwmod code will then place the module into either
98	* the IDLE state to save power, or in the case of a critical system
99	* module, the ENABLED state.
100	*
101	* OMAP core integration code can then call omap_hwmod*() functions
102	* directly to move the module between the IDLE, ENABLED, and DISABLED
103	* states, as needed. This is done during both the PM idle loop, and
104	* in the OMAP core integration code's implementation of the PM runtime
105	* functions.
106	*
107	* References
108	* ----------
109	* This is a partial list.
110	* - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064)
111	* - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090)
112	* - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108)
113	* - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140)
114	* - Open Core Protocol Specification 2.2
115	*
116	* To do:
117	* - handle IO mapping
118	* - bus throughput & module latency measurement code
119	*
120	* XXX add tests at the beginning of each function to ensure the hwmod is
121	* in the appropriate state
122	* XXX error return values should be checked to ensure that they are
123	* appropriate
124	*/
125	#undef DEBUG
126
127	#include <linux/kernel.h>
128	#include <linux/errno.h>
129	#include <linux/io.h>
130	#include <linux/clk.h>
131	#include <linux/clk-provider.h>
132	#include <linux/delay.h>
133	#include <linux/err.h>
134	#include <linux/list.h>
135	#include <linux/mutex.h>
136	#include <linux/spinlock.h>
137	#include <linux/slab.h>
138	#include <linux/cpu.h>
139	#include <linux/of.h>
140	#include <linux/of_address.h>
141	#include <linux/memblock.h>
142
143	#include <linux/platform_data/ti-sysc.h>
144
145	#include <dt-bindings/bus/ti-sysc.h>
146
147	#include <asm/system_misc.h>
148
149	#include "clock.h"
150	#include "omap_hwmod.h"
151
152	#include "soc.h"
153	#include "common.h"
154	#include "clockdomain.h"
155	#include "hdq1w.h"
156	#include "mmc.h"
157	#include "powerdomain.h"
158	#include "cm2xxx.h"
159	#include "cm3xxx.h"
160	#include "cm33xx.h"
161	#include "prm.h"
162	#include "prm3xxx.h"
163	#include "prm44xx.h"
164	#include "prm33xx.h"
165	#include "prminst44xx.h"
166	#include "pm.h"
167	#include "wd_timer.h"
168
169	/* Name of the OMAP hwmod for the MPU */
170	#define MPU_INITIATOR_NAME "mpu"
171
172	/*
173	* Number of struct omap_hwmod_link records per struct
174	* omap_hwmod_ocp_if record (master->slave and slave->master)
175	*/
176	#define LINKS_PER_OCP_IF 2
177
178	/*
179	* Address offset (in bytes) between the reset control and the reset
180	* status registers: 4 bytes on OMAP4
181	*/
182	#define OMAP4_RST_CTRL_ST_OFFSET 4
183
184	/*
185	* Maximum length for module clock handle names
186	*/
187	#define MOD_CLK_MAX_NAME_LEN 32
188
189	/**
190	* struct clkctrl_provider - clkctrl provider mapping data
191	* @num_addrs: number of base address ranges for the provider
192	* @addr: base address(es) for the provider
193	* @size: size(s) of the provider address space(s)
194	* @node: device node associated with the provider
195	* @link: list link
196	*/
197	struct clkctrl_provider {
198	int num_addrs;
199	u32 *addr;
200	u32 *size;
201	struct device_node *node;
202	struct list_head link;
203	};
204
205	static LIST_HEAD(clkctrl_providers);
206
207	/**
208	* struct omap_hwmod_reset - IP specific reset functions
209	* @match: string to match against the module name
210	* @len: number of characters to match
211	* @reset: IP specific reset function
212	*
213	* Used only in cases where struct omap_hwmod is dynamically allocated.
214	*/
215	struct omap_hwmod_reset {
216	const char *match;
217	int len;
218	int (*reset)(struct omap_hwmod *oh);
219	};
220
221	/**
222	* struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations
223	* @enable_module: function to enable a module (via MODULEMODE)
224	* @disable_module: function to disable a module (via MODULEMODE)
225	*
226	* XXX Eventually this functionality will be hidden inside the PRM/CM
227	* device drivers. Until then, this should avoid huge blocks of cpu_is_*()
228	* conditionals in this code.
229	*/
230	struct omap_hwmod_soc_ops {
231	void (*enable_module)(struct omap_hwmod *oh);
232	int (*disable_module)(struct omap_hwmod *oh);
233	int (*wait_target_ready)(struct omap_hwmod *oh);
234	int (*assert_hardreset)(struct omap_hwmod *oh,
235	struct omap_hwmod_rst_info *ohri);
236	int (*deassert_hardreset)(struct omap_hwmod *oh,
237	struct omap_hwmod_rst_info *ohri);
238	int (*is_hardreset_asserted)(struct omap_hwmod *oh,
239	struct omap_hwmod_rst_info *ohri);
240	int (*init_clkdm)(struct omap_hwmod *oh);
241	void (*update_context_lost)(struct omap_hwmod *oh);
242	int (*get_context_lost)(struct omap_hwmod *oh);
243	int (*disable_direct_prcm)(struct omap_hwmod *oh);
244	u32 (*xlate_clkctrl)(struct omap_hwmod *oh);
245	};
246
247	/* soc_ops: adapts the omap_hwmod code to the currently-booted SoC */
248	static struct omap_hwmod_soc_ops soc_ops;
249
250	/* omap_hwmod_list contains all registered struct omap_hwmods */
251	static LIST_HEAD(omap_hwmod_list);
252	static DEFINE_MUTEX(list_lock);
253
254	/* mpu_oh: used to add/remove MPU initiator from sleepdep list */
255	static struct omap_hwmod *mpu_oh;
256
257	/* inited: set to true once the hwmod code is initialized */
258	static bool inited;
259
260	/* Private functions */
261
262	/**
263	* _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy
264	* @oh: struct omap_hwmod *
265	*
266	* Load the current value of the hwmod OCP_SYSCONFIG register into the
267	* struct omap_hwmod for later use. Returns -EINVAL if the hwmod has no
268	* OCP_SYSCONFIG register or 0 upon success.
269	*/
270	static int _update_sysc_cache(struct omap_hwmod *oh)
271	{
272	if (!oh->class->sysc) {
273	WARN(1, "omap_hwmod: %s: cannot read OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name);
274	return -EINVAL;
275	}
276
277	/* XXX ensure module interface clock is up */
278
279	oh->_sysc_cache = omap_hwmod_read(oh, oh->class->sysc->sysc_offs);
280
281	if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE))
282	oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED;
283
284	return 0;
285	}
286
287	/**
288	* _write_sysconfig - write a value to the module's OCP_SYSCONFIG register
289	* @v: OCP_SYSCONFIG value to write
290	* @oh: struct omap_hwmod *
291	*
292	* Write @v into the module class' OCP_SYSCONFIG register, if it has
293	* one. No return value.
294	*/
295	static void _write_sysconfig(u32 v, struct omap_hwmod *oh)
296	{
297	if (!oh->class->sysc) {
298	WARN(1, "omap_hwmod: %s: cannot write OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name);
299	return;
300	}
301
302	/* XXX ensure module interface clock is up */
303
304	/* Module might have lost context, always update cache and register */
305	oh->_sysc_cache = v;
306
307	/*
308	* Some IP blocks (such as RTC) require unlocking of IP before
309	* accessing its registers. If a function pointer is present
310	* to unlock, then call it before accessing sysconfig and
311	* call lock after writing sysconfig.
312	*/
313	if (oh->class->unlock)
314	oh->class->unlock(oh);
315
316	omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs);
317
318	if (oh->class->lock)
319	oh->class->lock(oh);
320	}
321
322	/**
323	* _set_master_standbymode: set the OCP_SYSCONFIG MIDLEMODE field in @v
324	* @oh: struct omap_hwmod *
325	* @standbymode: MIDLEMODE field bits
326	* @v: pointer to register contents to modify
327	*
328	* Update the master standby mode bits in @v to be @standbymode for
329	* the @oh hwmod. Does not write to the hardware. Returns -EINVAL
330	* upon error or 0 upon success.
331	*/
332	static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode,
333	u32 *v)
334	{
335	u32 mstandby_mask;
336	u8 mstandby_shift;
337
338	if (!oh->class->sysc ||
339	!(oh->class->sysc->sysc_flags & SYSC_HAS_MIDLEMODE))
340	return -EINVAL;
341
342	if (!oh->class->sysc->sysc_fields) {
343	WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
344	return -EINVAL;
345	}
346
347	mstandby_shift = oh->class->sysc->sysc_fields->midle_shift;
348	mstandby_mask = (0x3 << mstandby_shift);
349
350	*v &= ~mstandby_mask;
351	*v |= __ffs(standbymode) << mstandby_shift;
352
353	return 0;
354	}
355
356	/**
357	* _set_slave_idlemode: set the OCP_SYSCONFIG SIDLEMODE field in @v
358	* @oh: struct omap_hwmod *
359	* @idlemode: SIDLEMODE field bits
360	* @v: pointer to register contents to modify
361	*
362	* Update the slave idle mode bits in @v to be @idlemode for the @oh
363	* hwmod. Does not write to the hardware. Returns -EINVAL upon error
364	* or 0 upon success.
365	*/
366	static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v)
367	{
368	u32 sidle_mask;
369	u8 sidle_shift;
370
371	if (!oh->class->sysc ||
372	!(oh->class->sysc->sysc_flags & SYSC_HAS_SIDLEMODE))
373	return -EINVAL;
374
375	if (!oh->class->sysc->sysc_fields) {
376	WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
377	return -EINVAL;
378	}
379
380	sidle_shift = oh->class->sysc->sysc_fields->sidle_shift;
381	sidle_mask = (0x3 << sidle_shift);
382
383	*v &= ~sidle_mask;
384	*v |= __ffs(idlemode) << sidle_shift;
385
386	return 0;
387	}
388
389	/**
390	* _set_clockactivity: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v
391	* @oh: struct omap_hwmod *
392	* @clockact: CLOCKACTIVITY field bits
393	* @v: pointer to register contents to modify
394	*
395	* Update the clockactivity mode bits in @v to be @clockact for the
396	* @oh hwmod. Used for additional powersaving on some modules. Does
397	* not write to the hardware. Returns -EINVAL upon error or 0 upon
398	* success.
399	*/
400	static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v)
401	{
402	u32 clkact_mask;
403	u8 clkact_shift;
404
405	if (!oh->class->sysc ||
406	!(oh->class->sysc->sysc_flags & SYSC_HAS_CLOCKACTIVITY))
407	return -EINVAL;
408
409	if (!oh->class->sysc->sysc_fields) {
410	WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
411	return -EINVAL;
412	}
413
414	clkact_shift = oh->class->sysc->sysc_fields->clkact_shift;
415	clkact_mask = (0x3 << clkact_shift);
416
417	*v &= ~clkact_mask;
418	*v |= clockact << clkact_shift;
419
420	return 0;
421	}
422
423	/**
424	* _set_softreset: set OCP_SYSCONFIG.SOFTRESET bit in @v
425	* @oh: struct omap_hwmod *
426	* @v: pointer to register contents to modify
427	*
428	* Set the SOFTRESET bit in @v for hwmod @oh. Returns -EINVAL upon
429	* error or 0 upon success.
430	*/
431	static int _set_softreset(struct omap_hwmod *oh, u32 *v)
432	{
433	u32 softrst_mask;
434
435	if (!oh->class->sysc ||
436	!(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET))
437	return -EINVAL;
438
439	if (!oh->class->sysc->sysc_fields) {
440	WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
441	return -EINVAL;
442	}
443
444	softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift);
445
446	*v |= softrst_mask;
447
448	return 0;
449	}
450
451	/**
452	* _clear_softreset: clear OCP_SYSCONFIG.SOFTRESET bit in @v
453	* @oh: struct omap_hwmod *
454	* @v: pointer to register contents to modify
455	*
456	* Clear the SOFTRESET bit in @v for hwmod @oh. Returns -EINVAL upon
457	* error or 0 upon success.
458	*/
459	static int _clear_softreset(struct omap_hwmod *oh, u32 *v)
460	{
461	u32 softrst_mask;
462
463	if (!oh->class->sysc ||
464	!(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET))
465	return -EINVAL;
466
467	if (!oh->class->sysc->sysc_fields) {
468	WARN(1,
469	"omap_hwmod: %s: sysc_fields absent for sysconfig class\n",
470	oh->name);
471	return -EINVAL;
472	}
473
474	softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift);
475
476	*v &= ~softrst_mask;
477
478	return 0;
479	}
480
481	/**
482	* _wait_softreset_complete - wait for an OCP softreset to complete
483	* @oh: struct omap_hwmod * to wait on
484	*
485	* Wait until the IP block represented by @oh reports that its OCP
486	* softreset is complete. This can be triggered by software (see
487	* _ocp_softreset()) or by hardware upon returning from off-mode (one
488	* example is HSMMC). Waits for up to MAX_MODULE_SOFTRESET_WAIT
489	* microseconds. Returns the number of microseconds waited.
490	*/
491	static int _wait_softreset_complete(struct omap_hwmod *oh)
492	{
493	struct omap_hwmod_class_sysconfig *sysc;
494	u32 softrst_mask;
495	int c = 0;
496
497	sysc = oh->class->sysc;
498
499	if (sysc->sysc_flags & SYSS_HAS_RESET_STATUS && sysc->syss_offs > 0)
500	omap_test_timeout((omap_hwmod_read(oh, sysc->syss_offs)
501	& SYSS_RESETDONE_MASK),
502	MAX_MODULE_SOFTRESET_WAIT, c);
503	else if (sysc->sysc_flags & SYSC_HAS_RESET_STATUS) {
504	softrst_mask = (0x1 << sysc->sysc_fields->srst_shift);
505	omap_test_timeout(!(omap_hwmod_read(oh, sysc->sysc_offs)
506	& softrst_mask),
507	MAX_MODULE_SOFTRESET_WAIT, c);
508	}
509
510	return c;
511	}
512
513	/**
514	* _set_dmadisable: set OCP_SYSCONFIG.DMADISABLE bit in @v
515	* @oh: struct omap_hwmod *
516	*
517	* The DMADISABLE bit is a semi-automatic bit present in sysconfig register
518	* of some modules. When the DMA must perform read/write accesses, the
519	* DMADISABLE bit is cleared by the hardware. But when the DMA must stop
520	* for power management, software must set the DMADISABLE bit back to 1.
521	*
522	* Set the DMADISABLE bit in @v for hwmod @oh. Returns -EINVAL upon
523	* error or 0 upon success.
524	*/
525	static int _set_dmadisable(struct omap_hwmod *oh)
526	{
527	u32 v;
528	u32 dmadisable_mask;
529
530	if (!oh->class->sysc ||
531	!(oh->class->sysc->sysc_flags & SYSC_HAS_DMADISABLE))
532	return -EINVAL;
533
534	if (!oh->class->sysc->sysc_fields) {
535	WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
536	return -EINVAL;
537	}
538
539	/* clocks must be on for this operation */
540	if (oh->_state != _HWMOD_STATE_ENABLED) {
541	pr_warn("omap_hwmod: %s: dma can be disabled only from enabled state\n", oh->name);
542	return -EINVAL;
543	}
544
545	pr_debug("omap_hwmod: %s: setting DMADISABLE\n", oh->name);
546
547	v = oh->_sysc_cache;
548	dmadisable_mask =
549	(0x1 << oh->class->sysc->sysc_fields->dmadisable_shift);
550	v |= dmadisable_mask;
551	_write_sysconfig(v, oh);
552
553	return 0;
554	}
555
556	/**
557	* _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v
558	* @oh: struct omap_hwmod *
559	* @autoidle: desired AUTOIDLE bitfield value (0 or 1)
560	* @v: pointer to register contents to modify
561	*
562	* Update the module autoidle bit in @v to be @autoidle for the @oh
563	* hwmod. The autoidle bit controls whether the module can gate
564	* internal clocks automatically when it isn't doing anything; the
565	* exact function of this bit varies on a per-module basis. This
566	* function does not write to the hardware. Returns -EINVAL upon
567	* error or 0 upon success.
568	*/
569	static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
570	u32 *v)
571	{
572	u32 autoidle_mask;
573	u8 autoidle_shift;
574
575	if (!oh->class->sysc ||
576	!(oh->class->sysc->sysc_flags & SYSC_HAS_AUTOIDLE))
577	return -EINVAL;
578
579	if (!oh->class->sysc->sysc_fields) {
580	WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
581	return -EINVAL;
582	}
583
584	autoidle_shift = oh->class->sysc->sysc_fields->autoidle_shift;
585	autoidle_mask = (0x1 << autoidle_shift);
586
587	*v &= ~autoidle_mask;
588	*v |= autoidle << autoidle_shift;
589
590	return 0;
591	}
592
593	/**
594	* _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware
595	* @oh: struct omap_hwmod *
596	*
597	* Allow the hardware module @oh to send wakeups. Returns -EINVAL
598	* upon error or 0 upon success.
599	*/
600	static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
601	{
602	if (!oh->class->sysc ||
603	!((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
604	(oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) ||
605	(oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)))
606	return -EINVAL;
607
608	if (!oh->class->sysc->sysc_fields) {
609	WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
610	return -EINVAL;
611	}
612
613	if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)
614	*v |= 0x1 << oh->class->sysc->sysc_fields->enwkup_shift;
615
616	if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
617	_set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
618	if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
619	_set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
620
621	/* XXX test pwrdm_get_wken for this hwmod's subsystem */
622
623	return 0;
624	}
625
626	static struct clockdomain *_get_clkdm(struct omap_hwmod *oh)
627	{
628	struct clk_hw_omap *clk;
629
630	if (!oh)
631	return NULL;
632
633	if (oh->clkdm) {
634	return oh->clkdm;
635	} else if (oh->_clk) {
636	if (!omap2_clk_is_hw_omap(hw: __clk_get_hw(clk: oh->_clk)))
637	return NULL;
638	clk = to_clk_hw_omap(__clk_get_hw(oh->_clk));
639	return clk->clkdm;
640	}
641	return NULL;
642	}
643
644	/**
645	* _add_initiator_dep: prevent @oh from smart-idling while @init_oh is active
646	* @oh: struct omap_hwmod *
647	*
648	* Prevent the hardware module @oh from entering idle while the
649	* hardare module initiator @init_oh is active. Useful when a module
650	* will be accessed by a particular initiator (e.g., if a module will
651	* be accessed by the IVA, there should be a sleepdep between the IVA
652	* initiator and the module). Only applies to modules in smart-idle
653	* mode. If the clockdomain is marked as not needing autodeps, return
654	* 0 without doing anything. Otherwise, returns -EINVAL upon error or
655	* passes along clkdm_add_sleepdep() value upon success.
656	*/
657	static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
658	{
659	struct clockdomain *clkdm, *init_clkdm;
660
661	clkdm = _get_clkdm(oh);
662	init_clkdm = _get_clkdm(oh: init_oh);
663
664	if (!clkdm || !init_clkdm)
665	return -EINVAL;
666
667	if (clkdm && clkdm->flags & CLKDM_NO_AUTODEPS)
668	return 0;
669
670	return clkdm_add_sleepdep(clkdm1: clkdm, clkdm2: init_clkdm);
671	}
672
673	/**
674	* _del_initiator_dep: allow @oh to smart-idle even if @init_oh is active
675	* @oh: struct omap_hwmod *
676	*
677	* Allow the hardware module @oh to enter idle while the hardare
678	* module initiator @init_oh is active. Useful when a module will not
679	* be accessed by a particular initiator (e.g., if a module will not
680	* be accessed by the IVA, there should be no sleepdep between the IVA
681	* initiator and the module). Only applies to modules in smart-idle
682	* mode. If the clockdomain is marked as not needing autodeps, return
683	* 0 without doing anything. Returns -EINVAL upon error or passes
684	* along clkdm_del_sleepdep() value upon success.
685	*/
686	static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
687	{
688	struct clockdomain *clkdm, *init_clkdm;
689
690	clkdm = _get_clkdm(oh);
691	init_clkdm = _get_clkdm(oh: init_oh);
692
693	if (!clkdm || !init_clkdm)
694	return -EINVAL;
695
696	if (clkdm && clkdm->flags & CLKDM_NO_AUTODEPS)
697	return 0;
698
699	return clkdm_del_sleepdep(clkdm1: clkdm, clkdm2: init_clkdm);
700	}
701
702	static const struct of_device_id ti_clkctrl_match_table[] __initconst = {
703	{ .compatible = "ti,clkctrl" },
704	{ }
705	};
706
707	static int __init _setup_clkctrl_provider(struct device_node *np)
708	{
709	struct clkctrl_provider *provider;
710	int i;
711
712	provider = memblock_alloc(size: sizeof(*provider), SMP_CACHE_BYTES);
713	if (!provider)
714	return -ENOMEM;
715
716	provider->node = np;
717
718	provider->num_addrs = of_address_count(np);
719
720	provider->addr =
721	memblock_alloc(size: sizeof(void *) * provider->num_addrs,
722	SMP_CACHE_BYTES);
723	if (!provider->addr)
724	return -ENOMEM;
725
726	provider->size =
727	memblock_alloc(size: sizeof(u32) * provider->num_addrs,
728	SMP_CACHE_BYTES);
729	if (!provider->size)
730	return -ENOMEM;
731
732	for (i = 0; i < provider->num_addrs; i++) {
733	struct resource res;
734	of_address_to_resource(dev: np, index: i, r: &res);
735	provider->addr[i] = res.start;
736	provider->size[i] = resource_size(res: &res);
737	pr_debug("%s: %pOF: %pR\n", __func__, np, &res);
738	}
739
740	list_add(new: &provider->link, head: &clkctrl_providers);
741
742	return 0;
743	}
744
745	static int __init _init_clkctrl_providers(void)
746	{
747	struct device_node *np;
748	int ret = 0;
749
750	for_each_matching_node(np, ti_clkctrl_match_table) {
751	ret = _setup_clkctrl_provider(np);
752	if (ret) {
753	of_node_put(node: np);
754	break;
755	}
756	}
757
758	return ret;
759	}
760
761	static u32 _omap4_xlate_clkctrl(struct omap_hwmod *oh)
762	{
763	if (!oh->prcm.omap4.modulemode)
764	return 0;
765
766	return omap_cm_xlate_clkctrl(part: oh->clkdm->prcm_partition,
767	inst: oh->clkdm->cm_inst,
768	clkctrl_offs: oh->prcm.omap4.clkctrl_offs);
769	}
770
771	static struct clk *_lookup_clkctrl_clk(struct omap_hwmod *oh)
772	{
773	struct clkctrl_provider *provider;
774	struct clk *clk;
775	u32 addr;
776
777	if (!soc_ops.xlate_clkctrl)
778	return NULL;
779
780	addr = soc_ops.xlate_clkctrl(oh);
781	if (!addr)
782	return NULL;
783
784	pr_debug("%s: %s: addr=%x\n", __func__, oh->name, addr);
785
786	list_for_each_entry(provider, &clkctrl_providers, link) {
787	int i;
788
789	for (i = 0; i < provider->num_addrs; i++) {
790	if (provider->addr[i] <= addr &&
791	provider->addr[i] + provider->size[i] > addr) {
792	struct of_phandle_args clkspec;
793
794	clkspec.np = provider->node;
795	clkspec.args_count = 2;
796	clkspec.args[0] = addr - provider->addr[0];
797	clkspec.args[1] = 0;
798
799	clk = of_clk_get_from_provider(clkspec: &clkspec);
800
801	pr_debug("%s: %s got %p (offset=%x, provider=%pOF)\n",
802	__func__, oh->name, clk,
803	clkspec.args[0], provider->node);
804
805	return clk;
806	}
807	}
808	}
809
810	return NULL;
811	}
812
813	/**
814	* _init_main_clk - get a struct clk * for the hwmod's main functional clk
815	* @oh: struct omap_hwmod *
816	*
817	* Called from _init_clocks(). Populates the @oh _clk (main
818	* functional clock pointer) if a clock matching the hwmod name is found,
819	* or a main_clk is present. Returns 0 on success or -EINVAL on error.
820	*/
821	static int _init_main_clk(struct omap_hwmod *oh)
822	{
823	int ret = 0;
824	struct clk *clk = NULL;
825
826	clk = _lookup_clkctrl_clk(oh);
827
828	if (!IS_ERR_OR_NULL(ptr: clk)) {
829	pr_debug("%s: mapped main_clk %s for %s\n", __func__,
830	__clk_get_name(clk), oh->name);
831	oh->main_clk = __clk_get_name(clk);
832	oh->_clk = clk;
833	soc_ops.disable_direct_prcm(oh);
834	} else {
835	if (!oh->main_clk)
836	return 0;
837
838	oh->_clk = clk_get(NULL, id: oh->main_clk);
839	}
840
841	if (IS_ERR(ptr: oh->_clk)) {
842	pr_warn("omap_hwmod: %s: cannot clk_get main_clk %s\n",
843	oh->name, oh->main_clk);
844	return -EINVAL;
845	}
846	/*
847	* HACK: This needs a re-visit once clk_prepare() is implemented
848	* to do something meaningful. Today its just a no-op.
849	* If clk_prepare() is used at some point to do things like
850	* voltage scaling etc, then this would have to be moved to
851	* some point where subsystems like i2c and pmic become
852	* available.
853	*/
854	clk_prepare(clk: oh->_clk);
855
856	if (!_get_clkdm(oh))
857	pr_debug("omap_hwmod: %s: missing clockdomain for %s.\n",
858	oh->name, oh->main_clk);
859
860	return ret;
861	}
862
863	/**
864	* _init_interface_clks - get a struct clk * for the hwmod's interface clks
865	* @oh: struct omap_hwmod *
866	*
867	* Called from _init_clocks(). Populates the @oh OCP slave interface
868	* clock pointers. Returns 0 on success or -EINVAL on error.
869	*/
870	static int _init_interface_clks(struct omap_hwmod *oh)
871	{
872	struct omap_hwmod_ocp_if *os;
873	struct clk *c;
874	int ret = 0;
875
876	list_for_each_entry(os, &oh->slave_ports, node) {
877	if (!os->clk)
878	continue;
879
880	c = clk_get(NULL, id: os->clk);
881	if (IS_ERR(ptr: c)) {
882	pr_warn("omap_hwmod: %s: cannot clk_get interface_clk %s\n",
883	oh->name, os->clk);
884	ret = -EINVAL;
885	continue;
886	}
887	os->_clk = c;
888	/*
889	* HACK: This needs a re-visit once clk_prepare() is implemented
890	* to do something meaningful. Today its just a no-op.
891	* If clk_prepare() is used at some point to do things like
892	* voltage scaling etc, then this would have to be moved to
893	* some point where subsystems like i2c and pmic become
894	* available.
895	*/
896	clk_prepare(clk: os->_clk);
897	}
898
899	return ret;
900	}
901
902	/**
903	* _init_opt_clk - get a struct clk * for the hwmod's optional clocks
904	* @oh: struct omap_hwmod *
905	*
906	* Called from _init_clocks(). Populates the @oh omap_hwmod_opt_clk
907	* clock pointers. Returns 0 on success or -EINVAL on error.
908	*/
909	static int _init_opt_clks(struct omap_hwmod *oh)
910	{
911	struct omap_hwmod_opt_clk *oc;
912	struct clk *c;
913	int i;
914	int ret = 0;
915
916	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) {
917	c = clk_get(NULL, id: oc->clk);
918	if (IS_ERR(ptr: c)) {
919	pr_warn("omap_hwmod: %s: cannot clk_get opt_clk %s\n",
920	oh->name, oc->clk);
921	ret = -EINVAL;
922	continue;
923	}
924	oc->_clk = c;
925	/*
926	* HACK: This needs a re-visit once clk_prepare() is implemented
927	* to do something meaningful. Today its just a no-op.
928	* If clk_prepare() is used at some point to do things like
929	* voltage scaling etc, then this would have to be moved to
930	* some point where subsystems like i2c and pmic become
931	* available.
932	*/
933	clk_prepare(clk: oc->_clk);
934	}
935
936	return ret;
937	}
938
939	static void _enable_optional_clocks(struct omap_hwmod *oh)
940	{
941	struct omap_hwmod_opt_clk *oc;
942	int i;
943
944	pr_debug("omap_hwmod: %s: enabling optional clocks\n", oh->name);
945
946	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
947	if (oc->_clk) {
948	pr_debug("omap_hwmod: enable %s:%s\n", oc->role,
949	__clk_get_name(oc->_clk));
950	clk_enable(clk: oc->_clk);
951	}
952	}
953
954	static void _disable_optional_clocks(struct omap_hwmod *oh)
955	{
956	struct omap_hwmod_opt_clk *oc;
957	int i;
958
959	pr_debug("omap_hwmod: %s: disabling optional clocks\n", oh->name);
960
961	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
962	if (oc->_clk) {
963	pr_debug("omap_hwmod: disable %s:%s\n", oc->role,
964	__clk_get_name(oc->_clk));
965	clk_disable(clk: oc->_clk);
966	}
967	}
968
969	/**
970	* _enable_clocks - enable hwmod main clock and interface clocks
971	* @oh: struct omap_hwmod *
972	*
973	* Enables all clocks necessary for register reads and writes to succeed
974	* on the hwmod @oh. Returns 0.
975	*/
976	static int _enable_clocks(struct omap_hwmod *oh)
977	{
978	struct omap_hwmod_ocp_if *os;
979
980	pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name);
981
982	if (oh->flags & HWMOD_OPT_CLKS_NEEDED)
983	_enable_optional_clocks(oh);
984
985	if (oh->_clk)
986	clk_enable(clk: oh->_clk);
987
988	list_for_each_entry(os, &oh->slave_ports, node) {
989	if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) {
990	omap2_clk_deny_idle(clk: os->_clk);
991	clk_enable(clk: os->_clk);
992	}
993	}
994
995	/* The opt clocks are controlled by the device driver. */
996
997	return 0;
998	}
999
1000	/**
1001	* _omap4_clkctrl_managed_by_clkfwk - true if clkctrl managed by clock framework
1002	* @oh: struct omap_hwmod *
1003	*/
1004	static bool _omap4_clkctrl_managed_by_clkfwk(struct omap_hwmod *oh)
1005	{
1006	if (oh->prcm.omap4.flags & HWMOD_OMAP4_CLKFWK_CLKCTR_CLOCK)
1007	return true;
1008
1009	return false;
1010	}
1011
1012	/**
1013	* _omap4_has_clkctrl_clock - returns true if a module has clkctrl clock
1014	* @oh: struct omap_hwmod *
1015	*/
1016	static bool _omap4_has_clkctrl_clock(struct omap_hwmod *oh)
1017	{
1018	if (oh->prcm.omap4.clkctrl_offs)
1019	return true;
1020
1021	if (!oh->prcm.omap4.clkctrl_offs &&
1022	oh->prcm.omap4.flags & HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET)
1023	return true;
1024
1025	return false;
1026	}
1027
1028	/**
1029	* _disable_clocks - disable hwmod main clock and interface clocks
1030	* @oh: struct omap_hwmod *
1031	*
1032	* Disables the hwmod @oh main functional and interface clocks. Returns 0.
1033	*/
1034	static int _disable_clocks(struct omap_hwmod *oh)
1035	{
1036	struct omap_hwmod_ocp_if *os;
1037
1038	pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name);
1039
1040	if (oh->_clk)
1041	clk_disable(clk: oh->_clk);
1042
1043	list_for_each_entry(os, &oh->slave_ports, node) {
1044	if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) {
1045	clk_disable(clk: os->_clk);
1046	omap2_clk_allow_idle(clk: os->_clk);
1047	}
1048	}
1049
1050	if (oh->flags & HWMOD_OPT_CLKS_NEEDED)
1051	_disable_optional_clocks(oh);
1052
1053	/* The opt clocks are controlled by the device driver. */
1054
1055	return 0;
1056	}
1057
1058	/**
1059	* _omap4_enable_module - enable CLKCTRL modulemode on OMAP4
1060	* @oh: struct omap_hwmod *
1061	*
1062	* Enables the PRCM module mode related to the hwmod @oh.
1063	* No return value.
1064	*/
1065	static void _omap4_enable_module(struct omap_hwmod *oh)
1066	{
1067	if (!oh->clkdm || !oh->prcm.omap4.modulemode ||
1068	_omap4_clkctrl_managed_by_clkfwk(oh))
1069	return;
1070
1071	pr_debug("omap_hwmod: %s: %s: %d\n",
1072	oh->name, __func__, oh->prcm.omap4.modulemode);
1073
1074	omap_cm_module_enable(mode: oh->prcm.omap4.modulemode,
1075	part: oh->clkdm->prcm_partition,
1076	inst: oh->clkdm->cm_inst, clkctrl_offs: oh->prcm.omap4.clkctrl_offs);
1077	}
1078
1079	/**
1080	* _omap4_wait_target_disable - wait for a module to be disabled on OMAP4
1081	* @oh: struct omap_hwmod *
1082	*
1083	* Wait for a module @oh to enter slave idle. Returns 0 if the module
1084	* does not have an IDLEST bit or if the module successfully enters
1085	* slave idle; otherwise, pass along the return value of the
1086	* appropriate *_cm*_wait_module_idle() function.
1087	*/
1088	static int _omap4_wait_target_disable(struct omap_hwmod *oh)
1089	{
1090	if (!oh)
1091	return -EINVAL;
1092
1093	if (oh->_int_flags & _HWMOD_NO_MPU_PORT || !oh->clkdm)
1094	return 0;
1095
1096	if (oh->flags & HWMOD_NO_IDLEST)
1097	return 0;
1098
1099	if (_omap4_clkctrl_managed_by_clkfwk(oh))
1100	return 0;
1101
1102	if (!_omap4_has_clkctrl_clock(oh))
1103	return 0;
1104
1105	return omap_cm_wait_module_idle(part: oh->clkdm->prcm_partition,
1106	prcm_mod: oh->clkdm->cm_inst,
1107	idlest_reg: oh->prcm.omap4.clkctrl_offs, idlest_shift: 0);
1108	}
1109
1110	/**
1111	* _save_mpu_port_index - find and save the index to @oh's MPU port
1112	* @oh: struct omap_hwmod *
1113	*
1114	* Determines the array index of the OCP slave port that the MPU uses
1115	* to address the device, and saves it into the struct omap_hwmod.
1116	* Intended to be called during hwmod registration only. No return
1117	* value.
1118	*/
1119	static void __init _save_mpu_port_index(struct omap_hwmod *oh)
1120	{
1121	struct omap_hwmod_ocp_if *os = NULL;
1122
1123	if (!oh)
1124	return;
1125
1126	oh->_int_flags |= _HWMOD_NO_MPU_PORT;
1127
1128	list_for_each_entry(os, &oh->slave_ports, node) {
1129	if (os->user & OCP_USER_MPU) {
1130	oh->_mpu_port = os;
1131	oh->_int_flags &= ~_HWMOD_NO_MPU_PORT;
1132	break;
1133	}
1134	}
1135
1136	return;
1137	}
1138
1139	/**
1140	* _find_mpu_rt_port - return omap_hwmod_ocp_if accessible by the MPU
1141	* @oh: struct omap_hwmod *
1142	*
1143	* Given a pointer to a struct omap_hwmod record @oh, return a pointer
1144	* to the struct omap_hwmod_ocp_if record that is used by the MPU to
1145	* communicate with the IP block. This interface need not be directly
1146	* connected to the MPU (and almost certainly is not), but is directly
1147	* connected to the IP block represented by @oh. Returns a pointer
1148	* to the struct omap_hwmod_ocp_if * upon success, or returns NULL upon
1149	* error or if there does not appear to be a path from the MPU to this
1150	* IP block.
1151	*/
1152	static struct omap_hwmod_ocp_if *_find_mpu_rt_port(struct omap_hwmod *oh)
1153	{
1154	if (!oh || oh->_int_flags & _HWMOD_NO_MPU_PORT || oh->slaves_cnt == 0)
1155	return NULL;
1156
1157	return oh->_mpu_port;
1158	};
1159
1160	/**
1161	* _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG
1162	* @oh: struct omap_hwmod *
1163	*
1164	* Ensure that the OCP_SYSCONFIG register for the IP block represented
1165	* by @oh is set to indicate to the PRCM that the IP block is active.
1166	* Usually this means placing the module into smart-idle mode and
1167	* smart-standby, but if there is a bug in the automatic idle handling
1168	* for the IP block, it may need to be placed into the force-idle or
1169	* no-idle variants of these modes. No return value.
1170	*/
1171	static void _enable_sysc(struct omap_hwmod *oh)
1172	{
1173	u8 idlemode, sf;
1174	u32 v;
1175	bool clkdm_act;
1176	struct clockdomain *clkdm;
1177
1178	if (!oh->class->sysc)
1179	return;
1180
1181	/*
1182	* Wait until reset has completed, this is needed as the IP
1183	* block is reset automatically by hardware in some cases
1184	* (off-mode for example), and the drivers require the
1185	* IP to be ready when they access it
1186	*/
1187	if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
1188	_enable_optional_clocks(oh);
1189	_wait_softreset_complete(oh);
1190	if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
1191	_disable_optional_clocks(oh);
1192
1193	v = oh->_sysc_cache;
1194	sf = oh->class->sysc->sysc_flags;
1195
1196	clkdm = _get_clkdm(oh);
1197	if (sf & SYSC_HAS_SIDLEMODE) {
1198	if (oh->flags & HWMOD_SWSUP_SIDLE ||
1199	oh->flags & HWMOD_SWSUP_SIDLE_ACT) {
1200	idlemode = HWMOD_IDLEMODE_NO;
1201	} else {
1202	if (sf & SYSC_HAS_ENAWAKEUP)
1203	_enable_wakeup(oh, v: &v);
1204	if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
1205	idlemode = HWMOD_IDLEMODE_SMART_WKUP;
1206	else
1207	idlemode = HWMOD_IDLEMODE_SMART;
1208	}
1209
1210	/*
1211	* This is special handling for some IPs like
1212	* 32k sync timer. Force them to idle!
1213	*/
1214	clkdm_act = (clkdm && clkdm->flags & CLKDM_ACTIVE_WITH_MPU);
1215	if (clkdm_act && !(oh->class->sysc->idlemodes &
1216	(SIDLE_SMART | SIDLE_SMART_WKUP)))
1217	idlemode = HWMOD_IDLEMODE_FORCE;
1218
1219	_set_slave_idlemode(oh, idlemode, v: &v);
1220	}
1221
1222	if (sf & SYSC_HAS_MIDLEMODE) {
1223	if (oh->flags & HWMOD_FORCE_MSTANDBY) {
1224	idlemode = HWMOD_IDLEMODE_FORCE;
1225	} else if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
1226	idlemode = HWMOD_IDLEMODE_NO;
1227	} else {
1228	if (sf & SYSC_HAS_ENAWAKEUP)
1229	_enable_wakeup(oh, v: &v);
1230	if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
1231	idlemode = HWMOD_IDLEMODE_SMART_WKUP;
1232	else
1233	idlemode = HWMOD_IDLEMODE_SMART;
1234	}
1235	_set_master_standbymode(oh, standbymode: idlemode, v: &v);
1236	}
1237
1238	/*
1239	* XXX The clock framework should handle this, by
1240	* calling into this code. But this must wait until the
1241	* clock structures are tagged with omap_hwmod entries
1242	*/
1243	if ((oh->flags & HWMOD_SET_DEFAULT_CLOCKACT) &&
1244	(sf & SYSC_HAS_CLOCKACTIVITY))
1245	_set_clockactivity(oh, CLOCKACT_TEST_ICLK, v: &v);
1246
1247	_write_sysconfig(v, oh);
1248
1249	/*
1250	* Set the autoidle bit only after setting the smartidle bit
1251	* Setting this will not have any impact on the other modules.
1252	*/
1253	if (sf & SYSC_HAS_AUTOIDLE) {
1254	idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ?
1255	0 : 1;
1256	_set_module_autoidle(oh, autoidle: idlemode, v: &v);
1257	_write_sysconfig(v, oh);
1258	}
1259	}
1260
1261	/**
1262	* _idle_sysc - try to put a module into idle via OCP_SYSCONFIG
1263	* @oh: struct omap_hwmod *
1264	*
1265	* If module is marked as SWSUP_SIDLE, force the module into slave
1266	* idle; otherwise, configure it for smart-idle. If module is marked
1267	* as SWSUP_MSUSPEND, force the module into master standby; otherwise,
1268	* configure it for smart-standby. No return value.
1269	*/
1270	static void _idle_sysc(struct omap_hwmod *oh)
1271	{
1272	u8 idlemode, sf;
1273	u32 v;
1274
1275	if (!oh->class->sysc)
1276	return;
1277
1278	v = oh->_sysc_cache;
1279	sf = oh->class->sysc->sysc_flags;
1280
1281	if (sf & SYSC_HAS_SIDLEMODE) {
1282	if (oh->flags & HWMOD_SWSUP_SIDLE) {
1283	idlemode = HWMOD_IDLEMODE_FORCE;
1284	} else {
1285	if (sf & SYSC_HAS_ENAWAKEUP)
1286	_enable_wakeup(oh, v: &v);
1287	if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
1288	idlemode = HWMOD_IDLEMODE_SMART_WKUP;
1289	else
1290	idlemode = HWMOD_IDLEMODE_SMART;
1291	}
1292	_set_slave_idlemode(oh, idlemode, v: &v);
1293	}
1294
1295	if (sf & SYSC_HAS_MIDLEMODE) {
1296	if ((oh->flags & HWMOD_SWSUP_MSTANDBY) ||
1297	(oh->flags & HWMOD_FORCE_MSTANDBY)) {
1298	idlemode = HWMOD_IDLEMODE_FORCE;
1299	} else {
1300	if (sf & SYSC_HAS_ENAWAKEUP)
1301	_enable_wakeup(oh, v: &v);
1302	if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
1303	idlemode = HWMOD_IDLEMODE_SMART_WKUP;
1304	else
1305	idlemode = HWMOD_IDLEMODE_SMART;
1306	}
1307	_set_master_standbymode(oh, standbymode: idlemode, v: &v);
1308	}
1309
1310	/* If the cached value is the same as the new value, skip the write */
1311	if (oh->_sysc_cache != v)
1312	_write_sysconfig(v, oh);
1313	}
1314
1315	/**
1316	* _shutdown_sysc - force a module into idle via OCP_SYSCONFIG
1317	* @oh: struct omap_hwmod *
1318	*
1319	* Force the module into slave idle and master suspend. No return
1320	* value.
1321	*/
1322	static void _shutdown_sysc(struct omap_hwmod *oh)
1323	{
1324	u32 v;
1325	u8 sf;
1326
1327	if (!oh->class->sysc)
1328	return;
1329
1330	v = oh->_sysc_cache;
1331	sf = oh->class->sysc->sysc_flags;
1332
1333	if (sf & SYSC_HAS_SIDLEMODE)
1334	_set_slave_idlemode(oh, HWMOD_IDLEMODE_FORCE, v: &v);
1335
1336	if (sf & SYSC_HAS_MIDLEMODE)
1337	_set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, v: &v);
1338
1339	if (sf & SYSC_HAS_AUTOIDLE)
1340	_set_module_autoidle(oh, autoidle: 1, v: &v);
1341
1342	_write_sysconfig(v, oh);
1343	}
1344
1345	/**
1346	* _lookup - find an omap_hwmod by name
1347	* @name: find an omap_hwmod by name
1348	*
1349	* Return a pointer to an omap_hwmod by name, or NULL if not found.
1350	*/
1351	static struct omap_hwmod *_lookup(const char *name)
1352	{
1353	struct omap_hwmod *oh, *temp_oh;
1354
1355	oh = NULL;
1356
1357	list_for_each_entry(temp_oh, &omap_hwmod_list, node) {
1358	if (!strcmp(name, temp_oh->name)) {
1359	oh = temp_oh;
1360	break;
1361	}
1362	}
1363
1364	return oh;
1365	}
1366
1367	/**
1368	* _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod
1369	* @oh: struct omap_hwmod *
1370	*
1371	* Convert a clockdomain name stored in a struct omap_hwmod into a
1372	* clockdomain pointer, and save it into the struct omap_hwmod.
1373	* Return -EINVAL if the clkdm_name lookup failed.
1374	*/
1375	static int _init_clkdm(struct omap_hwmod *oh)
1376	{
1377	if (!oh->clkdm_name) {
1378	pr_debug("omap_hwmod: %s: missing clockdomain\n", oh->name);
1379	return 0;
1380	}
1381
1382	oh->clkdm = clkdm_lookup(name: oh->clkdm_name);
1383	if (!oh->clkdm) {
1384	pr_warn("omap_hwmod: %s: could not associate to clkdm %s\n",
1385	oh->name, oh->clkdm_name);
1386	return 0;
1387	}
1388
1389	pr_debug("omap_hwmod: %s: associated to clkdm %s\n",
1390	oh->name, oh->clkdm_name);
1391
1392	return 0;
1393	}
1394
1395	/**
1396	* _init_clocks - clk_get() all clocks associated with this hwmod. Retrieve as
1397	* well the clockdomain.
1398	* @oh: struct omap_hwmod *
1399	* @np: device_node mapped to this hwmod
1400	*
1401	* Called by omap_hwmod_setup_*() (after omap2_clk_init()).
1402	* Resolves all clock names embedded in the hwmod. Returns 0 on
1403	* success, or a negative error code on failure.
1404	*/
1405	static int _init_clocks(struct omap_hwmod *oh, struct device_node *np)
1406	{
1407	int ret = 0;
1408
1409	if (oh->_state != _HWMOD_STATE_REGISTERED)
1410	return 0;
1411
1412	pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name);
1413
1414	if (soc_ops.init_clkdm)
1415	ret |= soc_ops.init_clkdm(oh);
1416
1417	ret |= _init_main_clk(oh);
1418	ret |= _init_interface_clks(oh);
1419	ret |= _init_opt_clks(oh);
1420
1421	if (!ret)
1422	oh->_state = _HWMOD_STATE_CLKS_INITED;
1423	else
1424	pr_warn("omap_hwmod: %s: cannot _init_clocks\n", oh->name);
1425
1426	return ret;
1427	}
1428
1429	/**
1430	* _lookup_hardreset - fill register bit info for this hwmod/reset line
1431	* @oh: struct omap_hwmod *
1432	* @name: name of the reset line in the context of this hwmod
1433	* @ohri: struct omap_hwmod_rst_info * that this function will fill in
1434	*
1435	* Return the bit position of the reset line that match the
1436	* input name. Return -ENOENT if not found.
1437	*/
1438	static int _lookup_hardreset(struct omap_hwmod *oh, const char *name,
1439	struct omap_hwmod_rst_info *ohri)
1440	{
1441	int i;
1442
1443	for (i = 0; i < oh->rst_lines_cnt; i++) {
1444	const char *rst_line = oh->rst_lines[i].name;
1445	if (!strcmp(rst_line, name)) {
1446	ohri->rst_shift = oh->rst_lines[i].rst_shift;
1447	ohri->st_shift = oh->rst_lines[i].st_shift;
1448	pr_debug("omap_hwmod: %s: %s: %s: rst %d st %d\n",
1449	oh->name, __func__, rst_line, ohri->rst_shift,
1450	ohri->st_shift);
1451
1452	return 0;
1453	}
1454	}
1455
1456	return -ENOENT;
1457	}
1458
1459	/**
1460	* _assert_hardreset - assert the HW reset line of submodules
1461	* contained in the hwmod module.
1462	* @oh: struct omap_hwmod *
1463	* @name: name of the reset line to lookup and assert
1464	*
1465	* Some IP like dsp, ipu or iva contain processor that require an HW
1466	* reset line to be assert / deassert in order to enable fully the IP.
1467	* Returns -EINVAL if @oh is null, -ENOSYS if we have no way of
1468	* asserting the hardreset line on the currently-booted SoC, or passes
1469	* along the return value from _lookup_hardreset() or the SoC's
1470	* assert_hardreset code.
1471	*/
1472	static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
1473	{
1474	struct omap_hwmod_rst_info ohri;
1475	int ret = -EINVAL;
1476
1477	if (!oh)
1478	return -EINVAL;
1479
1480	if (!soc_ops.assert_hardreset)
1481	return -ENOSYS;
1482
1483	ret = _lookup_hardreset(oh, name, ohri: &ohri);
1484	if (ret < 0)
1485	return ret;
1486
1487	ret = soc_ops.assert_hardreset(oh, &ohri);
1488
1489	return ret;
1490	}
1491
1492	/**
1493	* _deassert_hardreset - deassert the HW reset line of submodules contained
1494	* in the hwmod module.
1495	* @oh: struct omap_hwmod *
1496	* @name: name of the reset line to look up and deassert
1497	*
1498	* Some IP like dsp, ipu or iva contain processor that require an HW
1499	* reset line to be assert / deassert in order to enable fully the IP.
1500	* Returns -EINVAL if @oh is null, -ENOSYS if we have no way of
1501	* deasserting the hardreset line on the currently-booted SoC, or passes
1502	* along the return value from _lookup_hardreset() or the SoC's
1503	* deassert_hardreset code.
1504	*/
1505	static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
1506	{
1507	struct omap_hwmod_rst_info ohri;
1508	int ret = -EINVAL;
1509
1510	if (!oh)
1511	return -EINVAL;
1512
1513	if (!soc_ops.deassert_hardreset)
1514	return -ENOSYS;
1515
1516	ret = _lookup_hardreset(oh, name, ohri: &ohri);
1517	if (ret < 0)
1518	return ret;
1519
1520	if (oh->clkdm) {
1521	/*
1522	* A clockdomain must be in SW_SUP otherwise reset
1523	* might not be completed. The clockdomain can be set
1524	* in HW_AUTO only when the module become ready.
1525	*/
1526	clkdm_deny_idle(clkdm: oh->clkdm);
1527	ret = clkdm_hwmod_enable(clkdm: oh->clkdm, oh);
1528	if (ret) {
1529	WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n",
1530	oh->name, oh->clkdm->name, ret);
1531	return ret;
1532	}
1533	}
1534
1535	_enable_clocks(oh);
1536	if (soc_ops.enable_module)
1537	soc_ops.enable_module(oh);
1538
1539	ret = soc_ops.deassert_hardreset(oh, &ohri);
1540
1541	if (soc_ops.disable_module)
1542	soc_ops.disable_module(oh);
1543	_disable_clocks(oh);
1544
1545	if (ret == -EBUSY)
1546	pr_warn("omap_hwmod: %s: failed to hardreset\n", oh->name);
1547
1548	if (oh->clkdm) {
1549	/*
1550	* Set the clockdomain to HW_AUTO, assuming that the
1551	* previous state was HW_AUTO.
1552	*/
1553	clkdm_allow_idle(clkdm: oh->clkdm);
1554
1555	clkdm_hwmod_disable(clkdm: oh->clkdm, oh);
1556	}
1557
1558	return ret;
1559	}
1560
1561	/**
1562	* _read_hardreset - read the HW reset line state of submodules
1563	* contained in the hwmod module
1564	* @oh: struct omap_hwmod *
1565	* @name: name of the reset line to look up and read
1566	*
1567	* Return the state of the reset line. Returns -EINVAL if @oh is
1568	* null, -ENOSYS if we have no way of reading the hardreset line
1569	* status on the currently-booted SoC, or passes along the return
1570	* value from _lookup_hardreset() or the SoC's is_hardreset_asserted
1571	* code.
1572	*/
1573	static int _read_hardreset(struct omap_hwmod *oh, const char *name)
1574	{
1575	struct omap_hwmod_rst_info ohri;
1576	int ret = -EINVAL;
1577
1578	if (!oh)
1579	return -EINVAL;
1580
1581	if (!soc_ops.is_hardreset_asserted)
1582	return -ENOSYS;
1583
1584	ret = _lookup_hardreset(oh, name, ohri: &ohri);
1585	if (ret < 0)
1586	return ret;
1587
1588	return soc_ops.is_hardreset_asserted(oh, &ohri);
1589	}
1590
1591	/**
1592	* _are_all_hardreset_lines_asserted - return true if the @oh is hard-reset
1593	* @oh: struct omap_hwmod *
1594	*
1595	* If all hardreset lines associated with @oh are asserted, then return true.
1596	* Otherwise, if part of @oh is out hardreset or if no hardreset lines
1597	* associated with @oh are asserted, then return false.
1598	* This function is used to avoid executing some parts of the IP block
1599	* enable/disable sequence if its hardreset line is set.
1600	*/
1601	static bool _are_all_hardreset_lines_asserted(struct omap_hwmod *oh)
1602	{
1603	int i, rst_cnt = 0;
1604
1605	if (oh->rst_lines_cnt == 0)
1606	return false;
1607
1608	for (i = 0; i < oh->rst_lines_cnt; i++)
1609	if (_read_hardreset(oh, name: oh->rst_lines[i].name) > 0)
1610	rst_cnt++;
1611
1612	if (oh->rst_lines_cnt == rst_cnt)
1613	return true;
1614
1615	return false;
1616	}
1617
1618	/**
1619	* _are_any_hardreset_lines_asserted - return true if any part of @oh is
1620	* hard-reset
1621	* @oh: struct omap_hwmod *
1622	*
1623	* If any hardreset lines associated with @oh are asserted, then
1624	* return true. Otherwise, if no hardreset lines associated with @oh
1625	* are asserted, or if @oh has no hardreset lines, then return false.
1626	* This function is used to avoid executing some parts of the IP block
1627	* enable/disable sequence if any hardreset line is set.
1628	*/
1629	static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh)
1630	{
1631	int rst_cnt = 0;
1632	int i;
1633
1634	for (i = 0; i < oh->rst_lines_cnt && rst_cnt == 0; i++)
1635	if (_read_hardreset(oh, name: oh->rst_lines[i].name) > 0)
1636	rst_cnt++;
1637
1638	return (rst_cnt) ? true : false;
1639	}
1640
1641	/**
1642	* _omap4_disable_module - enable CLKCTRL modulemode on OMAP4
1643	* @oh: struct omap_hwmod *
1644	*
1645	* Disable the PRCM module mode related to the hwmod @oh.
1646	* Return EINVAL if the modulemode is not supported and 0 in case of success.
1647	*/
1648	static int _omap4_disable_module(struct omap_hwmod *oh)
1649	{
1650	int v;
1651
1652	if (!oh->clkdm || !oh->prcm.omap4.modulemode ||
1653	_omap4_clkctrl_managed_by_clkfwk(oh))
1654	return -EINVAL;
1655
1656	/*
1657	* Since integration code might still be doing something, only
1658	* disable if all lines are under hardreset.
1659	*/
1660	if (_are_any_hardreset_lines_asserted(oh))
1661	return 0;
1662
1663	pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
1664
1665	omap_cm_module_disable(part: oh->clkdm->prcm_partition, inst: oh->clkdm->cm_inst,
1666	clkctrl_offs: oh->prcm.omap4.clkctrl_offs);
1667
1668	v = _omap4_wait_target_disable(oh);
1669	if (v)
1670	pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
1671	oh->name);
1672
1673	return 0;
1674	}
1675
1676	/**
1677	* _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit
1678	* @oh: struct omap_hwmod *
1679	*
1680	* Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be
1681	* enabled for this to work. Returns -ENOENT if the hwmod cannot be
1682	* reset this way, -EINVAL if the hwmod is in the wrong state,
1683	* -ETIMEDOUT if the module did not reset in time, or 0 upon success.
1684	*
1685	* In OMAP3 a specific SYSSTATUS register is used to get the reset status.
1686	* Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead
1687	* use the SYSCONFIG softreset bit to provide the status.
1688	*
1689	* Note that some IP like McBSP do have reset control but don't have
1690	* reset status.
1691	*/
1692	static int _ocp_softreset(struct omap_hwmod *oh)
1693	{
1694	u32 v;
1695	int c = 0;
1696	int ret = 0;
1697
1698	if (!oh->class->sysc ||
1699	!(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET))
1700	return -ENOENT;
1701
1702	/* clocks must be on for this operation */
1703	if (oh->_state != _HWMOD_STATE_ENABLED) {
1704	pr_warn("omap_hwmod: %s: reset can only be entered from enabled state\n",
1705	oh->name);
1706	return -EINVAL;
1707	}
1708
1709	/* For some modules, all optionnal clocks need to be enabled as well */
1710	if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
1711	_enable_optional_clocks(oh);
1712
1713	pr_debug("omap_hwmod: %s: resetting via OCP SOFTRESET\n", oh->name);
1714
1715	v = oh->_sysc_cache;
1716	ret = _set_softreset(oh, v: &v);
1717	if (ret)
1718	goto dis_opt_clks;
1719
1720	_write_sysconfig(v, oh);
1721
1722	if (oh->class->sysc->srst_udelay)
1723	udelay(oh->class->sysc->srst_udelay);
1724
1725	c = _wait_softreset_complete(oh);
1726	if (c == MAX_MODULE_SOFTRESET_WAIT) {
1727	pr_warn("omap_hwmod: %s: softreset failed (waited %d usec)\n",
1728	oh->name, MAX_MODULE_SOFTRESET_WAIT);
1729	ret = -ETIMEDOUT;
1730	goto dis_opt_clks;
1731	} else {
1732	pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c);
1733	}
1734
1735	ret = _clear_softreset(oh, v: &v);
1736	if (ret)
1737	goto dis_opt_clks;
1738
1739	_write_sysconfig(v, oh);
1740
1741	/*
1742	* XXX add _HWMOD_STATE_WEDGED for modules that don't come back from
1743	* _wait_target_ready() or _reset()
1744	*/
1745
1746	dis_opt_clks:
1747	if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
1748	_disable_optional_clocks(oh);
1749
1750	return ret;
1751	}
1752
1753	/**
1754	* _reset - reset an omap_hwmod
1755	* @oh: struct omap_hwmod *
1756	*
1757	* Resets an omap_hwmod @oh. If the module has a custom reset
1758	* function pointer defined, then call it to reset the IP block, and
1759	* pass along its return value to the caller. Otherwise, if the IP
1760	* block has an OCP_SYSCONFIG register with a SOFTRESET bitfield
1761	* associated with it, call a function to reset the IP block via that
1762	* method, and pass along the return value to the caller. Finally, if
1763	* the IP block has some hardreset lines associated with it, assert
1764	* all of those, but do _not_ deassert them. (This is because driver
1765	* authors have expressed an apparent requirement to control the
1766	* deassertion of the hardreset lines themselves.)
1767	*
1768	* The default software reset mechanism for most OMAP IP blocks is
1769	* triggered via the OCP_SYSCONFIG.SOFTRESET bit. However, some
1770	* hwmods cannot be reset via this method. Some are not targets and
1771	* therefore have no OCP header registers to access. Others (like the
1772	* IVA) have idiosyncratic reset sequences. So for these relatively
1773	* rare cases, custom reset code can be supplied in the struct
1774	* omap_hwmod_class .reset function pointer.
1775	*
1776	* _set_dmadisable() is called to set the DMADISABLE bit so that it
1777	* does not prevent idling of the system. This is necessary for cases
1778	* where ROMCODE/BOOTLOADER uses dma and transfers control to the
1779	* kernel without disabling dma.
1780	*
1781	* Passes along the return value from either _ocp_softreset() or the
1782	* custom reset function - these must return -EINVAL if the hwmod
1783	* cannot be reset this way or if the hwmod is in the wrong state,
1784	* -ETIMEDOUT if the module did not reset in time, or 0 upon success.
1785	*/
1786	static int _reset(struct omap_hwmod *oh)
1787	{
1788	int i, r;
1789
1790	pr_debug("omap_hwmod: %s: resetting\n", oh->name);
1791
1792	if (oh->class->reset) {
1793	r = oh->class->reset(oh);
1794	} else {
1795	if (oh->rst_lines_cnt > 0) {
1796	for (i = 0; i < oh->rst_lines_cnt; i++)
1797	_assert_hardreset(oh, name: oh->rst_lines[i].name);
1798	return 0;
1799	} else {
1800	r = _ocp_softreset(oh);
1801	if (r == -ENOENT)
1802	r = 0;
1803	}
1804	}
1805
1806	_set_dmadisable(oh);
1807
1808	/*
1809	* OCP_SYSCONFIG bits need to be reprogrammed after a
1810	* softreset. The _enable() function should be split to avoid
1811	* the rewrite of the OCP_SYSCONFIG register.
1812	*/
1813	if (oh->class->sysc) {
1814	_update_sysc_cache(oh);
1815	_enable_sysc(oh);
1816	}
1817
1818	return r;
1819	}
1820
1821	/**
1822	* _omap4_update_context_lost - increment hwmod context loss counter if
1823	* hwmod context was lost, and clear hardware context loss reg
1824	* @oh: hwmod to check for context loss
1825	*
1826	* If the PRCM indicates that the hwmod @oh lost context, increment
1827	* our in-memory context loss counter, and clear the RM_*_CONTEXT
1828	* bits. No return value.
1829	*/
1830	static void _omap4_update_context_lost(struct omap_hwmod *oh)
1831	{
1832	if (oh->prcm.omap4.flags & HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT)
1833	return;
1834
1835	if (!prm_was_any_context_lost_old(part: oh->clkdm->pwrdm.ptr->prcm_partition,
1836	inst: oh->clkdm->pwrdm.ptr->prcm_offs,
1837	idx: oh->prcm.omap4.context_offs))
1838	return;
1839
1840	oh->prcm.omap4.context_lost_counter++;
1841	prm_clear_context_loss_flags_old(part: oh->clkdm->pwrdm.ptr->prcm_partition,
1842	inst: oh->clkdm->pwrdm.ptr->prcm_offs,
1843	idx: oh->prcm.omap4.context_offs);
1844	}
1845
1846	/**
1847	* _omap4_get_context_lost - get context loss counter for a hwmod
1848	* @oh: hwmod to get context loss counter for
1849	*
1850	* Returns the in-memory context loss counter for a hwmod.
1851	*/
1852	static int _omap4_get_context_lost(struct omap_hwmod *oh)
1853	{
1854	return oh->prcm.omap4.context_lost_counter;
1855	}
1856
1857	/**
1858	* _enable - enable an omap_hwmod
1859	* @oh: struct omap_hwmod *
1860	*
1861	* Enables an omap_hwmod @oh such that the MPU can access the hwmod's
1862	* register target. Returns -EINVAL if the hwmod is in the wrong
1863	* state or passes along the return value of _wait_target_ready().
1864	*/
1865	static int _enable(struct omap_hwmod *oh)
1866	{
1867	int r;
1868
1869	pr_debug("omap_hwmod: %s: enabling\n", oh->name);
1870
1871	/*
1872	* hwmods with HWMOD_INIT_NO_IDLE flag set are left in enabled
1873	* state at init.
1874	*/
1875	if (oh->_int_flags & _HWMOD_SKIP_ENABLE) {
1876	oh->_int_flags &= ~_HWMOD_SKIP_ENABLE;
1877	return 0;
1878	}
1879
1880	if (oh->_state != _HWMOD_STATE_INITIALIZED &&
1881	oh->_state != _HWMOD_STATE_IDLE &&
1882	oh->_state != _HWMOD_STATE_DISABLED) {
1883	WARN(1, "omap_hwmod: %s: enabled state can only be entered from initialized, idle, or disabled state\n",
1884	oh->name);
1885	return -EINVAL;
1886	}
1887
1888	/*
1889	* If an IP block contains HW reset lines and all of them are
1890	* asserted, we let integration code associated with that
1891	* block handle the enable. We've received very little
1892	* information on what those driver authors need, and until
1893	* detailed information is provided and the driver code is
1894	* posted to the public lists, this is probably the best we
1895	* can do.
1896	*/
1897	if (_are_all_hardreset_lines_asserted(oh))
1898	return 0;
1899
1900	_add_initiator_dep(oh, init_oh: mpu_oh);
1901
1902	if (oh->clkdm) {
1903	/*
1904	* A clockdomain must be in SW_SUP before enabling
1905	* completely the module. The clockdomain can be set
1906	* in HW_AUTO only when the module become ready.
1907	*/
1908	clkdm_deny_idle(clkdm: oh->clkdm);
1909	r = clkdm_hwmod_enable(clkdm: oh->clkdm, oh);
1910	if (r) {
1911	WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n",
1912	oh->name, oh->clkdm->name, r);
1913	return r;
1914	}
1915	}
1916
1917	_enable_clocks(oh);
1918	if (soc_ops.enable_module)
1919	soc_ops.enable_module(oh);
1920	if (oh->flags & HWMOD_BLOCK_WFI)
1921	cpu_idle_poll_ctrl(enable: true);
1922
1923	if (soc_ops.update_context_lost)
1924	soc_ops.update_context_lost(oh);
1925
1926	r = (soc_ops.wait_target_ready) ? soc_ops.wait_target_ready(oh) :
1927	-EINVAL;
1928	if (oh->clkdm && !(oh->flags & HWMOD_CLKDM_NOAUTO))
1929	clkdm_allow_idle(clkdm: oh->clkdm);
1930
1931	if (!r) {
1932	oh->_state = _HWMOD_STATE_ENABLED;
1933
1934	/* Access the sysconfig only if the target is ready */
1935	if (oh->class->sysc) {
1936	if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED))
1937	_update_sysc_cache(oh);
1938	_enable_sysc(oh);
1939	}
1940	} else {
1941	if (soc_ops.disable_module)
1942	soc_ops.disable_module(oh);
1943	_disable_clocks(oh);
1944	pr_err("omap_hwmod: %s: _wait_target_ready failed: %d\n",
1945	oh->name, r);
1946
1947	if (oh->clkdm)
1948	clkdm_hwmod_disable(clkdm: oh->clkdm, oh);
1949	}
1950
1951	return r;
1952	}
1953
1954	/**
1955	* _idle - idle an omap_hwmod
1956	* @oh: struct omap_hwmod *
1957	*
1958	* Idles an omap_hwmod @oh. This should be called once the hwmod has
1959	* no further work. Returns -EINVAL if the hwmod is in the wrong
1960	* state or returns 0.
1961	*/
1962	static int _idle(struct omap_hwmod *oh)
1963	{
1964	if (oh->flags & HWMOD_NO_IDLE) {
1965	oh->_int_flags |= _HWMOD_SKIP_ENABLE;
1966	return 0;
1967	}
1968
1969	pr_debug("omap_hwmod: %s: idling\n", oh->name);
1970
1971	if (_are_all_hardreset_lines_asserted(oh))
1972	return 0;
1973
1974	if (oh->_state != _HWMOD_STATE_ENABLED) {
1975	WARN(1, "omap_hwmod: %s: idle state can only be entered from enabled state\n",
1976	oh->name);
1977	return -EINVAL;
1978	}
1979
1980	if (oh->class->sysc)
1981	_idle_sysc(oh);
1982	_del_initiator_dep(oh, init_oh: mpu_oh);
1983
1984	/*
1985	* If HWMOD_CLKDM_NOAUTO is set then we don't
1986	* deny idle the clkdm again since idle was already denied
1987	* in _enable()
1988	*/
1989	if (oh->clkdm && !(oh->flags & HWMOD_CLKDM_NOAUTO))
1990	clkdm_deny_idle(clkdm: oh->clkdm);
1991
1992	if (oh->flags & HWMOD_BLOCK_WFI)
1993	cpu_idle_poll_ctrl(enable: false);
1994	if (soc_ops.disable_module)
1995	soc_ops.disable_module(oh);
1996
1997	/*
1998	* The module must be in idle mode before disabling any parents
1999	* clocks. Otherwise, the parent clock might be disabled before
2000	* the module transition is done, and thus will prevent the
2001	* transition to complete properly.
2002	*/
2003	_disable_clocks(oh);
2004	if (oh->clkdm) {
2005	clkdm_allow_idle(clkdm: oh->clkdm);
2006	clkdm_hwmod_disable(clkdm: oh->clkdm, oh);
2007	}
2008
2009	oh->_state = _HWMOD_STATE_IDLE;
2010
2011	return 0;
2012	}
2013
2014	/**
2015	* _shutdown - shutdown an omap_hwmod
2016	* @oh: struct omap_hwmod *
2017	*
2018	* Shut down an omap_hwmod @oh. This should be called when the driver
2019	* used for the hwmod is removed or unloaded or if the driver is not
2020	* used by the system. Returns -EINVAL if the hwmod is in the wrong
2021	* state or returns 0.
2022	*/
2023	static int _shutdown(struct omap_hwmod *oh)
2024	{
2025	int ret, i;
2026	u8 prev_state;
2027
2028	if (_are_all_hardreset_lines_asserted(oh))
2029	return 0;
2030
2031	if (oh->_state != _HWMOD_STATE_IDLE &&
2032	oh->_state != _HWMOD_STATE_ENABLED) {
2033	WARN(1, "omap_hwmod: %s: disabled state can only be entered from idle, or enabled state\n",
2034	oh->name);
2035	return -EINVAL;
2036	}
2037
2038	pr_debug("omap_hwmod: %s: disabling\n", oh->name);
2039
2040	if (oh->class->pre_shutdown) {
2041	prev_state = oh->_state;
2042	if (oh->_state == _HWMOD_STATE_IDLE)
2043	_enable(oh);
2044	ret = oh->class->pre_shutdown(oh);
2045	if (ret) {
2046	if (prev_state == _HWMOD_STATE_IDLE)
2047	_idle(oh);
2048	return ret;
2049	}
2050	}
2051
2052	if (oh->class->sysc) {
2053	if (oh->_state == _HWMOD_STATE_IDLE)
2054	_enable(oh);
2055	_shutdown_sysc(oh);
2056	}
2057
2058	/* clocks and deps are already disabled in idle */
2059	if (oh->_state == _HWMOD_STATE_ENABLED) {
2060	_del_initiator_dep(oh, init_oh: mpu_oh);
2061	/* XXX what about the other system initiators here? dma, dsp */
2062	if (oh->flags & HWMOD_BLOCK_WFI)
2063	cpu_idle_poll_ctrl(enable: false);
2064	if (soc_ops.disable_module)
2065	soc_ops.disable_module(oh);
2066	_disable_clocks(oh);
2067	if (oh->clkdm)
2068	clkdm_hwmod_disable(clkdm: oh->clkdm, oh);
2069	}
2070	/* XXX Should this code also force-disable the optional clocks? */
2071
2072	for (i = 0; i < oh->rst_lines_cnt; i++)
2073	_assert_hardreset(oh, name: oh->rst_lines[i].name);
2074
2075	oh->_state = _HWMOD_STATE_DISABLED;
2076
2077	return 0;
2078	}
2079
2080	static int of_dev_find_hwmod(struct device_node *np,
2081	struct omap_hwmod *oh)
2082	{
2083	int count, i, res;
2084	const char *p;
2085
2086	count = of_property_count_strings(np, propname: "ti,hwmods");
2087	if (count < 1)
2088	return -ENODEV;
2089
2090	for (i = 0; i < count; i++) {
2091	res = of_property_read_string_index(np, propname: "ti,hwmods",
2092	index: i, output: &p);
2093	if (res)
2094	continue;
2095	if (!strcmp(p, oh->name)) {
2096	pr_debug("omap_hwmod: dt %pOFn[%i] uses hwmod %s\n",
2097	np, i, oh->name);
2098	return i;
2099	}
2100	}
2101
2102	return -ENODEV;
2103	}
2104
2105	/**
2106	* of_dev_hwmod_lookup - look up needed hwmod from dt blob
2107	* @np: struct device_node *
2108	* @oh: struct omap_hwmod *
2109	* @index: index of the entry found
2110	* @found: struct device_node * found or NULL
2111	*
2112	* Parse the dt blob and find out needed hwmod. Recursive function is
2113	* implemented to take care hierarchical dt blob parsing.
2114	* Return: Returns 0 on success, -ENODEV when not found.
2115	*/
2116	static int of_dev_hwmod_lookup(struct device_node *np,
2117	struct omap_hwmod *oh,
2118	int *index,
2119	struct device_node **found)
2120	{
2121	struct device_node *np0 = NULL;
2122	int res;
2123
2124	res = of_dev_find_hwmod(np, oh);
2125	if (res >= 0) {
2126	*found = np;
2127	*index = res;
2128	return 0;
2129	}
2130
2131	for_each_child_of_node(np, np0) {
2132	struct device_node *fc;
2133	int i;
2134
2135	res = of_dev_hwmod_lookup(np: np0, oh, index: &i, found: &fc);
2136	if (res == 0) {
2137	*found = fc;
2138	*index = i;
2139	of_node_put(node: np0);
2140	return 0;
2141	}
2142	}
2143
2144	*found = NULL;
2145	*index = 0;
2146
2147	return -ENODEV;
2148	}
2149
2150	/**
2151	* omap_hwmod_fix_mpu_rt_idx - fix up mpu_rt_idx register offsets
2152	*
2153	* @oh: struct omap_hwmod *
2154	* @np: struct device_node *
2155	*
2156	* Fix up module register offsets for modules with mpu_rt_idx.
2157	* Only needed for cpsw with interconnect target module defined
2158	* in device tree while still using legacy hwmod platform data
2159	* for rev, sysc and syss registers.
2160	*
2161	* Can be removed when all cpsw hwmod platform data has been
2162	* dropped.
2163	*/
2164	static void omap_hwmod_fix_mpu_rt_idx(struct omap_hwmod *oh,
2165	struct device_node *np,
2166	struct resource *res)
2167	{
2168	struct device_node *child = NULL;
2169	int error;
2170
2171	child = of_get_next_child(node: np, prev: child);
2172	if (!child)
2173	return;
2174
2175	error = of_address_to_resource(dev: child, index: oh->mpu_rt_idx, r: res);
2176	if (error)
2177	pr_err("%s: error mapping mpu_rt_idx: %i\n",
2178	__func__, error);
2179	}
2180
2181	/**
2182	* omap_hwmod_parse_module_range - map module IO range from device tree
2183	* @oh: struct omap_hwmod *
2184	* @np: struct device_node *
2185	*
2186	* Parse the device tree range an interconnect target module provides
2187	* for it's child device IP blocks. This way we can support the old
2188	* "ti,hwmods" property with just dts data without a need for platform
2189	* data for IO resources. And we don't need all the child IP device
2190	* nodes available in the dts.
2191	*/
2192	int omap_hwmod_parse_module_range(struct omap_hwmod *oh,
2193	struct device_node *np,
2194	struct resource *res)
2195	{
2196	struct property *prop;
2197	const char *name;
2198	int err;
2199
2200	of_property_for_each_string(np, "compatible", prop, name)
2201	if (!strncmp("ti,sysc-", name, 8))
2202	break;
2203
2204	if (!name)
2205	return -ENOENT;
2206
2207	err = of_range_to_resource(np, index: 0, res);
2208	if (err)
2209	return err;
2210
2211	pr_debug("omap_hwmod: %s %pOFn at %pR\n",
2212	oh->name, np, res);
2213
2214	if (oh && oh->mpu_rt_idx) {
2215	omap_hwmod_fix_mpu_rt_idx(oh, np, res);
2216
2217	return 0;
2218	}
2219
2220	return 0;
2221	}
2222
2223	/**
2224	* _init_mpu_rt_base - populate the virtual address for a hwmod
2225	* @oh: struct omap_hwmod * to locate the virtual address
2226	* @data: (unused, caller should pass NULL)
2227	* @index: index of the reg entry iospace in device tree
2228	* @np: struct device_node * of the IP block's device node in the DT data
2229	*
2230	* Cache the virtual address used by the MPU to access this IP block's
2231	* registers. This address is needed early so the OCP registers that
2232	* are part of the device's address space can be ioremapped properly.
2233	*
2234	* If SYSC access is not needed, the registers will not be remapped
2235	* and non-availability of MPU access is not treated as an error.
2236	*
2237	* Returns 0 on success, -EINVAL if an invalid hwmod is passed, and
2238	* -ENXIO on absent or invalid register target address space.
2239	*/
2240	static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data,
2241	int index, struct device_node *np)
2242	{
2243	void __iomem *va_start = NULL;
2244	struct resource res;
2245	int error;
2246
2247	if (!oh)
2248	return -EINVAL;
2249
2250	_save_mpu_port_index(oh);
2251
2252	/* if we don't need sysc access we don't need to ioremap */
2253	if (!oh->class->sysc)
2254	return 0;
2255
2256	/* we can't continue without MPU PORT if we need sysc access */
2257	if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
2258	return -ENXIO;
2259
2260	if (!np) {
2261	pr_err("omap_hwmod: %s: no dt node\n", oh->name);
2262	return -ENXIO;
2263	}
2264
2265	/* Do we have a dts range for the interconnect target module? */
2266	error = omap_hwmod_parse_module_range(oh, np, res: &res);
2267	if (!error)
2268	va_start = ioremap(offset: res.start, size: resource_size(res: &res));
2269
2270	/* No ranges, rely on device reg entry */
2271	if (!va_start)
2272	va_start = of_iomap(node: np, index: index + oh->mpu_rt_idx);
2273	if (!va_start) {
2274	pr_err("omap_hwmod: %s: Missing dt reg%i for %pOF\n",
2275	oh->name, index, np);
2276	return -ENXIO;
2277	}
2278
2279	pr_debug("omap_hwmod: %s: MPU register target at va %p\n",
2280	oh->name, va_start);
2281
2282	oh->_mpu_rt_va = va_start;
2283	return 0;
2284	}
2285
2286	static void __init parse_module_flags(struct omap_hwmod *oh,
2287	struct device_node *np)
2288	{
2289	if (of_property_read_bool(np, propname: "ti,no-reset-on-init"))
2290	oh->flags |= HWMOD_INIT_NO_RESET;
2291	if (of_property_read_bool(np, propname: "ti,no-idle-on-init"))
2292	oh->flags |= HWMOD_INIT_NO_IDLE;
2293	if (of_property_read_bool(np, propname: "ti,no-idle"))
2294	oh->flags |= HWMOD_NO_IDLE;
2295	}
2296
2297	/**
2298	* _init - initialize internal data for the hwmod @oh
2299	* @oh: struct omap_hwmod *
2300	* @n: (unused)
2301	*
2302	* Look up the clocks and the address space used by the MPU to access
2303	* registers belonging to the hwmod @oh. @oh must already be
2304	* registered at this point. This is the first of two phases for
2305	* hwmod initialization. Code called here does not touch any hardware
2306	* registers, it simply prepares internal data structures. Returns 0
2307	* upon success or if the hwmod isn't registered or if the hwmod's
2308	* address space is not defined, or -EINVAL upon failure.
2309	*/
2310	static int __init _init(struct omap_hwmod *oh, void *data)
2311	{
2312	int r, index;
2313	struct device_node *np = NULL;
2314	struct device_node *bus;
2315
2316	if (oh->_state != _HWMOD_STATE_REGISTERED)
2317	return 0;
2318
2319	bus = of_find_node_by_name(NULL, name: "ocp");
2320	if (!bus)
2321	return -ENODEV;
2322
2323	r = of_dev_hwmod_lookup(np: bus, oh, index: &index, found: &np);
2324	if (r)
2325	pr_debug("omap_hwmod: %s missing dt data\n", oh->name);
2326	else if (np && index)
2327	pr_warn("omap_hwmod: %s using broken dt data from %pOFn\n",
2328	oh->name, np);
2329
2330	r = _init_mpu_rt_base(oh, NULL, index, np);
2331	if (r < 0) {
2332	WARN(1, "omap_hwmod: %s: doesn't have mpu register target base\n",
2333	oh->name);
2334	return 0;
2335	}
2336
2337	r = _init_clocks(oh, np);
2338	if (r < 0) {
2339	WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name);
2340	return -EINVAL;
2341	}
2342
2343	if (np) {
2344	struct device_node *child;
2345
2346	parse_module_flags(oh, np);
2347	child = of_get_next_child(node: np, NULL);
2348	if (child)
2349	parse_module_flags(oh, np: child);
2350	}
2351
2352	oh->_state = _HWMOD_STATE_INITIALIZED;
2353
2354	return 0;
2355	}
2356
2357	/**
2358	* _setup_iclk_autoidle - configure an IP block's interface clocks
2359	* @oh: struct omap_hwmod *
2360	*
2361	* Set up the module's interface clocks. XXX This function is still mostly
2362	* a stub; implementing this properly requires iclk autoidle usecounting in
2363	* the clock code. No return value.
2364	*/
2365	static void _setup_iclk_autoidle(struct omap_hwmod *oh)
2366	{
2367	struct omap_hwmod_ocp_if *os;
2368
2369	if (oh->_state != _HWMOD_STATE_INITIALIZED)
2370	return;
2371
2372	list_for_each_entry(os, &oh->slave_ports, node) {
2373	if (!os->_clk)
2374	continue;
2375
2376	if (os->flags & OCPIF_SWSUP_IDLE) {
2377	/*
2378	* we might have multiple users of one iclk with
2379	* different requirements, disable autoidle when
2380	* the module is enabled, e.g. dss iclk
2381	*/
2382	} else {
2383	/* we are enabling autoidle afterwards anyways */
2384	clk_enable(clk: os->_clk);
2385	}
2386	}
2387
2388	return;
2389	}
2390
2391	/**
2392	* _setup_reset - reset an IP block during the setup process
2393	* @oh: struct omap_hwmod *
2394	*
2395	* Reset the IP block corresponding to the hwmod @oh during the setup
2396	* process. The IP block is first enabled so it can be successfully
2397	* reset. Returns 0 upon success or a negative error code upon
2398	* failure.
2399	*/
2400	static int _setup_reset(struct omap_hwmod *oh)
2401	{
2402	int r = 0;
2403
2404	if (oh->_state != _HWMOD_STATE_INITIALIZED)
2405	return -EINVAL;
2406
2407	if (oh->flags & HWMOD_EXT_OPT_MAIN_CLK)
2408	return -EPERM;
2409
2410	if (oh->rst_lines_cnt == 0) {
2411	r = _enable(oh);
2412	if (r) {
2413	pr_warn("omap_hwmod: %s: cannot be enabled for reset (%d)\n",
2414	oh->name, oh->_state);
2415	return -EINVAL;
2416	}
2417	}
2418
2419	if (!(oh->flags & HWMOD_INIT_NO_RESET))
2420	r = _reset(oh);
2421
2422	return r;
2423	}
2424
2425	/**
2426	* _setup_postsetup - transition to the appropriate state after _setup
2427	* @oh: struct omap_hwmod *
2428	*
2429	* Place an IP block represented by @oh into a "post-setup" state --
2430	* either IDLE, ENABLED, or DISABLED. ("post-setup" simply means that
2431	* this function is called at the end of _setup().) The postsetup
2432	* state for an IP block can be changed by calling
2433	* omap_hwmod_enter_postsetup_state() early in the boot process,
2434	* before one of the omap_hwmod_setup*() functions are called for the
2435	* IP block.
2436	*
2437	* The IP block stays in this state until a PM runtime-based driver is
2438	* loaded for that IP block. A post-setup state of IDLE is
2439	* appropriate for almost all IP blocks with runtime PM-enabled
2440	* drivers, since those drivers are able to enable the IP block. A
2441	* post-setup state of ENABLED is appropriate for kernels with PM
2442	* runtime disabled. The DISABLED state is appropriate for unusual IP
2443	* blocks such as the MPU WDTIMER on kernels without WDTIMER drivers
2444	* included, since the WDTIMER starts running on reset and will reset
2445	* the MPU if left active.
2446	*
2447	* This post-setup mechanism is deprecated. Once all of the OMAP
2448	* drivers have been converted to use PM runtime, and all of the IP
2449	* block data and interconnect data is available to the hwmod code, it
2450	* should be possible to replace this mechanism with a "lazy reset"
2451	* arrangement. In a "lazy reset" setup, each IP block is enabled
2452	* when the driver first probes, then all remaining IP blocks without
2453	* drivers are either shut down or enabled after the drivers have
2454	* loaded. However, this cannot take place until the above
2455	* preconditions have been met, since otherwise the late reset code
2456	* has no way of knowing which IP blocks are in use by drivers, and
2457	* which ones are unused.
2458	*
2459	* No return value.
2460	*/
2461	static void _setup_postsetup(struct omap_hwmod *oh)
2462	{
2463	u8 postsetup_state;
2464
2465	if (oh->rst_lines_cnt > 0)
2466	return;
2467
2468	postsetup_state = oh->_postsetup_state;
2469	if (postsetup_state == _HWMOD_STATE_UNKNOWN)
2470	postsetup_state = _HWMOD_STATE_ENABLED;
2471
2472	/*
2473	* XXX HWMOD_INIT_NO_IDLE does not belong in hwmod data -
2474	* it should be set by the core code as a runtime flag during startup
2475	*/
2476	if ((oh->flags & (HWMOD_INIT_NO_IDLE | HWMOD_NO_IDLE)) &&
2477	(postsetup_state == _HWMOD_STATE_IDLE)) {
2478	oh->_int_flags |= _HWMOD_SKIP_ENABLE;
2479	postsetup_state = _HWMOD_STATE_ENABLED;
2480	}
2481
2482	if (postsetup_state == _HWMOD_STATE_IDLE)
2483	_idle(oh);
2484	else if (postsetup_state == _HWMOD_STATE_DISABLED)
2485	_shutdown(oh);
2486	else if (postsetup_state != _HWMOD_STATE_ENABLED)
2487	WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n",
2488	oh->name, postsetup_state);
2489
2490	return;
2491	}
2492
2493	/**
2494	* _setup - prepare IP block hardware for use
2495	* @oh: struct omap_hwmod *
2496	* @n: (unused, pass NULL)
2497	*
2498	* Configure the IP block represented by @oh. This may include
2499	* enabling the IP block, resetting it, and placing it into a
2500	* post-setup state, depending on the type of IP block and applicable
2501	* flags. IP blocks are reset to prevent any previous configuration
2502	* by the bootloader or previous operating system from interfering
2503	* with power management or other parts of the system. The reset can
2504	* be avoided; see omap_hwmod_no_setup_reset(). This is the second of
2505	* two phases for hwmod initialization. Code called here generally
2506	* affects the IP block hardware, or system integration hardware
2507	* associated with the IP block. Returns 0.
2508	*/
2509	static int _setup(struct omap_hwmod *oh, void *data)
2510	{
2511	if (oh->_state != _HWMOD_STATE_INITIALIZED)
2512	return 0;
2513
2514	if (oh->parent_hwmod) {
2515	int r;
2516
2517	r = _enable(oh: oh->parent_hwmod);
2518	WARN(r, "hwmod: %s: setup: failed to enable parent hwmod %s\n",
2519	oh->name, oh->parent_hwmod->name);
2520	}
2521
2522	_setup_iclk_autoidle(oh);
2523
2524	if (!_setup_reset(oh))
2525	_setup_postsetup(oh);
2526
2527	if (oh->parent_hwmod) {
2528	u8 postsetup_state;
2529
2530	postsetup_state = oh->parent_hwmod->_postsetup_state;
2531
2532	if (postsetup_state == _HWMOD_STATE_IDLE)
2533	_idle(oh: oh->parent_hwmod);
2534	else if (postsetup_state == _HWMOD_STATE_DISABLED)
2535	_shutdown(oh: oh->parent_hwmod);
2536	else if (postsetup_state != _HWMOD_STATE_ENABLED)
2537	WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n",
2538	oh->parent_hwmod->name, postsetup_state);
2539	}
2540
2541	return 0;
2542	}
2543
2544	/**
2545	* _register - register a struct omap_hwmod
2546	* @oh: struct omap_hwmod *
2547	*
2548	* Registers the omap_hwmod @oh. Returns -EEXIST if an omap_hwmod
2549	* already has been registered by the same name; -EINVAL if the
2550	* omap_hwmod is in the wrong state, if @oh is NULL, if the
2551	* omap_hwmod's class field is NULL; if the omap_hwmod is missing a
2552	* name, or if the omap_hwmod's class is missing a name; or 0 upon
2553	* success.
2554	*
2555	* XXX The data should be copied into bootmem, so the original data
2556	* should be marked __initdata and freed after init. This would allow
2557	* unneeded omap_hwmods to be freed on multi-OMAP configurations. Note
2558	* that the copy process would be relatively complex due to the large number
2559	* of substructures.
2560	*/
2561	static int _register(struct omap_hwmod *oh)
2562	{
2563	if (!oh || !oh->name || !oh->class || !oh->class->name ||
2564	(oh->_state != _HWMOD_STATE_UNKNOWN))
2565	return -EINVAL;
2566
2567	pr_debug("omap_hwmod: %s: registering\n", oh->name);
2568
2569	if (_lookup(name: oh->name))
2570	return -EEXIST;
2571
2572	list_add_tail(new: &oh->node, head: &omap_hwmod_list);
2573
2574	INIT_LIST_HEAD(list: &oh->slave_ports);
2575	spin_lock_init(&oh->_lock);
2576	lockdep_set_class(&oh->_lock, &oh->hwmod_key);
2577
2578	oh->_state = _HWMOD_STATE_REGISTERED;
2579
2580	/*
2581	* XXX Rather than doing a strcmp(), this should test a flag
2582	* set in the hwmod data, inserted by the autogenerator code.
2583	*/
2584	if (!strcmp(oh->name, MPU_INITIATOR_NAME))
2585	mpu_oh = oh;
2586
2587	return 0;
2588	}
2589
2590	/**
2591	* _add_link - add an interconnect between two IP blocks
2592	* @oi: pointer to a struct omap_hwmod_ocp_if record
2593	*
2594	* Add struct omap_hwmod_link records connecting the slave IP block
2595	* specified in @oi->slave to @oi. This code is assumed to run before
2596	* preemption or SMP has been enabled, thus avoiding the need for
2597	* locking in this code. Changes to this assumption will require
2598	* additional locking. Returns 0.
2599	*/
2600	static int _add_link(struct omap_hwmod_ocp_if *oi)
2601	{
2602	pr_debug("omap_hwmod: %s -> %s: adding link\n", oi->master->name,
2603	oi->slave->name);
2604
2605	list_add(new: &oi->node, head: &oi->slave->slave_ports);
2606	oi->slave->slaves_cnt++;
2607
2608	return 0;
2609	}
2610
2611	/**
2612	* _register_link - register a struct omap_hwmod_ocp_if
2613	* @oi: struct omap_hwmod_ocp_if *
2614	*
2615	* Registers the omap_hwmod_ocp_if record @oi. Returns -EEXIST if it
2616	* has already been registered; -EINVAL if @oi is NULL or if the
2617	* record pointed to by @oi is missing required fields; or 0 upon
2618	* success.
2619	*
2620	* XXX The data should be copied into bootmem, so the original data
2621	* should be marked __initdata and freed after init. This would allow
2622	* unneeded omap_hwmods to be freed on multi-OMAP configurations.
2623	*/
2624	static int __init _register_link(struct omap_hwmod_ocp_if *oi)
2625	{
2626	if (!oi || !oi->master || !oi->slave || !oi->user)
2627	return -EINVAL;
2628
2629	if (oi->_int_flags & _OCPIF_INT_FLAGS_REGISTERED)
2630	return -EEXIST;
2631
2632	pr_debug("omap_hwmod: registering link from %s to %s\n",
2633	oi->master->name, oi->slave->name);
2634
2635	/*
2636	* Register the connected hwmods, if they haven't been
2637	* registered already
2638	*/
2639	if (oi->master->_state != _HWMOD_STATE_REGISTERED)
2640	_register(oh: oi->master);
2641
2642	if (oi->slave->_state != _HWMOD_STATE_REGISTERED)
2643	_register(oh: oi->slave);
2644
2645	_add_link(oi);
2646
2647	oi->_int_flags |= _OCPIF_INT_FLAGS_REGISTERED;
2648
2649	return 0;
2650	}
2651
2652	/* Static functions intended only for use in soc_ops field function pointers */
2653
2654	/**
2655	* _omap2xxx_3xxx_wait_target_ready - wait for a module to leave slave idle
2656	* @oh: struct omap_hwmod *
2657	*
2658	* Wait for a module @oh to leave slave idle. Returns 0 if the module
2659	* does not have an IDLEST bit or if the module successfully leaves
2660	* slave idle; otherwise, pass along the return value of the
2661	* appropriate *_cm*_wait_module_ready() function.
2662	*/
2663	static int _omap2xxx_3xxx_wait_target_ready(struct omap_hwmod *oh)
2664	{
2665	if (!oh)
2666	return -EINVAL;
2667
2668	if (oh->flags & HWMOD_NO_IDLEST)
2669	return 0;
2670
2671	if (!_find_mpu_rt_port(oh))
2672	return 0;
2673
2674	/* XXX check module SIDLEMODE, hardreset status, enabled clocks */
2675
2676	return omap_cm_wait_module_ready(part: 0, prcm_mod: oh->prcm.omap2.module_offs,
2677	idlest_reg: oh->prcm.omap2.idlest_reg_id,
2678	idlest_shift: oh->prcm.omap2.idlest_idle_bit);
2679	}
2680
2681	/**
2682	* _omap4_wait_target_ready - wait for a module to leave slave idle
2683	* @oh: struct omap_hwmod *
2684	*
2685	* Wait for a module @oh to leave slave idle. Returns 0 if the module
2686	* does not have an IDLEST bit or if the module successfully leaves
2687	* slave idle; otherwise, pass along the return value of the
2688	* appropriate *_cm*_wait_module_ready() function.
2689	*/
2690	static int _omap4_wait_target_ready(struct omap_hwmod *oh)
2691	{
2692	if (!oh)
2693	return -EINVAL;
2694
2695	if (oh->flags & HWMOD_NO_IDLEST || !oh->clkdm)
2696	return 0;
2697
2698	if (!_find_mpu_rt_port(oh))
2699	return 0;
2700
2701	if (_omap4_clkctrl_managed_by_clkfwk(oh))
2702	return 0;
2703
2704	if (!_omap4_has_clkctrl_clock(oh))
2705	return 0;
2706
2707	/* XXX check module SIDLEMODE, hardreset status */
2708
2709	return omap_cm_wait_module_ready(part: oh->clkdm->prcm_partition,
2710	prcm_mod: oh->clkdm->cm_inst,
2711	idlest_reg: oh->prcm.omap4.clkctrl_offs, idlest_shift: 0);
2712	}
2713
2714	/**
2715	* _omap2_assert_hardreset - call OMAP2 PRM hardreset fn with hwmod args
2716	* @oh: struct omap_hwmod * to assert hardreset
2717	* @ohri: hardreset line data
2718	*
2719	* Call omap2_prm_assert_hardreset() with parameters extracted from
2720	* the hwmod @oh and the hardreset line data @ohri. Only intended for
2721	* use as an soc_ops function pointer. Passes along the return value
2722	* from omap2_prm_assert_hardreset(). XXX This function is scheduled
2723	* for removal when the PRM code is moved into drivers/.
2724	*/
2725	static int _omap2_assert_hardreset(struct omap_hwmod *oh,
2726	struct omap_hwmod_rst_info *ohri)
2727	{
2728	return omap_prm_assert_hardreset(shift: ohri->rst_shift, part: 0,
2729	prm_mod: oh->prcm.omap2.module_offs, offset: 0);
2730	}
2731
2732	/**
2733	* _omap2_deassert_hardreset - call OMAP2 PRM hardreset fn with hwmod args
2734	* @oh: struct omap_hwmod * to deassert hardreset
2735	* @ohri: hardreset line data
2736	*
2737	* Call omap2_prm_deassert_hardreset() with parameters extracted from
2738	* the hwmod @oh and the hardreset line data @ohri. Only intended for
2739	* use as an soc_ops function pointer. Passes along the return value
2740	* from omap2_prm_deassert_hardreset(). XXX This function is
2741	* scheduled for removal when the PRM code is moved into drivers/.
2742	*/
2743	static int _omap2_deassert_hardreset(struct omap_hwmod *oh,
2744	struct omap_hwmod_rst_info *ohri)
2745	{
2746	return omap_prm_deassert_hardreset(shift: ohri->rst_shift, st_shift: ohri->st_shift, part: 0,
2747	prm_mod: oh->prcm.omap2.module_offs, offset: 0, st_offset: 0);
2748	}
2749
2750	/**
2751	* _omap2_is_hardreset_asserted - call OMAP2 PRM hardreset fn with hwmod args
2752	* @oh: struct omap_hwmod * to test hardreset
2753	* @ohri: hardreset line data
2754	*
2755	* Call omap2_prm_is_hardreset_asserted() with parameters extracted
2756	* from the hwmod @oh and the hardreset line data @ohri. Only
2757	* intended for use as an soc_ops function pointer. Passes along the
2758	* return value from omap2_prm_is_hardreset_asserted(). XXX This
2759	* function is scheduled for removal when the PRM code is moved into
2760	* drivers/.
2761	*/
2762	static int _omap2_is_hardreset_asserted(struct omap_hwmod *oh,
2763	struct omap_hwmod_rst_info *ohri)
2764	{
2765	return omap_prm_is_hardreset_asserted(shift: ohri->st_shift, part: 0,
2766	prm_mod: oh->prcm.omap2.module_offs, offset: 0);
2767	}
2768
2769	/**
2770	* _omap4_assert_hardreset - call OMAP4 PRM hardreset fn with hwmod args
2771	* @oh: struct omap_hwmod * to assert hardreset
2772	* @ohri: hardreset line data
2773	*
2774	* Call omap4_prminst_assert_hardreset() with parameters extracted
2775	* from the hwmod @oh and the hardreset line data @ohri. Only
2776	* intended for use as an soc_ops function pointer. Passes along the
2777	* return value from omap4_prminst_assert_hardreset(). XXX This
2778	* function is scheduled for removal when the PRM code is moved into
2779	* drivers/.
2780	*/
2781	static int _omap4_assert_hardreset(struct omap_hwmod *oh,
2782	struct omap_hwmod_rst_info *ohri)
2783	{
2784	if (!oh->clkdm)
2785	return -EINVAL;
2786
2787	return omap_prm_assert_hardreset(shift: ohri->rst_shift,
2788	part: oh->clkdm->pwrdm.ptr->prcm_partition,
2789	prm_mod: oh->clkdm->pwrdm.ptr->prcm_offs,
2790	offset: oh->prcm.omap4.rstctrl_offs);
2791	}
2792
2793	/**
2794	* _omap4_deassert_hardreset - call OMAP4 PRM hardreset fn with hwmod args
2795	* @oh: struct omap_hwmod * to deassert hardreset
2796	* @ohri: hardreset line data
2797	*
2798	* Call omap4_prminst_deassert_hardreset() with parameters extracted
2799	* from the hwmod @oh and the hardreset line data @ohri. Only
2800	* intended for use as an soc_ops function pointer. Passes along the
2801	* return value from omap4_prminst_deassert_hardreset(). XXX This
2802	* function is scheduled for removal when the PRM code is moved into
2803	* drivers/.
2804	*/
2805	static int _omap4_deassert_hardreset(struct omap_hwmod *oh,
2806	struct omap_hwmod_rst_info *ohri)
2807	{
2808	if (!oh->clkdm)
2809	return -EINVAL;
2810
2811	if (ohri->st_shift)
2812	pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
2813	oh->name, ohri->name);
2814	return omap_prm_deassert_hardreset(shift: ohri->rst_shift, st_shift: ohri->rst_shift,
2815	part: oh->clkdm->pwrdm.ptr->prcm_partition,
2816	prm_mod: oh->clkdm->pwrdm.ptr->prcm_offs,
2817	offset: oh->prcm.omap4.rstctrl_offs,
2818	st_offset: oh->prcm.omap4.rstctrl_offs +
2819	OMAP4_RST_CTRL_ST_OFFSET);
2820	}
2821
2822	/**
2823	* _omap4_is_hardreset_asserted - call OMAP4 PRM hardreset fn with hwmod args
2824	* @oh: struct omap_hwmod * to test hardreset
2825	* @ohri: hardreset line data
2826	*
2827	* Call omap4_prminst_is_hardreset_asserted() with parameters
2828	* extracted from the hwmod @oh and the hardreset line data @ohri.
2829	* Only intended for use as an soc_ops function pointer. Passes along
2830	* the return value from omap4_prminst_is_hardreset_asserted(). XXX
2831	* This function is scheduled for removal when the PRM code is moved
2832	* into drivers/.
2833	*/
2834	static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh,
2835	struct omap_hwmod_rst_info *ohri)
2836	{
2837	if (!oh->clkdm)
2838	return -EINVAL;
2839
2840	return omap_prm_is_hardreset_asserted(shift: ohri->rst_shift,
2841	part: oh->clkdm->pwrdm.ptr->
2842	prcm_partition,
2843	prm_mod: oh->clkdm->pwrdm.ptr->prcm_offs,
2844	offset: oh->prcm.omap4.rstctrl_offs);
2845	}
2846
2847	/**
2848	* _omap4_disable_direct_prcm - disable direct PRCM control for hwmod
2849	* @oh: struct omap_hwmod * to disable control for
2850	*
2851	* Disables direct PRCM clkctrl done by hwmod core. Instead, the hwmod
2852	* will be using its main_clk to enable/disable the module. Returns
2853	* 0 if successful.
2854	*/
2855	static int _omap4_disable_direct_prcm(struct omap_hwmod *oh)
2856	{
2857	if (!oh)
2858	return -EINVAL;
2859
2860	oh->prcm.omap4.flags |= HWMOD_OMAP4_CLKFWK_CLKCTR_CLOCK;
2861
2862	return 0;
2863	}
2864
2865	/**
2866	* _am33xx_deassert_hardreset - call AM33XX PRM hardreset fn with hwmod args
2867	* @oh: struct omap_hwmod * to deassert hardreset
2868	* @ohri: hardreset line data
2869	*
2870	* Call am33xx_prminst_deassert_hardreset() with parameters extracted
2871	* from the hwmod @oh and the hardreset line data @ohri. Only
2872	* intended for use as an soc_ops function pointer. Passes along the
2873	* return value from am33xx_prminst_deassert_hardreset(). XXX This
2874	* function is scheduled for removal when the PRM code is moved into
2875	* drivers/.
2876	*/
2877	static int _am33xx_deassert_hardreset(struct omap_hwmod *oh,
2878	struct omap_hwmod_rst_info *ohri)
2879	{
2880	return omap_prm_deassert_hardreset(shift: ohri->rst_shift, st_shift: ohri->st_shift,
2881	part: oh->clkdm->pwrdm.ptr->prcm_partition,
2882	prm_mod: oh->clkdm->pwrdm.ptr->prcm_offs,
2883	offset: oh->prcm.omap4.rstctrl_offs,
2884	st_offset: oh->prcm.omap4.rstst_offs);
2885	}
2886
2887	/* Public functions */
2888
2889	u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs)
2890	{
2891	if (oh->flags & HWMOD_16BIT_REG)
2892	return readw_relaxed(oh->_mpu_rt_va + reg_offs);
2893	else
2894	return readl_relaxed(oh->_mpu_rt_va + reg_offs);
2895	}
2896
2897	void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
2898	{
2899	if (oh->flags & HWMOD_16BIT_REG)
2900	writew_relaxed(v, oh->_mpu_rt_va + reg_offs);
2901	else
2902	writel_relaxed(v, oh->_mpu_rt_va + reg_offs);
2903	}
2904
2905	/**
2906	* omap_hwmod_softreset - reset a module via SYSCONFIG.SOFTRESET bit
2907	* @oh: struct omap_hwmod *
2908	*
2909	* This is a public function exposed to drivers. Some drivers may need to do
2910	* some settings before and after resetting the device. Those drivers after
2911	* doing the necessary settings could use this function to start a reset by
2912	* setting the SYSCONFIG.SOFTRESET bit.
2913	*/
2914	int omap_hwmod_softreset(struct omap_hwmod *oh)
2915	{
2916	u32 v;
2917	int ret;
2918
2919	if (!oh || !(oh->_sysc_cache))
2920	return -EINVAL;
2921
2922	v = oh->_sysc_cache;
2923	ret = _set_softreset(oh, v: &v);
2924	if (ret)
2925	goto error;
2926	_write_sysconfig(v, oh);
2927
2928	ret = _clear_softreset(oh, v: &v);
2929	if (ret)
2930	goto error;
2931	_write_sysconfig(v, oh);
2932
2933	error:
2934	return ret;
2935	}
2936
2937	/**
2938	* omap_hwmod_lookup - look up a registered omap_hwmod by name
2939	* @name: name of the omap_hwmod to look up
2940	*
2941	* Given a @name of an omap_hwmod, return a pointer to the registered
2942	* struct omap_hwmod *, or NULL upon error.
2943	*/
2944	struct omap_hwmod *omap_hwmod_lookup(const char *name)
2945	{
2946	struct omap_hwmod *oh;
2947
2948	if (!name)
2949	return NULL;
2950
2951	oh = _lookup(name);
2952
2953	return oh;
2954	}
2955
2956	/**
2957	* omap_hwmod_for_each - call function for each registered omap_hwmod
2958	* @fn: pointer to a callback function
2959	* @data: void * data to pass to callback function
2960	*
2961	* Call @fn for each registered omap_hwmod, passing @data to each
2962	* function. @fn must return 0 for success or any other value for
2963	* failure. If @fn returns non-zero, the iteration across omap_hwmods
2964	* will stop and the non-zero return value will be passed to the
2965	* caller of omap_hwmod_for_each(). @fn is called with
2966	* omap_hwmod_for_each() held.
2967	*/
2968	int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
2969	void *data)
2970	{
2971	struct omap_hwmod *temp_oh;
2972	int ret = 0;
2973
2974	if (!fn)
2975	return -EINVAL;
2976
2977	list_for_each_entry(temp_oh, &omap_hwmod_list, node) {
2978	ret = (*fn)(temp_oh, data);
2979	if (ret)
2980	break;
2981	}
2982
2983	return ret;
2984	}
2985
2986	/**
2987	* omap_hwmod_register_links - register an array of hwmod links
2988	* @ois: pointer to an array of omap_hwmod_ocp_if to register
2989	*
2990	* Intended to be called early in boot before the clock framework is
2991	* initialized. If @ois is not null, will register all omap_hwmods
2992	* listed in @ois that are valid for this chip. Returns -EINVAL if
2993	* omap_hwmod_init() hasn't been called before calling this function,
2994	* -ENOMEM if the link memory area can't be allocated, or 0 upon
2995	* success.
2996	*/
2997	int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois)
2998	{
2999	int r, i;
3000
3001	if (!inited)
3002	return -EINVAL;
3003
3004	if (!ois)
3005	return 0;
3006
3007	if (ois[0] == NULL) /* Empty list */
3008	return 0;
3009
3010	i = 0;
3011	do {
3012	r = _register_link(oi: ois[i]);
3013	WARN(r && r != -EEXIST,
3014	"omap_hwmod: _register_link(%s -> %s) returned %d\n",
3015	ois[i]->master->name, ois[i]->slave->name, r);
3016	} while (ois[++i]);
3017
3018	return 0;
3019	}
3020
3021	static int __init omap_hwmod_setup_one(const char *oh_name);
3022
3023	/**
3024	* _ensure_mpu_hwmod_is_setup - ensure the MPU SS hwmod is init'ed and set up
3025	* @oh: pointer to the hwmod currently being set up (usually not the MPU)
3026	*
3027	* If the hwmod data corresponding to the MPU subsystem IP block
3028	* hasn't been initialized and set up yet, do so now. This must be
3029	* done first since sleep dependencies may be added from other hwmods
3030	* to the MPU. Intended to be called only by omap_hwmod_setup*(). No
3031	* return value.
3032	*/
3033	static void __init _ensure_mpu_hwmod_is_setup(struct omap_hwmod *oh)
3034	{
3035	if (!mpu_oh || mpu_oh->_state == _HWMOD_STATE_UNKNOWN)
3036	pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n",
3037	__func__, MPU_INITIATOR_NAME);
3038	else if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh)
3039	omap_hwmod_setup_one(MPU_INITIATOR_NAME);
3040	}
3041
3042	/**
3043	* omap_hwmod_setup_one - set up a single hwmod
3044	* @oh_name: const char * name of the already-registered hwmod to set up
3045	*
3046	* Initialize and set up a single hwmod. Intended to be used for a
3047	* small number of early devices, such as the timer IP blocks used for
3048	* the scheduler clock. Must be called after omap2_clk_init().
3049	* Resolves the struct clk names to struct clk pointers for each
3050	* registered omap_hwmod. Also calls _setup() on each hwmod. Returns
3051	* -EINVAL upon error or 0 upon success.
3052	*/
3053	static int __init omap_hwmod_setup_one(const char *oh_name)
3054	{
3055	struct omap_hwmod *oh;
3056
3057	pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__);
3058
3059	oh = _lookup(name: oh_name);
3060	if (!oh) {
3061	WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name);
3062	return -EINVAL;
3063	}
3064
3065	_ensure_mpu_hwmod_is_setup(oh);
3066
3067	_init(oh, NULL);
3068	_setup(oh, NULL);
3069
3070	return 0;
3071	}
3072
3073	static void omap_hwmod_check_one(struct device *dev,
3074	const char *name, s8 v1, u8 v2)
3075	{
3076	if (v1 < 0)
3077	return;
3078
3079	if (v1 != v2)
3080	dev_warn(dev, "%s %d != %d\n", name, v1, v2);
3081	}
3082
3083	/**
3084	* omap_hwmod_check_sysc - check sysc against platform sysc
3085	* @dev: struct device
3086	* @data: module data
3087	* @sysc_fields: new sysc configuration
3088	*/
3089	static int omap_hwmod_check_sysc(struct device *dev,
3090	const struct ti_sysc_module_data *data,
3091	struct sysc_regbits *sysc_fields)
3092	{
3093	const struct sysc_regbits *regbits = data->cap->regbits;
3094
3095	omap_hwmod_check_one(dev, name: "dmadisable_shift",
3096	v1: regbits->dmadisable_shift,
3097	v2: sysc_fields->dmadisable_shift);
3098	omap_hwmod_check_one(dev, name: "midle_shift",
3099	v1: regbits->midle_shift,
3100	v2: sysc_fields->midle_shift);
3101	omap_hwmod_check_one(dev, name: "sidle_shift",
3102	v1: regbits->sidle_shift,
3103	v2: sysc_fields->sidle_shift);
3104	omap_hwmod_check_one(dev, name: "clkact_shift",
3105	v1: regbits->clkact_shift,
3106	v2: sysc_fields->clkact_shift);
3107	omap_hwmod_check_one(dev, name: "enwkup_shift",
3108	v1: regbits->enwkup_shift,
3109	v2: sysc_fields->enwkup_shift);
3110	omap_hwmod_check_one(dev, name: "srst_shift",
3111	v1: regbits->srst_shift,
3112	v2: sysc_fields->srst_shift);
3113	omap_hwmod_check_one(dev, name: "autoidle_shift",
3114	v1: regbits->autoidle_shift,
3115	v2: sysc_fields->autoidle_shift);
3116
3117	return 0;
3118	}
3119
3120	/**
3121	* omap_hwmod_init_regbits - init sysconfig specific register bits
3122	* @dev: struct device
3123	* @oh: module
3124	* @data: module data
3125	* @sysc_fields: new sysc configuration
3126	*/
3127	static int omap_hwmod_init_regbits(struct device *dev, struct omap_hwmod *oh,
3128	const struct ti_sysc_module_data *data,
3129	struct sysc_regbits **sysc_fields)
3130	{
3131	switch (data->cap->type) {
3132	case TI_SYSC_OMAP2:
3133	case TI_SYSC_OMAP2_TIMER:
3134	*sysc_fields = &omap_hwmod_sysc_type1;
3135	break;
3136	case TI_SYSC_OMAP3_SHAM:
3137	*sysc_fields = &omap3_sham_sysc_fields;
3138	break;
3139	case TI_SYSC_OMAP3_AES:
3140	*sysc_fields = &omap3xxx_aes_sysc_fields;
3141	break;
3142	case TI_SYSC_OMAP4:
3143	case TI_SYSC_OMAP4_TIMER:
3144	*sysc_fields = &omap_hwmod_sysc_type2;
3145	break;
3146	case TI_SYSC_OMAP4_SIMPLE:
3147	*sysc_fields = &omap_hwmod_sysc_type3;
3148	break;
3149	case TI_SYSC_OMAP34XX_SR:
3150	*sysc_fields = &omap34xx_sr_sysc_fields;
3151	break;
3152	case TI_SYSC_OMAP36XX_SR:
3153	*sysc_fields = &omap36xx_sr_sysc_fields;
3154	break;
3155	case TI_SYSC_OMAP4_SR:
3156	*sysc_fields = &omap36xx_sr_sysc_fields;
3157	break;
3158	case TI_SYSC_OMAP4_MCASP:
3159	*sysc_fields = &omap_hwmod_sysc_type_mcasp;
3160	break;
3161	case TI_SYSC_OMAP4_USB_HOST_FS:
3162	*sysc_fields = &omap_hwmod_sysc_type_usb_host_fs;
3163	break;
3164	default:
3165	*sysc_fields = NULL;
3166	if (!oh->class->sysc->sysc_fields)
3167	return 0;
3168
3169	dev_err(dev, "sysc_fields not found\n");
3170
3171	return -EINVAL;
3172	}
3173
3174	return omap_hwmod_check_sysc(dev, data, sysc_fields: *sysc_fields);
3175	}
3176
3177	/**
3178	* omap_hwmod_init_reg_offs - initialize sysconfig register offsets
3179	* @dev: struct device
3180	* @data: module data
3181	* @rev_offs: revision register offset
3182	* @sysc_offs: sysc register offset
3183	* @syss_offs: syss register offset
3184	*/
3185	static int omap_hwmod_init_reg_offs(struct device *dev,
3186	const struct ti_sysc_module_data *data,
3187	s32 *rev_offs, s32 *sysc_offs,
3188	s32 *syss_offs)
3189	{
3190	*rev_offs = -ENODEV;
3191	*sysc_offs = 0;
3192	*syss_offs = 0;
3193
3194	if (data->offsets[SYSC_REVISION] >= 0)
3195	*rev_offs = data->offsets[SYSC_REVISION];
3196
3197	if (data->offsets[SYSC_SYSCONFIG] >= 0)
3198	*sysc_offs = data->offsets[SYSC_SYSCONFIG];
3199
3200	if (data->offsets[SYSC_SYSSTATUS] >= 0)
3201	*syss_offs = data->offsets[SYSC_SYSSTATUS];
3202
3203	return 0;
3204	}
3205
3206	/**
3207	* omap_hwmod_init_sysc_flags - initialize sysconfig features
3208	* @dev: struct device
3209	* @data: module data
3210	* @sysc_flags: module configuration
3211	*/
3212	static int omap_hwmod_init_sysc_flags(struct device *dev,
3213	const struct ti_sysc_module_data *data,
3214	u32 *sysc_flags)
3215	{
3216	*sysc_flags = 0;
3217
3218	switch (data->cap->type) {
3219	case TI_SYSC_OMAP2:
3220	case TI_SYSC_OMAP2_TIMER:
3221	/* See SYSC_OMAP2_* in include/dt-bindings/bus/ti-sysc.h */
3222	if (data->cfg->sysc_val & SYSC_OMAP2_CLOCKACTIVITY)
3223	*sysc_flags |= SYSC_HAS_CLOCKACTIVITY;
3224	if (data->cfg->sysc_val & SYSC_OMAP2_EMUFREE)
3225	*sysc_flags |= SYSC_HAS_EMUFREE;
3226	if (data->cfg->sysc_val & SYSC_OMAP2_ENAWAKEUP)
3227	*sysc_flags |= SYSC_HAS_ENAWAKEUP;
3228	if (data->cfg->sysc_val & SYSC_OMAP2_SOFTRESET)
3229	*sysc_flags |= SYSC_HAS_SOFTRESET;
3230	if (data->cfg->sysc_val & SYSC_OMAP2_AUTOIDLE)
3231	*sysc_flags |= SYSC_HAS_AUTOIDLE;
3232	break;
3233	case TI_SYSC_OMAP4:
3234	case TI_SYSC_OMAP4_TIMER:
3235	/* See SYSC_OMAP4_* in include/dt-bindings/bus/ti-sysc.h */
3236	if (data->cfg->sysc_val & SYSC_OMAP4_DMADISABLE)
3237	*sysc_flags |= SYSC_HAS_DMADISABLE;
3238	if (data->cfg->sysc_val & SYSC_OMAP4_FREEEMU)
3239	*sysc_flags |= SYSC_HAS_EMUFREE;
3240	if (data->cfg->sysc_val & SYSC_OMAP4_SOFTRESET)
3241	*sysc_flags |= SYSC_HAS_SOFTRESET;
3242	break;
3243	case TI_SYSC_OMAP34XX_SR:
3244	case TI_SYSC_OMAP36XX_SR:
3245	/* See SYSC_OMAP3_SR_* in include/dt-bindings/bus/ti-sysc.h */
3246	if (data->cfg->sysc_val & SYSC_OMAP3_SR_ENAWAKEUP)
3247	*sysc_flags |= SYSC_HAS_ENAWAKEUP;
3248	break;
3249	default:
3250	if (data->cap->regbits->emufree_shift >= 0)
3251	*sysc_flags |= SYSC_HAS_EMUFREE;
3252	if (data->cap->regbits->enwkup_shift >= 0)
3253	*sysc_flags |= SYSC_HAS_ENAWAKEUP;
3254	if (data->cap->regbits->srst_shift >= 0)
3255	*sysc_flags |= SYSC_HAS_SOFTRESET;
3256	if (data->cap->regbits->autoidle_shift >= 0)
3257	*sysc_flags |= SYSC_HAS_AUTOIDLE;
3258	break;
3259	}
3260
3261	if (data->cap->regbits->midle_shift >= 0 &&
3262	data->cfg->midlemodes)
3263	*sysc_flags |= SYSC_HAS_MIDLEMODE;
3264
3265	if (data->cap->regbits->sidle_shift >= 0 &&
3266	data->cfg->sidlemodes)
3267	*sysc_flags |= SYSC_HAS_SIDLEMODE;
3268
3269	if (data->cfg->quirks & SYSC_QUIRK_UNCACHED)
3270	*sysc_flags |= SYSC_NO_CACHE;
3271	if (data->cfg->quirks & SYSC_QUIRK_RESET_STATUS)
3272	*sysc_flags |= SYSC_HAS_RESET_STATUS;
3273
3274	if (data->cfg->syss_mask & 1)
3275	*sysc_flags |= SYSS_HAS_RESET_STATUS;
3276
3277	return 0;
3278	}
3279
3280	/**
3281	* omap_hwmod_init_idlemodes - initialize module idle modes
3282	* @dev: struct device
3283	* @data: module data
3284	* @idlemodes: module supported idle modes
3285	*/
3286	static int omap_hwmod_init_idlemodes(struct device *dev,
3287	const struct ti_sysc_module_data *data,
3288	u32 *idlemodes)
3289	{
3290	*idlemodes = 0;
3291
3292	if (data->cfg->midlemodes & BIT(SYSC_IDLE_FORCE))
3293	*idlemodes |= MSTANDBY_FORCE;
3294	if (data->cfg->midlemodes & BIT(SYSC_IDLE_NO))
3295	*idlemodes |= MSTANDBY_NO;
3296	if (data->cfg->midlemodes & BIT(SYSC_IDLE_SMART))
3297	*idlemodes |= MSTANDBY_SMART;
3298	if (data->cfg->midlemodes & BIT(SYSC_IDLE_SMART_WKUP))
3299	*idlemodes |= MSTANDBY_SMART_WKUP;
3300
3301	if (data->cfg->sidlemodes & BIT(SYSC_IDLE_FORCE))
3302	*idlemodes |= SIDLE_FORCE;
3303	if (data->cfg->sidlemodes & BIT(SYSC_IDLE_NO))
3304	*idlemodes |= SIDLE_NO;
3305	if (data->cfg->sidlemodes & BIT(SYSC_IDLE_SMART))
3306	*idlemodes |= SIDLE_SMART;
3307	if (data->cfg->sidlemodes & BIT(SYSC_IDLE_SMART_WKUP))
3308	*idlemodes |= SIDLE_SMART_WKUP;
3309
3310	return 0;
3311	}
3312
3313	/**
3314	* omap_hwmod_check_module - check new module against platform data
3315	* @dev: struct device
3316	* @oh: module
3317	* @data: new module data
3318	* @sysc_fields: sysc register bits
3319	* @rev_offs: revision register offset
3320	* @sysc_offs: sysconfig register offset
3321	* @syss_offs: sysstatus register offset
3322	* @sysc_flags: sysc specific flags
3323	* @idlemodes: sysc supported idlemodes
3324	*/
3325	static int omap_hwmod_check_module(struct device *dev,
3326	struct omap_hwmod *oh,
3327	const struct ti_sysc_module_data *data,
3328	struct sysc_regbits *sysc_fields,
3329	s32 rev_offs, s32 sysc_offs,
3330	s32 syss_offs, u32 sysc_flags,
3331	u32 idlemodes)
3332	{
3333	if (!oh->class->sysc)
3334	return -ENODEV;
3335
3336	if (oh->class->sysc->sysc_fields &&
3337	sysc_fields != oh->class->sysc->sysc_fields)
3338	dev_warn(dev, "sysc_fields mismatch\n");
3339
3340	if (rev_offs != oh->class->sysc->rev_offs)
3341	dev_warn(dev, "rev_offs %08x != %08x\n", rev_offs,
3342	oh->class->sysc->rev_offs);
3343	if (sysc_offs != oh->class->sysc->sysc_offs)
3344	dev_warn(dev, "sysc_offs %08x != %08x\n", sysc_offs,
3345	oh->class->sysc->sysc_offs);
3346	if (syss_offs != oh->class->sysc->syss_offs)
3347	dev_warn(dev, "syss_offs %08x != %08x\n", syss_offs,
3348	oh->class->sysc->syss_offs);
3349
3350	if (sysc_flags != oh->class->sysc->sysc_flags)
3351	dev_warn(dev, "sysc_flags %08x != %08x\n", sysc_flags,
3352	oh->class->sysc->sysc_flags);
3353
3354	if (idlemodes != oh->class->sysc->idlemodes)
3355	dev_warn(dev, "idlemodes %08x != %08x\n", idlemodes,
3356	oh->class->sysc->idlemodes);
3357
3358	if (data->cfg->srst_udelay != oh->class->sysc->srst_udelay)
3359	dev_warn(dev, "srst_udelay %i != %i\n",
3360	data->cfg->srst_udelay,
3361	oh->class->sysc->srst_udelay);
3362
3363	return 0;
3364	}
3365
3366	/**
3367	* omap_hwmod_allocate_module - allocate new module
3368	* @dev: struct device
3369	* @oh: module
3370	* @sysc_fields: sysc register bits
3371	* @clockdomain: clockdomain
3372	* @rev_offs: revision register offset
3373	* @sysc_offs: sysconfig register offset
3374	* @syss_offs: sysstatus register offset
3375	* @sysc_flags: sysc specific flags
3376	* @idlemodes: sysc supported idlemodes
3377	*
3378	* Note that the allocations here cannot use devm as ti-sysc can rebind.
3379	*/
3380	static int omap_hwmod_allocate_module(struct device *dev, struct omap_hwmod *oh,
3381	const struct ti_sysc_module_data *data,
3382	struct sysc_regbits *sysc_fields,
3383	struct clockdomain *clkdm,
3384	s32 rev_offs, s32 sysc_offs,
3385	s32 syss_offs, u32 sysc_flags,
3386	u32 idlemodes)
3387	{
3388	struct omap_hwmod_class_sysconfig *sysc;
3389	struct omap_hwmod_class *class = NULL;
3390	struct omap_hwmod_ocp_if *oi = NULL;
3391	void __iomem *regs = NULL;
3392	unsigned long flags;
3393
3394	sysc = kzalloc(size: sizeof(*sysc), GFP_KERNEL);
3395	if (!sysc)
3396	return -ENOMEM;
3397
3398	sysc->sysc_fields = sysc_fields;
3399	sysc->rev_offs = rev_offs;
3400	sysc->sysc_offs = sysc_offs;
3401	sysc->syss_offs = syss_offs;
3402	sysc->sysc_flags = sysc_flags;
3403	sysc->idlemodes = idlemodes;
3404	sysc->srst_udelay = data->cfg->srst_udelay;
3405
3406	if (!oh->_mpu_rt_va) {
3407	regs = ioremap(offset: data->module_pa,
3408	size: data->module_size);
3409	if (!regs)
3410	goto out_free_sysc;
3411	}
3412
3413	/*
3414	* We may need a new oh->class as the other devices in the same class
3415	* may not yet have ioremapped their registers.
3416	*/
3417	if (oh->class->name && strcmp(oh->class->name, data->name)) {
3418	class = kmemdup(p: oh->class, size: sizeof(*oh->class), GFP_KERNEL);
3419	if (!class)
3420	goto out_unmap;
3421	}
3422
3423	if (list_empty(head: &oh->slave_ports)) {
3424	oi = kzalloc(size: sizeof(*oi), GFP_KERNEL);
3425	if (!oi)
3426	goto out_free_class;
3427
3428	/*
3429	* Note that we assume interconnect interface clocks will be
3430	* managed by the interconnect driver for OCPIF_SWSUP_IDLE case
3431	* on omap24xx and omap3.
3432	*/
3433	oi->slave = oh;
3434	oi->user = OCP_USER_MPU | OCP_USER_SDMA;
3435	}
3436
3437	spin_lock_irqsave(&oh->_lock, flags);
3438	if (regs)
3439	oh->_mpu_rt_va = regs;
3440	if (class)
3441	oh->class = class;
3442	oh->class->sysc = sysc;
3443	if (oi)
3444	_add_link(oi);
3445	if (clkdm)
3446	oh->clkdm = clkdm;
3447	oh->_state = _HWMOD_STATE_INITIALIZED;
3448	oh->_postsetup_state = _HWMOD_STATE_DEFAULT;
3449	_setup(oh, NULL);
3450	spin_unlock_irqrestore(lock: &oh->_lock, flags);
3451
3452	return 0;
3453
3454	out_free_class:
3455	kfree(objp: class);
3456	out_unmap:
3457	iounmap(addr: regs);
3458	out_free_sysc:
3459	kfree(objp: sysc);
3460	return -ENOMEM;
3461	}
3462
3463	static const struct omap_hwmod_reset omap24xx_reset_quirks[] = {
3464	{ .match = "msdi", .len = 4, .reset = omap_msdi_reset, },
3465	};
3466
3467	static const struct omap_hwmod_reset omap_reset_quirks[] = {
3468	{ .match = "dss_core", .len = 8, .reset = omap_dss_reset, },
3469	{ .match = "hdq1w", .len = 5, .reset = omap_hdq1w_reset, },
3470	{ .match = "i2c", .len = 3, .reset = omap_i2c_reset, },
3471	{ .match = "wd_timer", .len = 8, .reset = omap2_wd_timer_reset, },
3472	};
3473
3474	static void
3475	omap_hwmod_init_reset_quirk(struct device *dev, struct omap_hwmod *oh,
3476	const struct ti_sysc_module_data *data,
3477	const struct omap_hwmod_reset *quirks,
3478	int quirks_sz)
3479	{
3480	const struct omap_hwmod_reset *quirk;
3481	int i;
3482
3483	for (i = 0; i < quirks_sz; i++) {
3484	quirk = &quirks[i];
3485	if (!strncmp(data->name, quirk->match, quirk->len)) {
3486	oh->class->reset = quirk->reset;
3487
3488	return;
3489	}
3490	}
3491	}
3492
3493	static void
3494	omap_hwmod_init_reset_quirks(struct device *dev, struct omap_hwmod *oh,
3495	const struct ti_sysc_module_data *data)
3496	{
3497	if (soc_is_omap24xx())
3498	omap_hwmod_init_reset_quirk(dev, oh, data,
3499	quirks: omap24xx_reset_quirks,
3500	ARRAY_SIZE(omap24xx_reset_quirks));
3501
3502	omap_hwmod_init_reset_quirk(dev, oh, data, quirks: omap_reset_quirks,
3503	ARRAY_SIZE(omap_reset_quirks));
3504	}
3505
3506	/**
3507	* omap_hwmod_init_module - initialize new module
3508	* @dev: struct device
3509	* @data: module data
3510	* @cookie: cookie for the caller to use for later calls
3511	*/
3512	int omap_hwmod_init_module(struct device *dev,
3513	const struct ti_sysc_module_data *data,
3514	struct ti_sysc_cookie *cookie)
3515	{
3516	struct omap_hwmod *oh;
3517	struct sysc_regbits *sysc_fields;
3518	s32 rev_offs, sysc_offs, syss_offs;
3519	u32 sysc_flags, idlemodes;
3520	int error;
3521
3522	if (!dev || !data || !data->name || !cookie)
3523	return -EINVAL;
3524
3525	oh = _lookup(name: data->name);
3526	if (!oh) {
3527	oh = kzalloc(size: sizeof(*oh), GFP_KERNEL);
3528	if (!oh)
3529	return -ENOMEM;
3530
3531	oh->name = data->name;
3532	oh->_state = _HWMOD_STATE_UNKNOWN;
3533	lockdep_register_key(key: &oh->hwmod_key);
3534
3535	/* Unused, can be handled by PRM driver handling resets */
3536	oh->prcm.omap4.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT;
3537
3538	oh->class = kzalloc(size: sizeof(*oh->class), GFP_KERNEL);
3539	if (!oh->class) {
3540	kfree(objp: oh);
3541	return -ENOMEM;
3542	}
3543
3544	omap_hwmod_init_reset_quirks(dev, oh, data);
3545
3546	oh->class->name = data->name;
3547	mutex_lock(&list_lock);
3548	error = _register(oh);
3549	mutex_unlock(lock: &list_lock);
3550	}
3551
3552	cookie->data = oh;
3553
3554	error = omap_hwmod_init_regbits(dev, oh, data, sysc_fields: &sysc_fields);
3555	if (error)
3556	return error;
3557
3558	error = omap_hwmod_init_reg_offs(dev, data, rev_offs: &rev_offs,
3559	sysc_offs: &sysc_offs, syss_offs: &syss_offs);
3560	if (error)
3561	return error;
3562
3563	error = omap_hwmod_init_sysc_flags(dev, data, sysc_flags: &sysc_flags);
3564	if (error)
3565	return error;
3566
3567	error = omap_hwmod_init_idlemodes(dev, data, idlemodes: &idlemodes);
3568	if (error)
3569	return error;
3570
3571	if (data->cfg->quirks & SYSC_QUIRK_NO_IDLE)
3572	oh->flags |= HWMOD_NO_IDLE;
3573	if (data->cfg->quirks & SYSC_QUIRK_NO_IDLE_ON_INIT)
3574	oh->flags |= HWMOD_INIT_NO_IDLE;
3575	if (data->cfg->quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
3576	oh->flags |= HWMOD_INIT_NO_RESET;
3577	if (data->cfg->quirks & SYSC_QUIRK_USE_CLOCKACT)
3578	oh->flags |= HWMOD_SET_DEFAULT_CLOCKACT;
3579	if (data->cfg->quirks & SYSC_QUIRK_SWSUP_SIDLE)
3580	oh->flags |= HWMOD_SWSUP_SIDLE;
3581	if (data->cfg->quirks & SYSC_QUIRK_SWSUP_SIDLE_ACT)
3582	oh->flags |= HWMOD_SWSUP_SIDLE_ACT;
3583	if (data->cfg->quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
3584	oh->flags |= HWMOD_SWSUP_MSTANDBY;
3585	if (data->cfg->quirks & SYSC_QUIRK_CLKDM_NOAUTO)
3586	oh->flags |= HWMOD_CLKDM_NOAUTO;
3587
3588	error = omap_hwmod_check_module(dev, oh, data, sysc_fields,
3589	rev_offs, sysc_offs, syss_offs,
3590	sysc_flags, idlemodes);
3591	if (!error)
3592	return error;
3593
3594	return omap_hwmod_allocate_module(dev, oh, data, sysc_fields,
3595	clkdm: cookie->clkdm, rev_offs,
3596	sysc_offs, syss_offs,
3597	sysc_flags, idlemodes);
3598	}
3599
3600	/**
3601	* omap_hwmod_setup_earlycon_flags - set up flags for early console
3602	*
3603	* Enable DEBUG_OMAPUART_FLAGS for uart hwmod that is being used as
3604	* early concole so that hwmod core doesn't reset and keep it in idle
3605	* that specific uart.
3606	*/
3607	#ifdef CONFIG_SERIAL_EARLYCON
3608	static void __init omap_hwmod_setup_earlycon_flags(void)
3609	{
3610	struct device_node *np;
3611	struct omap_hwmod *oh;
3612	const char *uart;
3613
3614	np = of_find_node_by_path(path: "/chosen");
3615	if (np) {
3616	uart = of_get_property(node: np, name: "stdout-path", NULL);
3617	if (uart) {
3618	np = of_find_node_by_path(path: uart);
3619	if (np) {
3620	uart = of_get_property(node: np, name: "ti,hwmods", NULL);
3621	oh = omap_hwmod_lookup(name: uart);
3622	if (!oh) {
3623	uart = of_get_property(node: np->parent,
3624	name: "ti,hwmods",
3625	NULL);
3626	oh = omap_hwmod_lookup(name: uart);
3627	}
3628	if (oh)
3629	oh->flags |= DEBUG_OMAPUART_FLAGS;
3630	}
3631	}
3632	}
3633	}
3634	#endif
3635
3636	/**
3637	* omap_hwmod_setup_all - set up all registered IP blocks
3638	*
3639	* Initialize and set up all IP blocks registered with the hwmod code.
3640	* Must be called after omap2_clk_init(). Resolves the struct clk
3641	* names to struct clk pointers for each registered omap_hwmod. Also
3642	* calls _setup() on each hwmod. Returns 0 upon success.
3643	*/
3644	static int __init omap_hwmod_setup_all(void)
3645	{
3646	if (!inited)
3647	return 0;
3648
3649	_ensure_mpu_hwmod_is_setup(NULL);
3650
3651	omap_hwmod_for_each(fn: _init, NULL);
3652	#ifdef CONFIG_SERIAL_EARLYCON
3653	omap_hwmod_setup_earlycon_flags();
3654	#endif
3655	omap_hwmod_for_each(fn: _setup, NULL);
3656
3657	return 0;
3658	}
3659	omap_postcore_initcall(omap_hwmod_setup_all);
3660
3661	/**
3662	* omap_hwmod_enable - enable an omap_hwmod
3663	* @oh: struct omap_hwmod *
3664	*
3665	* Enable an omap_hwmod @oh. Intended to be called by omap_device_enable().
3666	* Returns -EINVAL on error or passes along the return value from _enable().
3667	*/
3668	int omap_hwmod_enable(struct omap_hwmod *oh)
3669	{
3670	int r;
3671	unsigned long flags;
3672
3673	if (!oh)
3674	return -EINVAL;
3675
3676	spin_lock_irqsave(&oh->_lock, flags);
3677	r = _enable(oh);
3678	spin_unlock_irqrestore(lock: &oh->_lock, flags);
3679
3680	return r;
3681	}
3682
3683	/**
3684	* omap_hwmod_idle - idle an omap_hwmod
3685	* @oh: struct omap_hwmod *
3686	*
3687	* Idle an omap_hwmod @oh. Intended to be called by omap_device_idle().
3688	* Returns -EINVAL on error or passes along the return value from _idle().
3689	*/
3690	int omap_hwmod_idle(struct omap_hwmod *oh)
3691	{
3692	int r;
3693	unsigned long flags;
3694
3695	if (!oh)
3696	return -EINVAL;
3697
3698	spin_lock_irqsave(&oh->_lock, flags);
3699	r = _idle(oh);
3700	spin_unlock_irqrestore(lock: &oh->_lock, flags);
3701
3702	return r;
3703	}
3704
3705	/**
3706	* omap_hwmod_shutdown - shutdown an omap_hwmod
3707	* @oh: struct omap_hwmod *
3708	*
3709	* Shutdown an omap_hwmod @oh. Intended to be called by
3710	* omap_device_shutdown(). Returns -EINVAL on error or passes along
3711	* the return value from _shutdown().
3712	*/
3713	int omap_hwmod_shutdown(struct omap_hwmod *oh)
3714	{
3715	int r;
3716	unsigned long flags;
3717
3718	if (!oh)
3719	return -EINVAL;
3720
3721	spin_lock_irqsave(&oh->_lock, flags);
3722	r = _shutdown(oh);
3723	spin_unlock_irqrestore(lock: &oh->_lock, flags);
3724
3725	return r;
3726	}
3727
3728	/*
3729	* IP block data retrieval functions
3730	*/
3731
3732	/**
3733	* omap_hwmod_get_mpu_rt_va - return the module's base address (for the MPU)
3734	* @oh: struct omap_hwmod *
3735	*
3736	* Returns the virtual address corresponding to the beginning of the
3737	* module's register target, in the address range that is intended to
3738	* be used by the MPU. Returns the virtual address upon success or NULL
3739	* upon error.
3740	*/
3741	void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh)
3742	{
3743	if (!oh)
3744	return NULL;
3745
3746	if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
3747	return NULL;
3748
3749	if (oh->_state == _HWMOD_STATE_UNKNOWN)
3750	return NULL;
3751
3752	return oh->_mpu_rt_va;
3753	}
3754
3755	/*
3756	* XXX what about functions for drivers to save/restore ocp_sysconfig
3757	* for context save/restore operations?
3758	*/
3759
3760	/**
3761	* omap_hwmod_assert_hardreset - assert the HW reset line of submodules
3762	* contained in the hwmod module.
3763	* @oh: struct omap_hwmod *
3764	* @name: name of the reset line to lookup and assert
3765	*
3766	* Some IP like dsp, ipu or iva contain processor that require
3767	* an HW reset line to be assert / deassert in order to enable fully
3768	* the IP. Returns -EINVAL if @oh is null or if the operation is not
3769	* yet supported on this OMAP; otherwise, passes along the return value
3770	* from _assert_hardreset().
3771	*/
3772	int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name)
3773	{
3774	int ret;
3775	unsigned long flags;
3776
3777	if (!oh)
3778	return -EINVAL;
3779
3780	spin_lock_irqsave(&oh->_lock, flags);
3781	ret = _assert_hardreset(oh, name);
3782	spin_unlock_irqrestore(lock: &oh->_lock, flags);
3783
3784	return ret;
3785	}
3786
3787	/**
3788	* omap_hwmod_deassert_hardreset - deassert the HW reset line of submodules
3789	* contained in the hwmod module.
3790	* @oh: struct omap_hwmod *
3791	* @name: name of the reset line to look up and deassert
3792	*
3793	* Some IP like dsp, ipu or iva contain processor that require
3794	* an HW reset line to be assert / deassert in order to enable fully
3795	* the IP. Returns -EINVAL if @oh is null or if the operation is not
3796	* yet supported on this OMAP; otherwise, passes along the return value
3797	* from _deassert_hardreset().
3798	*/
3799	int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name)
3800	{
3801	int ret;
3802	unsigned long flags;
3803
3804	if (!oh)
3805	return -EINVAL;
3806
3807	spin_lock_irqsave(&oh->_lock, flags);
3808	ret = _deassert_hardreset(oh, name);
3809	spin_unlock_irqrestore(lock: &oh->_lock, flags);
3810
3811	return ret;
3812	}
3813
3814	/**
3815	* omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname
3816	* @classname: struct omap_hwmod_class name to search for
3817	* @fn: callback function pointer to call for each hwmod in class @classname
3818	* @user: arbitrary context data to pass to the callback function
3819	*
3820	* For each omap_hwmod of class @classname, call @fn.
3821	* If the callback function returns something other than
3822	* zero, the iterator is terminated, and the callback function's return
3823	* value is passed back to the caller. Returns 0 upon success, -EINVAL
3824	* if @classname or @fn are NULL, or passes back the error code from @fn.
3825	*/
3826	int omap_hwmod_for_each_by_class(const char *classname,
3827	int (*fn)(struct omap_hwmod *oh,
3828	void *user),
3829	void *user)
3830	{
3831	struct omap_hwmod *temp_oh;
3832	int ret = 0;
3833
3834	if (!classname || !fn)
3835	return -EINVAL;
3836
3837	pr_debug("omap_hwmod: %s: looking for modules of class %s\n",
3838	__func__, classname);
3839
3840	list_for_each_entry(temp_oh, &omap_hwmod_list, node) {
3841	if (!strcmp(temp_oh->class->name, classname)) {
3842	pr_debug("omap_hwmod: %s: %s: calling callback fn\n",
3843	__func__, temp_oh->name);
3844	ret = (*fn)(temp_oh, user);
3845	if (ret)
3846	break;
3847	}
3848	}
3849
3850	if (ret)
3851	pr_debug("omap_hwmod: %s: iterator terminated early: %d\n",
3852	__func__, ret);
3853
3854	return ret;
3855	}
3856
3857	/**
3858	* omap_hwmod_set_postsetup_state - set the post-_setup() state for this hwmod
3859	* @oh: struct omap_hwmod *
3860	* @state: state that _setup() should leave the hwmod in
3861	*
3862	* Sets the hwmod state that @oh will enter at the end of _setup()
3863	* (called by omap_hwmod_setup_*()). See also the documentation
3864	* for _setup_postsetup(), above. Returns 0 upon success or
3865	* -EINVAL if there is a problem with the arguments or if the hwmod is
3866	* in the wrong state.
3867	*/
3868	int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state)
3869	{
3870	int ret;
3871	unsigned long flags;
3872
3873	if (!oh)
3874	return -EINVAL;
3875
3876	if (state != _HWMOD_STATE_DISABLED &&
3877	state != _HWMOD_STATE_ENABLED &&
3878	state != _HWMOD_STATE_IDLE)
3879	return -EINVAL;
3880
3881	spin_lock_irqsave(&oh->_lock, flags);
3882
3883	if (oh->_state != _HWMOD_STATE_REGISTERED) {
3884	ret = -EINVAL;
3885	goto ohsps_unlock;
3886	}
3887
3888	oh->_postsetup_state = state;
3889	ret = 0;
3890
3891	ohsps_unlock:
3892	spin_unlock_irqrestore(lock: &oh->_lock, flags);
3893
3894	return ret;
3895	}
3896
3897	/**
3898	* omap_hwmod_init - initialize the hwmod code
3899	*
3900	* Sets up some function pointers needed by the hwmod code to operate on the
3901	* currently-booted SoC. Intended to be called once during kernel init
3902	* before any hwmods are registered. No return value.
3903	*/
3904	void __init omap_hwmod_init(void)
3905	{
3906	if (cpu_is_omap24xx()) {
3907	soc_ops.wait_target_ready = _omap2xxx_3xxx_wait_target_ready;
3908	soc_ops.assert_hardreset = _omap2_assert_hardreset;
3909	soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
3910	soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
3911	} else if (cpu_is_omap34xx()) {
3912	soc_ops.wait_target_ready = _omap2xxx_3xxx_wait_target_ready;
3913	soc_ops.assert_hardreset = _omap2_assert_hardreset;
3914	soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
3915	soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
3916	soc_ops.init_clkdm = _init_clkdm;
3917	} else if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
3918	soc_ops.enable_module = _omap4_enable_module;
3919	soc_ops.disable_module = _omap4_disable_module;
3920	soc_ops.wait_target_ready = _omap4_wait_target_ready;
3921	soc_ops.assert_hardreset = _omap4_assert_hardreset;
3922	soc_ops.deassert_hardreset = _omap4_deassert_hardreset;
3923	soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
3924	soc_ops.init_clkdm = _init_clkdm;
3925	soc_ops.update_context_lost = _omap4_update_context_lost;
3926	soc_ops.get_context_lost = _omap4_get_context_lost;
3927	soc_ops.disable_direct_prcm = _omap4_disable_direct_prcm;
3928	soc_ops.xlate_clkctrl = _omap4_xlate_clkctrl;
3929	} else if (cpu_is_ti814x() || cpu_is_ti816x() || soc_is_am33xx() ||
3930	soc_is_am43xx()) {
3931	soc_ops.enable_module = _omap4_enable_module;
3932	soc_ops.disable_module = _omap4_disable_module;
3933	soc_ops.wait_target_ready = _omap4_wait_target_ready;
3934	soc_ops.assert_hardreset = _omap4_assert_hardreset;
3935	soc_ops.deassert_hardreset = _am33xx_deassert_hardreset;
3936	soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
3937	soc_ops.init_clkdm = _init_clkdm;
3938	soc_ops.disable_direct_prcm = _omap4_disable_direct_prcm;
3939	soc_ops.xlate_clkctrl = _omap4_xlate_clkctrl;
3940	} else {
3941	WARN(1, "omap_hwmod: unknown SoC type\n");
3942	}
3943
3944	_init_clkctrl_providers();
3945
3946	inited = true;
3947	}
3948