1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * omap_hwmod macros, structures |
4 | * |
5 | * Copyright (C) 2009-2011 Nokia Corporation |
6 | * Copyright (C) 2011-2012 Texas Instruments, Inc. |
7 | * Paul Walmsley |
8 | * |
9 | * Created in collaboration with (alphabetical order): BenoƮt Cousson, |
10 | * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari |
11 | * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff |
12 | * |
13 | * These headers and macros are used to define OMAP on-chip module |
14 | * data and their integration with other OMAP modules and Linux. |
15 | * Copious documentation and references can also be found in the |
16 | * omap_hwmod code, in arch/arm/mach-omap2/omap_hwmod.c (as of this |
17 | * writing). |
18 | * |
19 | * To do: |
20 | * - add interconnect error log structures |
21 | * - init_conn_id_bit (CONNID_BIT_VECTOR) |
22 | * - implement default hwmod SMS/SDRC flags? |
23 | * - move Linux-specific data ("non-ROM data") out |
24 | */ |
25 | #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H |
26 | #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H |
27 | |
28 | #include <linux/kernel.h> |
29 | #include <linux/init.h> |
30 | #include <linux/list.h> |
31 | #include <linux/ioport.h> |
32 | #include <linux/spinlock.h> |
33 | |
34 | struct omap_device; |
35 | |
36 | extern struct sysc_regbits omap_hwmod_sysc_type1; |
37 | extern struct sysc_regbits omap_hwmod_sysc_type2; |
38 | extern struct sysc_regbits omap_hwmod_sysc_type3; |
39 | extern struct sysc_regbits omap34xx_sr_sysc_fields; |
40 | extern struct sysc_regbits omap36xx_sr_sysc_fields; |
41 | extern struct sysc_regbits omap3_sham_sysc_fields; |
42 | extern struct sysc_regbits omap3xxx_aes_sysc_fields; |
43 | extern struct sysc_regbits omap_hwmod_sysc_type_mcasp; |
44 | extern struct sysc_regbits omap_hwmod_sysc_type_usb_host_fs; |
45 | |
46 | /* |
47 | * OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant |
48 | * with the original PRCM protocol defined for OMAP2420 |
49 | */ |
50 | #define SYSC_TYPE1_MIDLEMODE_SHIFT 12 |
51 | #define SYSC_TYPE1_MIDLEMODE_MASK (0x3 << SYSC_TYPE1_MIDLEMODE_SHIFT) |
52 | #define SYSC_TYPE1_CLOCKACTIVITY_SHIFT 8 |
53 | #define SYSC_TYPE1_CLOCKACTIVITY_MASK (0x3 << SYSC_TYPE1_CLOCKACTIVITY_SHIFT) |
54 | #define SYSC_TYPE1_SIDLEMODE_SHIFT 3 |
55 | #define SYSC_TYPE1_SIDLEMODE_MASK (0x3 << SYSC_TYPE1_SIDLEMODE_SHIFT) |
56 | #define SYSC_TYPE1_ENAWAKEUP_SHIFT 2 |
57 | #define SYSC_TYPE1_ENAWAKEUP_MASK (1 << SYSC_TYPE1_ENAWAKEUP_SHIFT) |
58 | #define SYSC_TYPE1_SOFTRESET_SHIFT 1 |
59 | #define SYSC_TYPE1_SOFTRESET_MASK (1 << SYSC_TYPE1_SOFTRESET_SHIFT) |
60 | #define SYSC_TYPE1_AUTOIDLE_SHIFT 0 |
61 | #define SYSC_TYPE1_AUTOIDLE_MASK (1 << SYSC_TYPE1_AUTOIDLE_SHIFT) |
62 | |
63 | /* |
64 | * OCP SYSCONFIG bit shifts/masks TYPE2. These are for IPs compliant |
65 | * with the new PRCM protocol defined for new OMAP4 IPs. |
66 | */ |
67 | #define SYSC_TYPE2_SOFTRESET_SHIFT 0 |
68 | #define SYSC_TYPE2_SOFTRESET_MASK (1 << SYSC_TYPE2_SOFTRESET_SHIFT) |
69 | #define SYSC_TYPE2_SIDLEMODE_SHIFT 2 |
70 | #define SYSC_TYPE2_SIDLEMODE_MASK (0x3 << SYSC_TYPE2_SIDLEMODE_SHIFT) |
71 | #define SYSC_TYPE2_MIDLEMODE_SHIFT 4 |
72 | #define SYSC_TYPE2_MIDLEMODE_MASK (0x3 << SYSC_TYPE2_MIDLEMODE_SHIFT) |
73 | #define SYSC_TYPE2_DMADISABLE_SHIFT 16 |
74 | #define SYSC_TYPE2_DMADISABLE_MASK (0x1 << SYSC_TYPE2_DMADISABLE_SHIFT) |
75 | |
76 | /* |
77 | * OCP SYSCONFIG bit shifts/masks TYPE3. |
78 | * This is applicable for some IPs present in AM33XX |
79 | */ |
80 | #define SYSC_TYPE3_SIDLEMODE_SHIFT 0 |
81 | #define SYSC_TYPE3_SIDLEMODE_MASK (0x3 << SYSC_TYPE3_SIDLEMODE_SHIFT) |
82 | #define SYSC_TYPE3_MIDLEMODE_SHIFT 2 |
83 | #define SYSC_TYPE3_MIDLEMODE_MASK (0x3 << SYSC_TYPE3_MIDLEMODE_SHIFT) |
84 | |
85 | /* OCP SYSSTATUS bit shifts/masks */ |
86 | #define SYSS_RESETDONE_SHIFT 0 |
87 | #define SYSS_RESETDONE_MASK (1 << SYSS_RESETDONE_SHIFT) |
88 | |
89 | /* Master standby/slave idle mode flags */ |
90 | #define HWMOD_IDLEMODE_FORCE (1 << 0) |
91 | #define HWMOD_IDLEMODE_NO (1 << 1) |
92 | #define HWMOD_IDLEMODE_SMART (1 << 2) |
93 | #define HWMOD_IDLEMODE_SMART_WKUP (1 << 3) |
94 | |
95 | /* modulemode control type (SW or HW) */ |
96 | #define MODULEMODE_HWCTRL 1 |
97 | #define MODULEMODE_SWCTRL 2 |
98 | |
99 | #define DEBUG_OMAP2UART1_FLAGS 0 |
100 | #define DEBUG_OMAP2UART2_FLAGS 0 |
101 | #define DEBUG_OMAP2UART3_FLAGS 0 |
102 | #define DEBUG_OMAP3UART3_FLAGS 0 |
103 | #define DEBUG_OMAP3UART4_FLAGS 0 |
104 | #define DEBUG_OMAP4UART3_FLAGS 0 |
105 | #define DEBUG_OMAP4UART4_FLAGS 0 |
106 | #define DEBUG_TI81XXUART1_FLAGS 0 |
107 | #define DEBUG_TI81XXUART2_FLAGS 0 |
108 | #define DEBUG_TI81XXUART3_FLAGS 0 |
109 | #define DEBUG_AM33XXUART1_FLAGS 0 |
110 | |
111 | #define DEBUG_OMAPUART_FLAGS (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET) |
112 | |
113 | #ifdef CONFIG_OMAP_GPMC_DEBUG |
114 | #define DEBUG_OMAP_GPMC_HWMOD_FLAGS HWMOD_INIT_NO_RESET |
115 | #else |
116 | #define DEBUG_OMAP_GPMC_HWMOD_FLAGS 0 |
117 | #endif |
118 | |
119 | #if defined(CONFIG_DEBUG_OMAP2UART1) |
120 | #undef DEBUG_OMAP2UART1_FLAGS |
121 | #define DEBUG_OMAP2UART1_FLAGS DEBUG_OMAPUART_FLAGS |
122 | #elif defined(CONFIG_DEBUG_OMAP2UART2) |
123 | #undef DEBUG_OMAP2UART2_FLAGS |
124 | #define DEBUG_OMAP2UART2_FLAGS DEBUG_OMAPUART_FLAGS |
125 | #elif defined(CONFIG_DEBUG_OMAP2UART3) |
126 | #undef DEBUG_OMAP2UART3_FLAGS |
127 | #define DEBUG_OMAP2UART3_FLAGS DEBUG_OMAPUART_FLAGS |
128 | #elif defined(CONFIG_DEBUG_OMAP3UART3) |
129 | #undef DEBUG_OMAP3UART3_FLAGS |
130 | #define DEBUG_OMAP3UART3_FLAGS DEBUG_OMAPUART_FLAGS |
131 | #elif defined(CONFIG_DEBUG_OMAP3UART4) |
132 | #undef DEBUG_OMAP3UART4_FLAGS |
133 | #define DEBUG_OMAP3UART4_FLAGS DEBUG_OMAPUART_FLAGS |
134 | #elif defined(CONFIG_DEBUG_OMAP4UART3) |
135 | #undef DEBUG_OMAP4UART3_FLAGS |
136 | #define DEBUG_OMAP4UART3_FLAGS DEBUG_OMAPUART_FLAGS |
137 | #elif defined(CONFIG_DEBUG_OMAP4UART4) |
138 | #undef DEBUG_OMAP4UART4_FLAGS |
139 | #define DEBUG_OMAP4UART4_FLAGS DEBUG_OMAPUART_FLAGS |
140 | #elif defined(CONFIG_DEBUG_TI81XXUART1) |
141 | #undef DEBUG_TI81XXUART1_FLAGS |
142 | #define DEBUG_TI81XXUART1_FLAGS DEBUG_OMAPUART_FLAGS |
143 | #elif defined(CONFIG_DEBUG_TI81XXUART2) |
144 | #undef DEBUG_TI81XXUART2_FLAGS |
145 | #define DEBUG_TI81XXUART2_FLAGS DEBUG_OMAPUART_FLAGS |
146 | #elif defined(CONFIG_DEBUG_TI81XXUART3) |
147 | #undef DEBUG_TI81XXUART3_FLAGS |
148 | #define DEBUG_TI81XXUART3_FLAGS DEBUG_OMAPUART_FLAGS |
149 | #elif defined(CONFIG_DEBUG_AM33XXUART1) |
150 | #undef DEBUG_AM33XXUART1_FLAGS |
151 | #define DEBUG_AM33XXUART1_FLAGS DEBUG_OMAPUART_FLAGS |
152 | #endif |
153 | |
154 | /** |
155 | * struct omap_hwmod_rst_info - IPs reset lines use by hwmod |
156 | * @name: name of the reset line (module local name) |
157 | * @rst_shift: Offset of the reset bit |
158 | * @st_shift: Offset of the reset status bit (OMAP2/3 only) |
159 | * |
160 | * @name should be something short, e.g., "cpu0" or "rst". It is defined |
161 | * locally to the hwmod. |
162 | */ |
163 | struct omap_hwmod_rst_info { |
164 | const char *name; |
165 | u8 rst_shift; |
166 | u8 st_shift; |
167 | }; |
168 | |
169 | /** |
170 | * struct omap_hwmod_opt_clk - optional clocks used by this hwmod |
171 | * @role: "sys", "32k", "tv", etc -- for use in clk_get() |
172 | * @clk: opt clock: OMAP clock name |
173 | * @_clk: pointer to the struct clk (filled in at runtime) |
174 | * |
175 | * The module's interface clock and main functional clock should not |
176 | * be added as optional clocks. |
177 | */ |
178 | struct omap_hwmod_opt_clk { |
179 | const char *role; |
180 | const char *clk; |
181 | struct clk *_clk; |
182 | }; |
183 | |
184 | |
185 | /* omap_hwmod_omap2_firewall.flags bits */ |
186 | #define OMAP_FIREWALL_L3 (1 << 0) |
187 | #define OMAP_FIREWALL_L4 (1 << 1) |
188 | |
189 | /** |
190 | * struct omap_hwmod_omap2_firewall - OMAP2/3 device firewall data |
191 | * @l3_perm_bit: bit shift for L3_PM_*_PERMISSION_* |
192 | * @l4_fw_region: L4 firewall region ID |
193 | * @l4_prot_group: L4 protection group ID |
194 | * @flags: (see omap_hwmod_omap2_firewall.flags macros above) |
195 | */ |
196 | struct omap_hwmod_omap2_firewall { |
197 | u8 l3_perm_bit; |
198 | u8 l4_fw_region; |
199 | u8 l4_prot_group; |
200 | u8 flags; |
201 | }; |
202 | |
203 | /* |
204 | * omap_hwmod_ocp_if.user bits: these indicate the initiators that use this |
205 | * interface to interact with the hwmod. Used to add sleep dependencies |
206 | * when the module is enabled or disabled. |
207 | */ |
208 | #define OCP_USER_MPU (1 << 0) |
209 | #define OCP_USER_SDMA (1 << 1) |
210 | #define OCP_USER_DSP (1 << 2) |
211 | #define OCP_USER_IVA (1 << 3) |
212 | |
213 | /* omap_hwmod_ocp_if.flags bits */ |
214 | #define OCPIF_SWSUP_IDLE (1 << 0) |
215 | #define OCPIF_CAN_BURST (1 << 1) |
216 | |
217 | /* omap_hwmod_ocp_if._int_flags possibilities */ |
218 | #define _OCPIF_INT_FLAGS_REGISTERED (1 << 0) |
219 | |
220 | |
221 | /** |
222 | * struct omap_hwmod_ocp_if - OCP interface data |
223 | * @master: struct omap_hwmod that initiates OCP transactions on this link |
224 | * @slave: struct omap_hwmod that responds to OCP transactions on this link |
225 | * @addr: address space associated with this link |
226 | * @clk: interface clock: OMAP clock name |
227 | * @_clk: pointer to the interface struct clk (filled in at runtime) |
228 | * @fw: interface firewall data |
229 | * @width: OCP data width |
230 | * @user: initiators using this interface (see OCP_USER_* macros above) |
231 | * @flags: OCP interface flags (see OCPIF_* macros above) |
232 | * @_int_flags: internal flags (see _OCPIF_INT_FLAGS* macros above) |
233 | * |
234 | * It may also be useful to add a tag_cnt field for OCP2.x devices. |
235 | * |
236 | * Parameter names beginning with an underscore are managed internally by |
237 | * the omap_hwmod code and should not be set during initialization. |
238 | */ |
239 | struct omap_hwmod_ocp_if { |
240 | struct omap_hwmod *master; |
241 | struct omap_hwmod *slave; |
242 | struct omap_hwmod_addr_space *addr; |
243 | const char *clk; |
244 | struct clk *_clk; |
245 | struct list_head node; |
246 | union { |
247 | struct omap_hwmod_omap2_firewall omap2; |
248 | } fw; |
249 | u8 width; |
250 | u8 user; |
251 | u8 flags; |
252 | u8 _int_flags; |
253 | }; |
254 | |
255 | |
256 | /* Macros for use in struct omap_hwmod_sysconfig */ |
257 | |
258 | /* Flags for use in omap_hwmod_sysconfig.idlemodes */ |
259 | #define MASTER_STANDBY_SHIFT 4 |
260 | #define SLAVE_IDLE_SHIFT 0 |
261 | #define SIDLE_FORCE (HWMOD_IDLEMODE_FORCE << SLAVE_IDLE_SHIFT) |
262 | #define SIDLE_NO (HWMOD_IDLEMODE_NO << SLAVE_IDLE_SHIFT) |
263 | #define SIDLE_SMART (HWMOD_IDLEMODE_SMART << SLAVE_IDLE_SHIFT) |
264 | #define SIDLE_SMART_WKUP (HWMOD_IDLEMODE_SMART_WKUP << SLAVE_IDLE_SHIFT) |
265 | #define MSTANDBY_FORCE (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT) |
266 | #define MSTANDBY_NO (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT) |
267 | #define MSTANDBY_SMART (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT) |
268 | #define MSTANDBY_SMART_WKUP (HWMOD_IDLEMODE_SMART_WKUP << MASTER_STANDBY_SHIFT) |
269 | |
270 | /* omap_hwmod_sysconfig.sysc_flags capability flags */ |
271 | #define SYSC_HAS_AUTOIDLE (1 << 0) |
272 | #define SYSC_HAS_SOFTRESET (1 << 1) |
273 | #define SYSC_HAS_ENAWAKEUP (1 << 2) |
274 | #define SYSC_HAS_EMUFREE (1 << 3) |
275 | #define SYSC_HAS_CLOCKACTIVITY (1 << 4) |
276 | #define SYSC_HAS_SIDLEMODE (1 << 5) |
277 | #define SYSC_HAS_MIDLEMODE (1 << 6) |
278 | #define SYSS_HAS_RESET_STATUS (1 << 7) |
279 | #define SYSC_NO_CACHE (1 << 8) /* XXX SW flag, belongs elsewhere */ |
280 | #define SYSC_HAS_RESET_STATUS (1 << 9) |
281 | #define SYSC_HAS_DMADISABLE (1 << 10) |
282 | |
283 | /* omap_hwmod_sysconfig.clockact flags */ |
284 | #define CLOCKACT_TEST_BOTH 0x0 |
285 | #define CLOCKACT_TEST_MAIN 0x1 |
286 | #define CLOCKACT_TEST_ICLK 0x2 |
287 | #define CLOCKACT_TEST_NONE 0x3 |
288 | |
289 | /** |
290 | * struct omap_hwmod_class_sysconfig - hwmod class OCP_SYS* data |
291 | * @rev_offs: IP block revision register offset (from module base addr) |
292 | * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr) |
293 | * @syss_offs: OCP_SYSSTATUS register offset (from module base addr) |
294 | * @srst_udelay: Delay needed after doing a softreset in usecs |
295 | * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART} |
296 | * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported |
297 | * @clockact: the default value of the module CLOCKACTIVITY bits |
298 | * |
299 | * @clockact describes to the module which clocks are likely to be |
300 | * disabled when the PRCM issues its idle request to the module. Some |
301 | * modules have separate clockdomains for the interface clock and main |
302 | * functional clock, and can check whether they should acknowledge the |
303 | * idle request based on the internal module functionality that has |
304 | * been associated with the clocks marked in @clockact. This field is |
305 | * only used if HWMOD_SET_DEFAULT_CLOCKACT is set (see below) |
306 | * |
307 | * @sysc_fields: structure containing the offset positions of various bits in |
308 | * SYSCONFIG register. This can be populated using omap_hwmod_sysc_type1 or |
309 | * omap_hwmod_sysc_type2 defined in omap_hwmod_common_data.c depending on |
310 | * whether the device ip is compliant with the original PRCM protocol |
311 | * defined for OMAP2420 or the new PRCM protocol for new OMAP4 IPs. |
312 | * If the device follows a different scheme for the sysconfig register , |
313 | * then this field has to be populated with the correct offset structure. |
314 | */ |
315 | struct omap_hwmod_class_sysconfig { |
316 | s32 rev_offs; |
317 | s32 sysc_offs; |
318 | s32 syss_offs; |
319 | u16 sysc_flags; |
320 | struct sysc_regbits *sysc_fields; |
321 | u8 srst_udelay; |
322 | u8 idlemodes; |
323 | }; |
324 | |
325 | /** |
326 | * struct omap_hwmod_omap2_prcm - OMAP2/3-specific PRCM data |
327 | * @module_offs: PRCM submodule offset from the start of the PRM/CM |
328 | * @idlest_reg_id: IDLEST register ID (e.g., 3 for CM_IDLEST3) |
329 | * @idlest_idle_bit: register bit shift for CM_IDLEST slave idle bit |
330 | * |
331 | * @prcm_reg_id and @module_bit are specific to the AUTOIDLE, WKST, |
332 | * WKEN, GRPSEL registers. In an ideal world, no extra information |
333 | * would be needed for IDLEST information, but alas, there are some |
334 | * exceptions, so @idlest_reg_id, @idlest_idle_bit, @idlest_stdby_bit |
335 | * are needed for the IDLEST registers (c.f. 2430 I2CHS, 3430 USBHOST) |
336 | */ |
337 | struct omap_hwmod_omap2_prcm { |
338 | s16 module_offs; |
339 | u8 idlest_reg_id; |
340 | u8 idlest_idle_bit; |
341 | }; |
342 | |
343 | /* |
344 | * Possible values for struct omap_hwmod_omap4_prcm.flags |
345 | * |
346 | * HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT: Some IP blocks don't have a PRCM |
347 | * module-level context loss register associated with them; this |
348 | * flag bit should be set in those cases |
349 | * HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET: Some IP blocks have a valid CLKCTRL |
350 | * offset of zero; this flag bit should be set in those cases to |
351 | * distinguish from hwmods that have no clkctrl offset. |
352 | * HWMOD_OMAP4_CLKFWK_CLKCTR_CLOCK: Module clockctrl clock is managed |
353 | * by the common clock framework and not hwmod. |
354 | */ |
355 | #define HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT (1 << 0) |
356 | #define HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET (1 << 1) |
357 | #define HWMOD_OMAP4_CLKFWK_CLKCTR_CLOCK (1 << 2) |
358 | |
359 | /** |
360 | * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data |
361 | * @clkctrl_offs: offset of the PRCM clock control register |
362 | * @rstctrl_offs: offset of the XXX_RSTCTRL register located in the PRM |
363 | * @context_offs: offset of the RM_*_CONTEXT register |
364 | * @lostcontext_mask: bitmask for selecting bits from RM_*_CONTEXT register |
365 | * @rstst_reg: (AM33XX only) address of the XXX_RSTST register in the PRM |
366 | * @submodule_wkdep_bit: bit shift of the WKDEP range |
367 | * @flags: PRCM register capabilities for this IP block |
368 | * @modulemode: allowable modulemodes |
369 | * @context_lost_counter: Count of module level context lost |
370 | * |
371 | * If @lostcontext_mask is not defined, context loss check code uses |
372 | * whole register without masking. @lostcontext_mask should only be |
373 | * defined in cases where @context_offs register is shared by two or |
374 | * more hwmods. |
375 | */ |
376 | struct omap_hwmod_omap4_prcm { |
377 | u16 clkctrl_offs; |
378 | u16 rstctrl_offs; |
379 | u16 rstst_offs; |
380 | u16 context_offs; |
381 | u32 lostcontext_mask; |
382 | u8 submodule_wkdep_bit; |
383 | u8 modulemode; |
384 | u8 flags; |
385 | int context_lost_counter; |
386 | }; |
387 | |
388 | |
389 | /* |
390 | * omap_hwmod.flags definitions |
391 | * |
392 | * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out |
393 | * of idle, rather than relying on module smart-idle |
394 | * HWMOD_SWSUP_MSTANDBY: omap_hwmod code should manually bring module in and |
395 | * out of standby, rather than relying on module smart-standby |
396 | * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for |
397 | * SDRAM controller, etc. XXX probably belongs outside the main hwmod file |
398 | * XXX Should be HWMOD_SETUP_NO_RESET |
399 | * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM |
400 | * controller, etc. XXX probably belongs outside the main hwmod file |
401 | * XXX Should be HWMOD_SETUP_NO_IDLE |
402 | * HWMOD_NO_OCP_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE) |
403 | * when module is enabled, rather than the default, which is to |
404 | * enable autoidle |
405 | * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup |
406 | * HWMOD_NO_IDLEST: this module does not have idle status - this is the case |
407 | * only for few initiator modules on OMAP2 & 3. |
408 | * HWMOD_CONTROL_OPT_CLKS_IN_RESET: Enable all optional clocks during reset. |
409 | * This is needed for devices like DSS that require optional clocks enabled |
410 | * in order to complete the reset. Optional clocks will be disabled |
411 | * again after the reset. |
412 | * HWMOD_16BIT_REG: Module has 16bit registers |
413 | * HWMOD_EXT_OPT_MAIN_CLK: The only main functional clock source for |
414 | * this IP block comes from an off-chip source and is not always |
415 | * enabled. This prevents the hwmod code from being able to |
416 | * enable and reset the IP block early. XXX Eventually it should |
417 | * be possible to query the clock framework for this information. |
418 | * HWMOD_BLOCK_WFI: Some OMAP peripherals apparently don't work |
419 | * correctly if the MPU is allowed to go idle while the |
420 | * peripherals are active. This is apparently true for the I2C on |
421 | * OMAP2420, and also the EMAC on AM3517/3505. It's unlikely that |
422 | * this is really true -- we're probably not configuring something |
423 | * correctly, or this is being abused to deal with some PM latency |
424 | * issues -- but we're currently suffering from a shortage of |
425 | * folks who are able to track these issues down properly. |
426 | * HWMOD_FORCE_MSTANDBY: Always keep MIDLEMODE bits cleared so that device |
427 | * is kept in force-standby mode. Failing to do so causes PM problems |
428 | * with musb on OMAP3630 at least. Note that musb has a dedicated register |
429 | * to control MSTANDBY signal when MIDLEMODE is set to force-standby. |
430 | * HWMOD_SWSUP_SIDLE_ACT: omap_hwmod code should manually bring the module |
431 | * out of idle, but rely on smart-idle to the put it back in idle, |
432 | * so the wakeups are still functional (Only known case for now is UART) |
433 | * HWMOD_RECONFIG_IO_CHAIN: omap_hwmod code needs to reconfigure wake-up |
434 | * events by calling _reconfigure_io_chain() when a device is enabled |
435 | * or idled. |
436 | * HWMOD_OPT_CLKS_NEEDED: The optional clocks are needed for the module to |
437 | * operate and they need to be handled at the same time as the main_clk. |
438 | * HWMOD_NO_IDLE: Do not idle the hwmod at all. Useful to handle certain |
439 | * IPs like CPSW on DRA7, where clocks to this module cannot be disabled. |
440 | * HWMOD_CLKDM_NOAUTO: Allows the hwmod's clockdomain to be prevented from |
441 | * entering HW_AUTO while hwmod is active. This is needed to workaround |
442 | * some modules which don't function correctly with HW_AUTO. For example, |
443 | * DCAN on DRA7x SoC needs this to workaround errata i893. |
444 | */ |
445 | #define HWMOD_SWSUP_SIDLE (1 << 0) |
446 | #define HWMOD_SWSUP_MSTANDBY (1 << 1) |
447 | #define HWMOD_INIT_NO_RESET (1 << 2) |
448 | #define HWMOD_INIT_NO_IDLE (1 << 3) |
449 | #define HWMOD_NO_OCP_AUTOIDLE (1 << 4) |
450 | #define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5) |
451 | #define HWMOD_NO_IDLEST (1 << 6) |
452 | #define HWMOD_CONTROL_OPT_CLKS_IN_RESET (1 << 7) |
453 | #define HWMOD_16BIT_REG (1 << 8) |
454 | #define HWMOD_EXT_OPT_MAIN_CLK (1 << 9) |
455 | #define HWMOD_BLOCK_WFI (1 << 10) |
456 | #define HWMOD_FORCE_MSTANDBY (1 << 11) |
457 | #define HWMOD_SWSUP_SIDLE_ACT (1 << 12) |
458 | #define HWMOD_RECONFIG_IO_CHAIN (1 << 13) |
459 | #define HWMOD_OPT_CLKS_NEEDED (1 << 14) |
460 | #define HWMOD_NO_IDLE (1 << 15) |
461 | #define HWMOD_CLKDM_NOAUTO (1 << 16) |
462 | |
463 | /* |
464 | * omap_hwmod._int_flags definitions |
465 | * These are for internal use only and are managed by the omap_hwmod code. |
466 | * |
467 | * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module |
468 | * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached |
469 | * _HWMOD_SKIP_ENABLE: set if hwmod enabled during init (HWMOD_INIT_NO_IDLE) - |
470 | * causes the first call to _enable() to only update the pinmux |
471 | */ |
472 | #define _HWMOD_NO_MPU_PORT (1 << 0) |
473 | #define _HWMOD_SYSCONFIG_LOADED (1 << 1) |
474 | #define _HWMOD_SKIP_ENABLE (1 << 2) |
475 | |
476 | /* |
477 | * omap_hwmod._state definitions |
478 | * |
479 | * INITIALIZED: reset (optionally), initialized, enabled, disabled |
480 | * (optionally) |
481 | * |
482 | * |
483 | */ |
484 | #define _HWMOD_STATE_UNKNOWN 0 |
485 | #define _HWMOD_STATE_REGISTERED 1 |
486 | #define _HWMOD_STATE_CLKS_INITED 2 |
487 | #define _HWMOD_STATE_INITIALIZED 3 |
488 | #define _HWMOD_STATE_ENABLED 4 |
489 | #define _HWMOD_STATE_IDLE 5 |
490 | #define _HWMOD_STATE_DISABLED 6 |
491 | |
492 | #ifdef CONFIG_PM |
493 | #define _HWMOD_STATE_DEFAULT _HWMOD_STATE_IDLE |
494 | #else |
495 | #define _HWMOD_STATE_DEFAULT _HWMOD_STATE_ENABLED |
496 | #endif |
497 | |
498 | /** |
499 | * struct omap_hwmod_class - the type of an IP block |
500 | * @name: name of the hwmod_class |
501 | * @sysc: device SYSCONFIG/SYSSTATUS register data |
502 | * @pre_shutdown: ptr to fn to be executed immediately prior to device shutdown |
503 | * @reset: ptr to fn to be executed in place of the standard hwmod reset fn |
504 | * @lock: ptr to fn to be executed to lock IP registers |
505 | * @unlock: ptr to fn to be executed to unlock IP registers |
506 | * |
507 | * Represent the class of a OMAP hardware "modules" (e.g. timer, |
508 | * smartreflex, gpio, uart...) |
509 | * |
510 | * @pre_shutdown is a function that will be run immediately before |
511 | * hwmod clocks are disabled, etc. It is intended for use for hwmods |
512 | * like the MPU watchdog, which cannot be disabled with the standard |
513 | * omap_hwmod_shutdown(). The function should return 0 upon success, |
514 | * or some negative error upon failure. Returning an error will cause |
515 | * omap_hwmod_shutdown() to abort the device shutdown and return an |
516 | * error. |
517 | * |
518 | * If @reset is defined, then the function it points to will be |
519 | * executed in place of the standard hwmod _reset() code in |
520 | * mach-omap2/omap_hwmod.c. This is needed for IP blocks which have |
521 | * unusual reset sequences - usually processor IP blocks like the IVA. |
522 | */ |
523 | struct omap_hwmod_class { |
524 | const char *name; |
525 | struct omap_hwmod_class_sysconfig *sysc; |
526 | int (*pre_shutdown)(struct omap_hwmod *oh); |
527 | int (*reset)(struct omap_hwmod *oh); |
528 | void (*lock)(struct omap_hwmod *oh); |
529 | void (*unlock)(struct omap_hwmod *oh); |
530 | }; |
531 | |
532 | /** |
533 | * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks) |
534 | * @name: name of the hwmod |
535 | * @class: struct omap_hwmod_class * to the class of this hwmod |
536 | * @od: struct omap_device currently associated with this hwmod (internal use) |
537 | * @prcm: PRCM data pertaining to this hwmod |
538 | * @main_clk: main clock: OMAP clock name |
539 | * @_clk: pointer to the main struct clk (filled in at runtime) |
540 | * @opt_clks: other device clocks that drivers can request (0..*) |
541 | * @voltdm: pointer to voltage domain (filled in at runtime) |
542 | * @dev_attr: arbitrary device attributes that can be passed to the driver |
543 | * @_sysc_cache: internal-use hwmod flags |
544 | * @mpu_rt_idx: index of device address space for register target (for DT boot) |
545 | * @_mpu_rt_va: cached register target start address (internal use) |
546 | * @_mpu_port: cached MPU register target slave (internal use) |
547 | * @opt_clks_cnt: number of @opt_clks |
548 | * @master_cnt: number of @master entries |
549 | * @slaves_cnt: number of @slave entries |
550 | * @response_lat: device OCP response latency (in interface clock cycles) |
551 | * @_int_flags: internal-use hwmod flags |
552 | * @_state: internal-use hwmod state |
553 | * @_postsetup_state: internal-use state to leave the hwmod in after _setup() |
554 | * @flags: hwmod flags (documented below) |
555 | * @_lock: spinlock serializing operations on this hwmod |
556 | * @node: list node for hwmod list (internal use) |
557 | * @parent_hwmod: (temporary) a pointer to the hierarchical parent of this hwmod |
558 | * |
559 | * @main_clk refers to this module's "main clock," which for our |
560 | * purposes is defined as "the functional clock needed for register |
561 | * accesses to complete." Modules may not have a main clock if the |
562 | * interface clock also serves as a main clock. |
563 | * |
564 | * Parameter names beginning with an underscore are managed internally by |
565 | * the omap_hwmod code and should not be set during initialization. |
566 | * |
567 | * @masters and @slaves are now deprecated. |
568 | * |
569 | * @parent_hwmod is temporary; there should be no need for it, as this |
570 | * information should already be expressed in the OCP interface |
571 | * structures. @parent_hwmod is present as a workaround until we improve |
572 | * handling for hwmods with multiple parents (e.g., OMAP4+ DSS with |
573 | * multiple register targets across different interconnects). |
574 | */ |
575 | struct omap_hwmod { |
576 | const char *name; |
577 | struct omap_hwmod_class *class; |
578 | struct omap_device *od; |
579 | struct omap_hwmod_rst_info *rst_lines; |
580 | union { |
581 | struct omap_hwmod_omap2_prcm omap2; |
582 | struct omap_hwmod_omap4_prcm omap4; |
583 | } prcm; |
584 | const char *main_clk; |
585 | struct clk *_clk; |
586 | struct omap_hwmod_opt_clk *opt_clks; |
587 | const char *clkdm_name; |
588 | struct clockdomain *clkdm; |
589 | struct list_head slave_ports; /* connect to *_TA */ |
590 | void *dev_attr; |
591 | u32 _sysc_cache; |
592 | void __iomem *_mpu_rt_va; |
593 | spinlock_t _lock; |
594 | struct lock_class_key hwmod_key; /* unique lock class */ |
595 | struct list_head node; |
596 | struct omap_hwmod_ocp_if *_mpu_port; |
597 | u32 flags; |
598 | u8 mpu_rt_idx; |
599 | u8 response_lat; |
600 | u8 rst_lines_cnt; |
601 | u8 opt_clks_cnt; |
602 | u8 slaves_cnt; |
603 | u8 hwmods_cnt; |
604 | u8 _int_flags; |
605 | u8 _state; |
606 | u8 _postsetup_state; |
607 | struct omap_hwmod *parent_hwmod; |
608 | }; |
609 | |
610 | #ifdef CONFIG_OMAP_HWMOD |
611 | |
612 | struct device_node; |
613 | |
614 | struct omap_hwmod *omap_hwmod_lookup(const char *name); |
615 | int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), |
616 | void *data); |
617 | |
618 | int omap_hwmod_parse_module_range(struct omap_hwmod *oh, |
619 | struct device_node *np, |
620 | struct resource *res); |
621 | |
622 | struct ti_sysc_module_data; |
623 | struct ti_sysc_cookie; |
624 | |
625 | int omap_hwmod_init_module(struct device *dev, |
626 | const struct ti_sysc_module_data *data, |
627 | struct ti_sysc_cookie *cookie); |
628 | |
629 | int omap_hwmod_enable(struct omap_hwmod *oh); |
630 | int omap_hwmod_idle(struct omap_hwmod *oh); |
631 | int omap_hwmod_shutdown(struct omap_hwmod *oh); |
632 | |
633 | int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name); |
634 | int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name); |
635 | |
636 | void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs); |
637 | u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs); |
638 | int omap_hwmod_softreset(struct omap_hwmod *oh); |
639 | |
640 | void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh); |
641 | |
642 | int omap_hwmod_for_each_by_class(const char *classname, |
643 | int (*fn)(struct omap_hwmod *oh, |
644 | void *user), |
645 | void *user); |
646 | |
647 | int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state); |
648 | |
649 | extern void __init omap_hwmod_init(void); |
650 | |
651 | #else /* CONFIG_OMAP_HWMOD */ |
652 | |
653 | static inline int |
654 | omap_hwmod_for_each_by_class(const char *classname, |
655 | int (*fn)(struct omap_hwmod *oh, void *user), |
656 | void *user) |
657 | { |
658 | return 0; |
659 | } |
660 | #endif /* CONFIG_OMAP_HWMOD */ |
661 | |
662 | /* |
663 | * Chip variant-specific hwmod init routines - XXX should be converted |
664 | * to use initcalls once the initial boot ordering is straightened out |
665 | */ |
666 | extern int omap2420_hwmod_init(void); |
667 | extern int omap2430_hwmod_init(void); |
668 | extern int omap3xxx_hwmod_init(void); |
669 | extern int dm814x_hwmod_init(void); |
670 | extern int dm816x_hwmod_init(void); |
671 | |
672 | extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois); |
673 | |
674 | #endif |
675 | |