1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3 |
4 | * |
5 | * Copyright (C) 2011 Nokia Corporation |
6 | * Copyright (C) 2012 Texas Instruments, Inc. |
7 | * Paul Walmsley |
8 | */ |
9 | |
10 | #include <linux/dmaengine.h> |
11 | #include <linux/omap-dma.h> |
12 | |
13 | #include "omap_hwmod.h" |
14 | #include "hdq1w.h" |
15 | |
16 | #include "omap_hwmod_common_data.h" |
17 | |
18 | /* UART */ |
19 | |
20 | static struct omap_hwmod_class_sysconfig omap2_uart_sysc = { |
21 | .rev_offs = 0x50, |
22 | .sysc_offs = 0x54, |
23 | .syss_offs = 0x58, |
24 | .sysc_flags = (SYSC_HAS_SIDLEMODE | |
25 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
26 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), |
27 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
28 | .sysc_fields = &omap_hwmod_sysc_type1, |
29 | }; |
30 | |
31 | struct omap_hwmod_class omap2_uart_class = { |
32 | .name = "uart" , |
33 | .sysc = &omap2_uart_sysc, |
34 | }; |
35 | |
36 | /* |
37 | * 'venc' class |
38 | * video encoder |
39 | */ |
40 | |
41 | struct omap_hwmod_class omap2_venc_hwmod_class = { |
42 | .name = "venc" , |
43 | }; |
44 | |
45 | /* |
46 | * omap_hwmod class data |
47 | */ |
48 | |
49 | struct omap_hwmod_class l3_hwmod_class = { |
50 | .name = "l3" , |
51 | }; |
52 | |
53 | struct omap_hwmod_class l4_hwmod_class = { |
54 | .name = "l4" , |
55 | }; |
56 | |
57 | struct omap_hwmod_class mpu_hwmod_class = { |
58 | .name = "mpu" , |
59 | }; |
60 | |
61 | struct omap_hwmod_class iva_hwmod_class = { |
62 | .name = "iva" , |
63 | }; |
64 | |
65 | static struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = { |
66 | .rev_offs = 0x0, |
67 | .sysc_offs = 0x14, |
68 | .syss_offs = 0x18, |
69 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | |
70 | SYSS_HAS_RESET_STATUS), |
71 | .sysc_fields = &omap_hwmod_sysc_type1, |
72 | }; |
73 | |
74 | struct omap_hwmod_class omap2_hdq1w_class = { |
75 | .name = "hdq1w" , |
76 | .sysc = &omap2_hdq1w_sysc, |
77 | .reset = &omap_hdq1w_reset, |
78 | }; |
79 | |