1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * DM81xx hwmod data. |
4 | * |
5 | * Copyright (C) 2010 Texas Instruments, Inc. - https://www.ti.com/ |
6 | * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/ |
7 | */ |
8 | |
9 | #include <linux/types.h> |
10 | |
11 | #include <linux/platform_data/hsmmc-omap.h> |
12 | |
13 | #include "omap_hwmod_common_data.h" |
14 | #include "cm81xx.h" |
15 | #include "ti81xx.h" |
16 | #include "wd_timer.h" |
17 | |
18 | /* |
19 | * DM816X hardware modules integration data |
20 | * |
21 | * Note: This is incomplete and at present, not generated from h/w database. |
22 | */ |
23 | |
24 | /* |
25 | * Common alwon .clkctrl_offs from dm814x TRM "Table 2-278. CM_ALWON REGISTERS" |
26 | * also dm816x TRM 18.7.17 CM_ALWON device register values minus 0x1400. |
27 | */ |
28 | #define DM81XX_CM_ALWON_MCASP0_CLKCTRL 0x140 |
29 | #define DM81XX_CM_ALWON_MCASP1_CLKCTRL 0x144 |
30 | #define DM81XX_CM_ALWON_MCASP2_CLKCTRL 0x148 |
31 | #define DM81XX_CM_ALWON_MCBSP_CLKCTRL 0x14c |
32 | #define DM81XX_CM_ALWON_UART_0_CLKCTRL 0x150 |
33 | #define DM81XX_CM_ALWON_UART_1_CLKCTRL 0x154 |
34 | #define DM81XX_CM_ALWON_UART_2_CLKCTRL 0x158 |
35 | #define DM81XX_CM_ALWON_GPIO_0_CLKCTRL 0x15c |
36 | #define DM81XX_CM_ALWON_GPIO_1_CLKCTRL 0x160 |
37 | #define DM81XX_CM_ALWON_I2C_0_CLKCTRL 0x164 |
38 | #define DM81XX_CM_ALWON_I2C_1_CLKCTRL 0x168 |
39 | #define DM81XX_CM_ALWON_WDTIMER_CLKCTRL 0x18c |
40 | #define DM81XX_CM_ALWON_SPI_CLKCTRL 0x190 |
41 | #define DM81XX_CM_ALWON_MAILBOX_CLKCTRL 0x194 |
42 | #define DM81XX_CM_ALWON_SPINBOX_CLKCTRL 0x198 |
43 | #define DM81XX_CM_ALWON_MMUDATA_CLKCTRL 0x19c |
44 | #define DM81XX_CM_ALWON_MMUCFG_CLKCTRL 0x1a8 |
45 | #define DM81XX_CM_ALWON_CONTROL_CLKCTRL 0x1c4 |
46 | #define DM81XX_CM_ALWON_GPMC_CLKCTRL 0x1d0 |
47 | #define DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL 0x1d4 |
48 | #define DM81XX_CM_ALWON_L3_CLKCTRL 0x1e4 |
49 | #define DM81XX_CM_ALWON_L4HS_CLKCTRL 0x1e8 |
50 | #define DM81XX_CM_ALWON_L4LS_CLKCTRL 0x1ec |
51 | #define DM81XX_CM_ALWON_RTC_CLKCTRL 0x1f0 |
52 | #define DM81XX_CM_ALWON_TPCC_CLKCTRL 0x1f4 |
53 | #define DM81XX_CM_ALWON_TPTC0_CLKCTRL 0x1f8 |
54 | #define DM81XX_CM_ALWON_TPTC1_CLKCTRL 0x1fc |
55 | #define DM81XX_CM_ALWON_TPTC2_CLKCTRL 0x200 |
56 | #define DM81XX_CM_ALWON_TPTC3_CLKCTRL 0x204 |
57 | |
58 | /* Registers specific to dm814x */ |
59 | #define DM814X_CM_ALWON_MCASP_3_4_5_CLKCTRL 0x16c |
60 | #define DM814X_CM_ALWON_ATL_CLKCTRL 0x170 |
61 | #define DM814X_CM_ALWON_MLB_CLKCTRL 0x174 |
62 | #define DM814X_CM_ALWON_PATA_CLKCTRL 0x178 |
63 | #define DM814X_CM_ALWON_UART_3_CLKCTRL 0x180 |
64 | #define DM814X_CM_ALWON_UART_4_CLKCTRL 0x184 |
65 | #define DM814X_CM_ALWON_UART_5_CLKCTRL 0x188 |
66 | #define DM814X_CM_ALWON_OCM_0_CLKCTRL 0x1b4 |
67 | #define DM814X_CM_ALWON_VCP_CLKCTRL 0x1b8 |
68 | #define DM814X_CM_ALWON_MPU_CLKCTRL 0x1dc |
69 | #define DM814X_CM_ALWON_DEBUGSS_CLKCTRL 0x1e0 |
70 | #define DM814X_CM_ALWON_DCAN_0_1_CLKCTRL 0x218 |
71 | #define DM814X_CM_ALWON_MMCHS_0_CLKCTRL 0x21c |
72 | #define DM814X_CM_ALWON_MMCHS_1_CLKCTRL 0x220 |
73 | #define DM814X_CM_ALWON_MMCHS_2_CLKCTRL 0x224 |
74 | #define DM814X_CM_ALWON_CUST_EFUSE_CLKCTRL 0x228 |
75 | |
76 | /* Registers specific to dm816x */ |
77 | #define DM816X_DM_ALWON_BASE 0x1400 |
78 | #define DM816X_CM_ALWON_TIMER_1_CLKCTRL (0x1570 - DM816X_DM_ALWON_BASE) |
79 | #define DM816X_CM_ALWON_TIMER_2_CLKCTRL (0x1574 - DM816X_DM_ALWON_BASE) |
80 | #define DM816X_CM_ALWON_TIMER_3_CLKCTRL (0x1578 - DM816X_DM_ALWON_BASE) |
81 | #define DM816X_CM_ALWON_TIMER_4_CLKCTRL (0x157c - DM816X_DM_ALWON_BASE) |
82 | #define DM816X_CM_ALWON_TIMER_5_CLKCTRL (0x1580 - DM816X_DM_ALWON_BASE) |
83 | #define DM816X_CM_ALWON_TIMER_6_CLKCTRL (0x1584 - DM816X_DM_ALWON_BASE) |
84 | #define DM816X_CM_ALWON_TIMER_7_CLKCTRL (0x1588 - DM816X_DM_ALWON_BASE) |
85 | #define DM816X_CM_ALWON_SDIO_CLKCTRL (0x15b0 - DM816X_DM_ALWON_BASE) |
86 | #define DM816X_CM_ALWON_OCMC_0_CLKCTRL (0x15b4 - DM816X_DM_ALWON_BASE) |
87 | #define DM816X_CM_ALWON_OCMC_1_CLKCTRL (0x15b8 - DM816X_DM_ALWON_BASE) |
88 | #define DM816X_CM_ALWON_ETHERNET_1_CLKCTRL (0x15d8 - DM816X_DM_ALWON_BASE) |
89 | #define DM816X_CM_ALWON_MPU_CLKCTRL (0x15dc - DM816X_DM_ALWON_BASE) |
90 | #define DM816X_CM_ALWON_SR_0_CLKCTRL (0x1608 - DM816X_DM_ALWON_BASE) |
91 | #define DM816X_CM_ALWON_SR_1_CLKCTRL (0x160c - DM816X_DM_ALWON_BASE) |
92 | |
93 | /* |
94 | * The default .clkctrl_offs field is offset from CM_DEFAULT, that's |
95 | * TRM 18.7.6 CM_DEFAULT device register values minus 0x500 |
96 | */ |
97 | #define DM81XX_CM_DEFAULT_OFFSET 0x500 |
98 | #define DM81XX_CM_DEFAULT_USB_CLKCTRL (0x558 - DM81XX_CM_DEFAULT_OFFSET) |
99 | #define DM81XX_CM_DEFAULT_SATA_CLKCTRL (0x560 - DM81XX_CM_DEFAULT_OFFSET) |
100 | |
101 | /* L3 Interconnect entries clocked at 125, 250 and 500MHz */ |
102 | static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = { |
103 | .name = "alwon_l3_slow" , |
104 | .clkdm_name = "alwon_l3s_clkdm" , |
105 | .class = &l3_hwmod_class, |
106 | .flags = HWMOD_NO_IDLEST, |
107 | }; |
108 | |
109 | static struct omap_hwmod dm81xx_default_l3_slow_hwmod = { |
110 | .name = "default_l3_slow" , |
111 | .clkdm_name = "default_l3_slow_clkdm" , |
112 | .class = &l3_hwmod_class, |
113 | .flags = HWMOD_NO_IDLEST, |
114 | }; |
115 | |
116 | static struct omap_hwmod dm81xx_alwon_l3_med_hwmod = { |
117 | .name = "l3_med" , |
118 | .clkdm_name = "alwon_l3_med_clkdm" , |
119 | .class = &l3_hwmod_class, |
120 | .flags = HWMOD_NO_IDLEST, |
121 | }; |
122 | |
123 | /* |
124 | * L4 standard peripherals, see TRM table 1-12 for devices using this. |
125 | * See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock. |
126 | */ |
127 | static struct omap_hwmod dm81xx_l4_ls_hwmod = { |
128 | .name = "l4_ls" , |
129 | .clkdm_name = "alwon_l3s_clkdm" , |
130 | .class = &l4_hwmod_class, |
131 | .flags = HWMOD_NO_IDLEST, |
132 | }; |
133 | |
134 | /* |
135 | * L4 high-speed peripherals. For devices using this, please see the TRM |
136 | * table 1-13. On dm816x, only EMAC, MDIO and SATA use this. See also TRM |
137 | * table 1-73 for devices using 250MHz SYSCLK5 clock. |
138 | */ |
139 | static struct omap_hwmod dm81xx_l4_hs_hwmod = { |
140 | .name = "l4_hs" , |
141 | .clkdm_name = "alwon_l3_med_clkdm" , |
142 | .class = &l4_hwmod_class, |
143 | .flags = HWMOD_NO_IDLEST, |
144 | }; |
145 | |
146 | /* L3 slow -> L4 ls peripheral interface running at 125MHz */ |
147 | static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_ls = { |
148 | .master = &dm81xx_alwon_l3_slow_hwmod, |
149 | .slave = &dm81xx_l4_ls_hwmod, |
150 | .user = OCP_USER_MPU, |
151 | }; |
152 | |
153 | /* L3 med -> L4 fast peripheral interface running at 250MHz */ |
154 | static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_hs = { |
155 | .master = &dm81xx_alwon_l3_med_hwmod, |
156 | .slave = &dm81xx_l4_hs_hwmod, |
157 | .user = OCP_USER_MPU, |
158 | }; |
159 | |
160 | /* MPU */ |
161 | static struct omap_hwmod dm814x_mpu_hwmod = { |
162 | .name = "mpu" , |
163 | .clkdm_name = "alwon_l3s_clkdm" , |
164 | .class = &mpu_hwmod_class, |
165 | .flags = HWMOD_INIT_NO_IDLE, |
166 | .main_clk = "mpu_ck" , |
167 | .prcm = { |
168 | .omap4 = { |
169 | .clkctrl_offs = DM814X_CM_ALWON_MPU_CLKCTRL, |
170 | .modulemode = MODULEMODE_SWCTRL, |
171 | }, |
172 | }, |
173 | }; |
174 | |
175 | static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_slow = { |
176 | .master = &dm814x_mpu_hwmod, |
177 | .slave = &dm81xx_alwon_l3_slow_hwmod, |
178 | .user = OCP_USER_MPU, |
179 | }; |
180 | |
181 | /* L3 med peripheral interface running at 200MHz */ |
182 | static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_med = { |
183 | .master = &dm814x_mpu_hwmod, |
184 | .slave = &dm81xx_alwon_l3_med_hwmod, |
185 | .user = OCP_USER_MPU, |
186 | }; |
187 | |
188 | static struct omap_hwmod dm816x_mpu_hwmod = { |
189 | .name = "mpu" , |
190 | .clkdm_name = "alwon_mpu_clkdm" , |
191 | .class = &mpu_hwmod_class, |
192 | .flags = HWMOD_INIT_NO_IDLE, |
193 | .main_clk = "mpu_ck" , |
194 | .prcm = { |
195 | .omap4 = { |
196 | .clkctrl_offs = DM816X_CM_ALWON_MPU_CLKCTRL, |
197 | .modulemode = MODULEMODE_SWCTRL, |
198 | }, |
199 | }, |
200 | }; |
201 | |
202 | static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_slow = { |
203 | .master = &dm816x_mpu_hwmod, |
204 | .slave = &dm81xx_alwon_l3_slow_hwmod, |
205 | .user = OCP_USER_MPU, |
206 | }; |
207 | |
208 | /* L3 med peripheral interface running at 250MHz */ |
209 | static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_med = { |
210 | .master = &dm816x_mpu_hwmod, |
211 | .slave = &dm81xx_alwon_l3_med_hwmod, |
212 | .user = OCP_USER_MPU, |
213 | }; |
214 | |
215 | /* RTC */ |
216 | static struct omap_hwmod_class_sysconfig ti81xx_rtc_sysc = { |
217 | .rev_offs = 0x74, |
218 | .sysc_offs = 0x78, |
219 | .sysc_flags = SYSC_HAS_SIDLEMODE, |
220 | .idlemodes = SIDLE_FORCE | SIDLE_NO | |
221 | SIDLE_SMART | SIDLE_SMART_WKUP, |
222 | .sysc_fields = &omap_hwmod_sysc_type3, |
223 | }; |
224 | |
225 | static struct omap_hwmod_class ti81xx_rtc_hwmod_class = { |
226 | .name = "rtc" , |
227 | .sysc = &ti81xx_rtc_sysc, |
228 | }; |
229 | |
230 | static struct omap_hwmod ti81xx_rtc_hwmod = { |
231 | .name = "rtc" , |
232 | .class = &ti81xx_rtc_hwmod_class, |
233 | .clkdm_name = "alwon_l3s_clkdm" , |
234 | .flags = HWMOD_NO_IDLEST, |
235 | .main_clk = "sysclk18_ck" , |
236 | .prcm = { |
237 | .omap4 = { |
238 | .clkctrl_offs = DM81XX_CM_ALWON_RTC_CLKCTRL, |
239 | .modulemode = MODULEMODE_SWCTRL, |
240 | }, |
241 | }, |
242 | }; |
243 | |
244 | static struct omap_hwmod_ocp_if ti81xx_l4_ls__rtc = { |
245 | .master = &dm81xx_l4_ls_hwmod, |
246 | .slave = &ti81xx_rtc_hwmod, |
247 | .clk = "sysclk6_ck" , |
248 | .user = OCP_USER_MPU, |
249 | }; |
250 | |
251 | /* UART common */ |
252 | static struct omap_hwmod_class_sysconfig uart_sysc = { |
253 | .rev_offs = 0x50, |
254 | .sysc_offs = 0x54, |
255 | .syss_offs = 0x58, |
256 | .sysc_flags = SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | |
257 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | |
258 | SYSS_HAS_RESET_STATUS, |
259 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
260 | MSTANDBY_SMART_WKUP, |
261 | .sysc_fields = &omap_hwmod_sysc_type1, |
262 | }; |
263 | |
264 | static struct omap_hwmod_class uart_class = { |
265 | .name = "uart" , |
266 | .sysc = &uart_sysc, |
267 | }; |
268 | |
269 | static struct omap_hwmod dm81xx_uart1_hwmod = { |
270 | .name = "uart1" , |
271 | .clkdm_name = "alwon_l3s_clkdm" , |
272 | .main_clk = "sysclk10_ck" , |
273 | .prcm = { |
274 | .omap4 = { |
275 | .clkctrl_offs = DM81XX_CM_ALWON_UART_0_CLKCTRL, |
276 | .modulemode = MODULEMODE_SWCTRL, |
277 | }, |
278 | }, |
279 | .class = &uart_class, |
280 | .flags = DEBUG_TI81XXUART1_FLAGS, |
281 | }; |
282 | |
283 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart1 = { |
284 | .master = &dm81xx_l4_ls_hwmod, |
285 | .slave = &dm81xx_uart1_hwmod, |
286 | .clk = "sysclk6_ck" , |
287 | .user = OCP_USER_MPU, |
288 | }; |
289 | |
290 | static struct omap_hwmod dm81xx_uart2_hwmod = { |
291 | .name = "uart2" , |
292 | .clkdm_name = "alwon_l3s_clkdm" , |
293 | .main_clk = "sysclk10_ck" , |
294 | .prcm = { |
295 | .omap4 = { |
296 | .clkctrl_offs = DM81XX_CM_ALWON_UART_1_CLKCTRL, |
297 | .modulemode = MODULEMODE_SWCTRL, |
298 | }, |
299 | }, |
300 | .class = &uart_class, |
301 | .flags = DEBUG_TI81XXUART2_FLAGS, |
302 | }; |
303 | |
304 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart2 = { |
305 | .master = &dm81xx_l4_ls_hwmod, |
306 | .slave = &dm81xx_uart2_hwmod, |
307 | .clk = "sysclk6_ck" , |
308 | .user = OCP_USER_MPU, |
309 | }; |
310 | |
311 | static struct omap_hwmod dm81xx_uart3_hwmod = { |
312 | .name = "uart3" , |
313 | .clkdm_name = "alwon_l3s_clkdm" , |
314 | .main_clk = "sysclk10_ck" , |
315 | .prcm = { |
316 | .omap4 = { |
317 | .clkctrl_offs = DM81XX_CM_ALWON_UART_2_CLKCTRL, |
318 | .modulemode = MODULEMODE_SWCTRL, |
319 | }, |
320 | }, |
321 | .class = &uart_class, |
322 | .flags = DEBUG_TI81XXUART3_FLAGS, |
323 | }; |
324 | |
325 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart3 = { |
326 | .master = &dm81xx_l4_ls_hwmod, |
327 | .slave = &dm81xx_uart3_hwmod, |
328 | .clk = "sysclk6_ck" , |
329 | .user = OCP_USER_MPU, |
330 | }; |
331 | |
332 | static struct omap_hwmod_class_sysconfig wd_timer_sysc = { |
333 | .rev_offs = 0x0, |
334 | .sysc_offs = 0x10, |
335 | .syss_offs = 0x14, |
336 | .sysc_flags = SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | |
337 | SYSS_HAS_RESET_STATUS, |
338 | .sysc_fields = &omap_hwmod_sysc_type1, |
339 | }; |
340 | |
341 | static struct omap_hwmod_class wd_timer_class = { |
342 | .name = "wd_timer" , |
343 | .sysc = &wd_timer_sysc, |
344 | .pre_shutdown = &omap2_wd_timer_disable, |
345 | .reset = &omap2_wd_timer_reset, |
346 | }; |
347 | |
348 | static struct omap_hwmod dm81xx_wd_timer_hwmod = { |
349 | .name = "wd_timer" , |
350 | .clkdm_name = "alwon_l3s_clkdm" , |
351 | .main_clk = "sysclk18_ck" , |
352 | .flags = HWMOD_NO_IDLEST, |
353 | .prcm = { |
354 | .omap4 = { |
355 | .clkctrl_offs = DM81XX_CM_ALWON_WDTIMER_CLKCTRL, |
356 | .modulemode = MODULEMODE_SWCTRL, |
357 | }, |
358 | }, |
359 | .class = &wd_timer_class, |
360 | }; |
361 | |
362 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__wd_timer1 = { |
363 | .master = &dm81xx_l4_ls_hwmod, |
364 | .slave = &dm81xx_wd_timer_hwmod, |
365 | .clk = "sysclk6_ck" , |
366 | .user = OCP_USER_MPU, |
367 | }; |
368 | |
369 | /* I2C common */ |
370 | static struct omap_hwmod_class_sysconfig i2c_sysc = { |
371 | .rev_offs = 0x0, |
372 | .sysc_offs = 0x10, |
373 | .syss_offs = 0x90, |
374 | .sysc_flags = SYSC_HAS_SIDLEMODE | |
375 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
376 | SYSC_HAS_AUTOIDLE, |
377 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, |
378 | .sysc_fields = &omap_hwmod_sysc_type1, |
379 | }; |
380 | |
381 | static struct omap_hwmod_class i2c_class = { |
382 | .name = "i2c" , |
383 | .sysc = &i2c_sysc, |
384 | }; |
385 | |
386 | static struct omap_hwmod dm81xx_i2c1_hwmod = { |
387 | .name = "i2c1" , |
388 | .clkdm_name = "alwon_l3s_clkdm" , |
389 | .main_clk = "sysclk10_ck" , |
390 | .prcm = { |
391 | .omap4 = { |
392 | .clkctrl_offs = DM81XX_CM_ALWON_I2C_0_CLKCTRL, |
393 | .modulemode = MODULEMODE_SWCTRL, |
394 | }, |
395 | }, |
396 | .class = &i2c_class, |
397 | }; |
398 | |
399 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c1 = { |
400 | .master = &dm81xx_l4_ls_hwmod, |
401 | .slave = &dm81xx_i2c1_hwmod, |
402 | .clk = "sysclk6_ck" , |
403 | .user = OCP_USER_MPU, |
404 | }; |
405 | |
406 | static struct omap_hwmod dm81xx_i2c2_hwmod = { |
407 | .name = "i2c2" , |
408 | .clkdm_name = "alwon_l3s_clkdm" , |
409 | .main_clk = "sysclk10_ck" , |
410 | .prcm = { |
411 | .omap4 = { |
412 | .clkctrl_offs = DM81XX_CM_ALWON_I2C_1_CLKCTRL, |
413 | .modulemode = MODULEMODE_SWCTRL, |
414 | }, |
415 | }, |
416 | .class = &i2c_class, |
417 | }; |
418 | |
419 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = { |
420 | .master = &dm81xx_l4_ls_hwmod, |
421 | .slave = &dm81xx_i2c2_hwmod, |
422 | .clk = "sysclk6_ck" , |
423 | .user = OCP_USER_MPU, |
424 | }; |
425 | |
426 | static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = { |
427 | .rev_offs = 0x0000, |
428 | .sysc_offs = 0x0010, |
429 | .syss_offs = 0x0014, |
430 | .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | |
431 | SYSC_HAS_SOFTRESET | |
432 | SYSS_HAS_RESET_STATUS, |
433 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, |
434 | .sysc_fields = &omap_hwmod_sysc_type1, |
435 | }; |
436 | |
437 | static struct omap_hwmod_class dm81xx_elm_hwmod_class = { |
438 | .name = "elm" , |
439 | .sysc = &dm81xx_elm_sysc, |
440 | }; |
441 | |
442 | static struct omap_hwmod dm81xx_elm_hwmod = { |
443 | .name = "elm" , |
444 | .clkdm_name = "alwon_l3s_clkdm" , |
445 | .class = &dm81xx_elm_hwmod_class, |
446 | .main_clk = "sysclk6_ck" , |
447 | }; |
448 | |
449 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__elm = { |
450 | .master = &dm81xx_l4_ls_hwmod, |
451 | .slave = &dm81xx_elm_hwmod, |
452 | .clk = "sysclk6_ck" , |
453 | .user = OCP_USER_MPU, |
454 | }; |
455 | |
456 | static struct omap_hwmod_class_sysconfig dm81xx_gpio_sysc = { |
457 | .rev_offs = 0x0000, |
458 | .sysc_offs = 0x0010, |
459 | .syss_offs = 0x0114, |
460 | .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | |
461 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
462 | SYSS_HAS_RESET_STATUS, |
463 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
464 | SIDLE_SMART_WKUP, |
465 | .sysc_fields = &omap_hwmod_sysc_type1, |
466 | }; |
467 | |
468 | static struct omap_hwmod_class dm81xx_gpio_hwmod_class = { |
469 | .name = "gpio" , |
470 | .sysc = &dm81xx_gpio_sysc, |
471 | }; |
472 | |
473 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { |
474 | { .role = "dbclk" , .clk = "sysclk18_ck" }, |
475 | }; |
476 | |
477 | static struct omap_hwmod dm81xx_gpio1_hwmod = { |
478 | .name = "gpio1" , |
479 | .clkdm_name = "alwon_l3s_clkdm" , |
480 | .class = &dm81xx_gpio_hwmod_class, |
481 | .main_clk = "sysclk6_ck" , |
482 | .prcm = { |
483 | .omap4 = { |
484 | .clkctrl_offs = DM81XX_CM_ALWON_GPIO_0_CLKCTRL, |
485 | .modulemode = MODULEMODE_SWCTRL, |
486 | }, |
487 | }, |
488 | .opt_clks = gpio1_opt_clks, |
489 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), |
490 | }; |
491 | |
492 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1 = { |
493 | .master = &dm81xx_l4_ls_hwmod, |
494 | .slave = &dm81xx_gpio1_hwmod, |
495 | .clk = "sysclk6_ck" , |
496 | .user = OCP_USER_MPU, |
497 | }; |
498 | |
499 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { |
500 | { .role = "dbclk" , .clk = "sysclk18_ck" }, |
501 | }; |
502 | |
503 | static struct omap_hwmod dm81xx_gpio2_hwmod = { |
504 | .name = "gpio2" , |
505 | .clkdm_name = "alwon_l3s_clkdm" , |
506 | .class = &dm81xx_gpio_hwmod_class, |
507 | .main_clk = "sysclk6_ck" , |
508 | .prcm = { |
509 | .omap4 = { |
510 | .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL, |
511 | .modulemode = MODULEMODE_SWCTRL, |
512 | }, |
513 | }, |
514 | .opt_clks = gpio2_opt_clks, |
515 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), |
516 | }; |
517 | |
518 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = { |
519 | .master = &dm81xx_l4_ls_hwmod, |
520 | .slave = &dm81xx_gpio2_hwmod, |
521 | .clk = "sysclk6_ck" , |
522 | .user = OCP_USER_MPU, |
523 | }; |
524 | |
525 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { |
526 | { .role = "dbclk" , .clk = "sysclk18_ck" }, |
527 | }; |
528 | |
529 | static struct omap_hwmod dm81xx_gpio3_hwmod = { |
530 | .name = "gpio3" , |
531 | .clkdm_name = "alwon_l3s_clkdm" , |
532 | .class = &dm81xx_gpio_hwmod_class, |
533 | .main_clk = "sysclk6_ck" , |
534 | .prcm = { |
535 | .omap4 = { |
536 | .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL, |
537 | .modulemode = MODULEMODE_SWCTRL, |
538 | }, |
539 | }, |
540 | .opt_clks = gpio3_opt_clks, |
541 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), |
542 | }; |
543 | |
544 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio3 = { |
545 | .master = &dm81xx_l4_ls_hwmod, |
546 | .slave = &dm81xx_gpio3_hwmod, |
547 | .clk = "sysclk6_ck" , |
548 | .user = OCP_USER_MPU, |
549 | }; |
550 | |
551 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { |
552 | { .role = "dbclk" , .clk = "sysclk18_ck" }, |
553 | }; |
554 | |
555 | static struct omap_hwmod dm81xx_gpio4_hwmod = { |
556 | .name = "gpio4" , |
557 | .clkdm_name = "alwon_l3s_clkdm" , |
558 | .class = &dm81xx_gpio_hwmod_class, |
559 | .main_clk = "sysclk6_ck" , |
560 | .prcm = { |
561 | .omap4 = { |
562 | .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL, |
563 | .modulemode = MODULEMODE_SWCTRL, |
564 | }, |
565 | }, |
566 | .opt_clks = gpio4_opt_clks, |
567 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), |
568 | }; |
569 | |
570 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio4 = { |
571 | .master = &dm81xx_l4_ls_hwmod, |
572 | .slave = &dm81xx_gpio4_hwmod, |
573 | .clk = "sysclk6_ck" , |
574 | .user = OCP_USER_MPU, |
575 | }; |
576 | |
577 | static struct omap_hwmod_class_sysconfig dm81xx_gpmc_sysc = { |
578 | .rev_offs = 0x0, |
579 | .sysc_offs = 0x10, |
580 | .syss_offs = 0x14, |
581 | .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
582 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, |
583 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, |
584 | .sysc_fields = &omap_hwmod_sysc_type1, |
585 | }; |
586 | |
587 | static struct omap_hwmod_class dm81xx_gpmc_hwmod_class = { |
588 | .name = "gpmc" , |
589 | .sysc = &dm81xx_gpmc_sysc, |
590 | }; |
591 | |
592 | static struct omap_hwmod dm81xx_gpmc_hwmod = { |
593 | .name = "gpmc" , |
594 | .clkdm_name = "alwon_l3s_clkdm" , |
595 | .class = &dm81xx_gpmc_hwmod_class, |
596 | .main_clk = "sysclk6_ck" , |
597 | /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */ |
598 | .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS, |
599 | .prcm = { |
600 | .omap4 = { |
601 | .clkctrl_offs = DM81XX_CM_ALWON_GPMC_CLKCTRL, |
602 | .modulemode = MODULEMODE_SWCTRL, |
603 | }, |
604 | }, |
605 | }; |
606 | |
607 | static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc = { |
608 | .master = &dm81xx_alwon_l3_slow_hwmod, |
609 | .slave = &dm81xx_gpmc_hwmod, |
610 | .user = OCP_USER_MPU, |
611 | }; |
612 | |
613 | /* USB needs udelay 1 after reset at least on hp t410, use 2 for margin */ |
614 | static struct omap_hwmod_class_sysconfig dm81xx_usbhsotg_sysc = { |
615 | .rev_offs = 0x0, |
616 | .sysc_offs = 0x10, |
617 | .srst_udelay = 2, |
618 | .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | |
619 | SYSC_HAS_SOFTRESET, |
620 | .idlemodes = SIDLE_SMART | MSTANDBY_FORCE | MSTANDBY_SMART, |
621 | .sysc_fields = &omap_hwmod_sysc_type2, |
622 | }; |
623 | |
624 | static struct omap_hwmod_class dm81xx_usbotg_class = { |
625 | .name = "usbotg" , |
626 | .sysc = &dm81xx_usbhsotg_sysc, |
627 | }; |
628 | |
629 | static struct omap_hwmod dm814x_usbss_hwmod = { |
630 | .name = "usb_otg_hs" , |
631 | .clkdm_name = "default_l3_slow_clkdm" , |
632 | .main_clk = "pll260dcoclkldo" , /* 481c5260.adpll.dcoclkldo */ |
633 | .prcm = { |
634 | .omap4 = { |
635 | .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL, |
636 | .modulemode = MODULEMODE_SWCTRL, |
637 | }, |
638 | }, |
639 | .class = &dm81xx_usbotg_class, |
640 | }; |
641 | |
642 | static struct omap_hwmod_ocp_if dm814x_default_l3_slow__usbss = { |
643 | .master = &dm81xx_default_l3_slow_hwmod, |
644 | .slave = &dm814x_usbss_hwmod, |
645 | .clk = "sysclk6_ck" , |
646 | .user = OCP_USER_MPU, |
647 | }; |
648 | |
649 | static struct omap_hwmod dm816x_usbss_hwmod = { |
650 | .name = "usb_otg_hs" , |
651 | .clkdm_name = "default_l3_slow_clkdm" , |
652 | .main_clk = "sysclk6_ck" , |
653 | .prcm = { |
654 | .omap4 = { |
655 | .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL, |
656 | .modulemode = MODULEMODE_SWCTRL, |
657 | }, |
658 | }, |
659 | .class = &dm81xx_usbotg_class, |
660 | }; |
661 | |
662 | static struct omap_hwmod_ocp_if dm816x_default_l3_slow__usbss = { |
663 | .master = &dm81xx_default_l3_slow_hwmod, |
664 | .slave = &dm816x_usbss_hwmod, |
665 | .clk = "sysclk6_ck" , |
666 | .user = OCP_USER_MPU, |
667 | }; |
668 | |
669 | static struct omap_hwmod_class_sysconfig dm816x_timer_sysc = { |
670 | .rev_offs = 0x0000, |
671 | .sysc_offs = 0x0010, |
672 | .syss_offs = 0x0014, |
673 | .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET, |
674 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
675 | SIDLE_SMART_WKUP, |
676 | .sysc_fields = &omap_hwmod_sysc_type2, |
677 | }; |
678 | |
679 | static struct omap_hwmod_class dm816x_timer_hwmod_class = { |
680 | .name = "timer" , |
681 | .sysc = &dm816x_timer_sysc, |
682 | }; |
683 | |
684 | static struct omap_hwmod dm816x_timer3_hwmod = { |
685 | .name = "timer3" , |
686 | .clkdm_name = "alwon_l3s_clkdm" , |
687 | .main_clk = "timer3_fck" , |
688 | .prcm = { |
689 | .omap4 = { |
690 | .clkctrl_offs = DM816X_CM_ALWON_TIMER_3_CLKCTRL, |
691 | .modulemode = MODULEMODE_SWCTRL, |
692 | }, |
693 | }, |
694 | .class = &dm816x_timer_hwmod_class, |
695 | }; |
696 | |
697 | static struct omap_hwmod_ocp_if dm816x_l4_ls__timer3 = { |
698 | .master = &dm81xx_l4_ls_hwmod, |
699 | .slave = &dm816x_timer3_hwmod, |
700 | .clk = "sysclk6_ck" , |
701 | .user = OCP_USER_MPU, |
702 | }; |
703 | |
704 | static struct omap_hwmod dm816x_timer4_hwmod = { |
705 | .name = "timer4" , |
706 | .clkdm_name = "alwon_l3s_clkdm" , |
707 | .main_clk = "timer4_fck" , |
708 | .prcm = { |
709 | .omap4 = { |
710 | .clkctrl_offs = DM816X_CM_ALWON_TIMER_4_CLKCTRL, |
711 | .modulemode = MODULEMODE_SWCTRL, |
712 | }, |
713 | }, |
714 | .class = &dm816x_timer_hwmod_class, |
715 | }; |
716 | |
717 | static struct omap_hwmod_ocp_if dm816x_l4_ls__timer4 = { |
718 | .master = &dm81xx_l4_ls_hwmod, |
719 | .slave = &dm816x_timer4_hwmod, |
720 | .clk = "sysclk6_ck" , |
721 | .user = OCP_USER_MPU, |
722 | }; |
723 | |
724 | static struct omap_hwmod dm816x_timer5_hwmod = { |
725 | .name = "timer5" , |
726 | .clkdm_name = "alwon_l3s_clkdm" , |
727 | .main_clk = "timer5_fck" , |
728 | .prcm = { |
729 | .omap4 = { |
730 | .clkctrl_offs = DM816X_CM_ALWON_TIMER_5_CLKCTRL, |
731 | .modulemode = MODULEMODE_SWCTRL, |
732 | }, |
733 | }, |
734 | .class = &dm816x_timer_hwmod_class, |
735 | }; |
736 | |
737 | static struct omap_hwmod_ocp_if dm816x_l4_ls__timer5 = { |
738 | .master = &dm81xx_l4_ls_hwmod, |
739 | .slave = &dm816x_timer5_hwmod, |
740 | .clk = "sysclk6_ck" , |
741 | .user = OCP_USER_MPU, |
742 | }; |
743 | |
744 | static struct omap_hwmod dm816x_timer6_hwmod = { |
745 | .name = "timer6" , |
746 | .clkdm_name = "alwon_l3s_clkdm" , |
747 | .main_clk = "timer6_fck" , |
748 | .prcm = { |
749 | .omap4 = { |
750 | .clkctrl_offs = DM816X_CM_ALWON_TIMER_6_CLKCTRL, |
751 | .modulemode = MODULEMODE_SWCTRL, |
752 | }, |
753 | }, |
754 | .class = &dm816x_timer_hwmod_class, |
755 | }; |
756 | |
757 | static struct omap_hwmod_ocp_if dm816x_l4_ls__timer6 = { |
758 | .master = &dm81xx_l4_ls_hwmod, |
759 | .slave = &dm816x_timer6_hwmod, |
760 | .clk = "sysclk6_ck" , |
761 | .user = OCP_USER_MPU, |
762 | }; |
763 | |
764 | static struct omap_hwmod dm816x_timer7_hwmod = { |
765 | .name = "timer7" , |
766 | .clkdm_name = "alwon_l3s_clkdm" , |
767 | .main_clk = "timer7_fck" , |
768 | .prcm = { |
769 | .omap4 = { |
770 | .clkctrl_offs = DM816X_CM_ALWON_TIMER_7_CLKCTRL, |
771 | .modulemode = MODULEMODE_SWCTRL, |
772 | }, |
773 | }, |
774 | .class = &dm816x_timer_hwmod_class, |
775 | }; |
776 | |
777 | static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7 = { |
778 | .master = &dm81xx_l4_ls_hwmod, |
779 | .slave = &dm816x_timer7_hwmod, |
780 | .clk = "sysclk6_ck" , |
781 | .user = OCP_USER_MPU, |
782 | }; |
783 | |
784 | /* EMAC Ethernet */ |
785 | static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = { |
786 | .rev_offs = 0x0, |
787 | .sysc_offs = 0x4, |
788 | .sysc_flags = SYSC_HAS_SOFTRESET, |
789 | .sysc_fields = &omap_hwmod_sysc_type2, |
790 | }; |
791 | |
792 | static struct omap_hwmod_class dm816x_emac_hwmod_class = { |
793 | .name = "emac" , |
794 | .sysc = &dm816x_emac_sysc, |
795 | }; |
796 | |
797 | /* |
798 | * On dm816x the MDIO is within EMAC0. As the MDIO driver is a separate |
799 | * driver probed before EMAC0, we let MDIO do the clock idling. |
800 | */ |
801 | static struct omap_hwmod dm816x_emac0_hwmod = { |
802 | .name = "emac0" , |
803 | .clkdm_name = "alwon_ethernet_clkdm" , |
804 | .class = &dm816x_emac_hwmod_class, |
805 | .flags = HWMOD_NO_IDLEST, |
806 | }; |
807 | |
808 | static struct omap_hwmod_ocp_if dm81xx_l4_hs__emac0 = { |
809 | .master = &dm81xx_l4_hs_hwmod, |
810 | .slave = &dm816x_emac0_hwmod, |
811 | .clk = "sysclk5_ck" , |
812 | .user = OCP_USER_MPU, |
813 | }; |
814 | |
815 | static struct omap_hwmod_class dm81xx_mdio_hwmod_class = { |
816 | .name = "davinci_mdio" , |
817 | .sysc = &dm816x_emac_sysc, |
818 | }; |
819 | |
820 | static struct omap_hwmod dm81xx_emac0_mdio_hwmod = { |
821 | .name = "davinci_mdio" , |
822 | .class = &dm81xx_mdio_hwmod_class, |
823 | .clkdm_name = "alwon_ethernet_clkdm" , |
824 | .main_clk = "sysclk24_ck" , |
825 | .flags = HWMOD_NO_IDLEST, |
826 | /* |
827 | * REVISIT: This should be moved to the emac0_hwmod |
828 | * once we have a better way to handle device slaves. |
829 | */ |
830 | .prcm = { |
831 | .omap4 = { |
832 | .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL, |
833 | .modulemode = MODULEMODE_SWCTRL, |
834 | }, |
835 | }, |
836 | }; |
837 | |
838 | static struct omap_hwmod_ocp_if dm81xx_emac0__mdio = { |
839 | .master = &dm81xx_l4_hs_hwmod, |
840 | .slave = &dm81xx_emac0_mdio_hwmod, |
841 | .user = OCP_USER_MPU, |
842 | }; |
843 | |
844 | static struct omap_hwmod dm816x_emac1_hwmod = { |
845 | .name = "emac1" , |
846 | .clkdm_name = "alwon_ethernet_clkdm" , |
847 | .main_clk = "sysclk24_ck" , |
848 | .flags = HWMOD_NO_IDLEST, |
849 | .prcm = { |
850 | .omap4 = { |
851 | .clkctrl_offs = DM816X_CM_ALWON_ETHERNET_1_CLKCTRL, |
852 | .modulemode = MODULEMODE_SWCTRL, |
853 | }, |
854 | }, |
855 | .class = &dm816x_emac_hwmod_class, |
856 | }; |
857 | |
858 | static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = { |
859 | .master = &dm81xx_l4_hs_hwmod, |
860 | .slave = &dm816x_emac1_hwmod, |
861 | .clk = "sysclk5_ck" , |
862 | .user = OCP_USER_MPU, |
863 | }; |
864 | |
865 | static struct omap_hwmod_class_sysconfig dm81xx_sata_sysc = { |
866 | .rev_offs = 0x00fc, |
867 | .sysc_offs = 0x1100, |
868 | .sysc_flags = SYSC_HAS_SIDLEMODE, |
869 | .idlemodes = SIDLE_FORCE, |
870 | .sysc_fields = &omap_hwmod_sysc_type3, |
871 | }; |
872 | |
873 | static struct omap_hwmod_class dm81xx_sata_hwmod_class = { |
874 | .name = "sata" , |
875 | .sysc = &dm81xx_sata_sysc, |
876 | }; |
877 | |
878 | static struct omap_hwmod dm81xx_sata_hwmod = { |
879 | .name = "sata" , |
880 | .clkdm_name = "default_clkdm" , |
881 | .flags = HWMOD_NO_IDLEST, |
882 | .prcm = { |
883 | .omap4 = { |
884 | .clkctrl_offs = DM81XX_CM_DEFAULT_SATA_CLKCTRL, |
885 | .modulemode = MODULEMODE_SWCTRL, |
886 | }, |
887 | }, |
888 | .class = &dm81xx_sata_hwmod_class, |
889 | }; |
890 | |
891 | static struct omap_hwmod_ocp_if dm81xx_l4_hs__sata = { |
892 | .master = &dm81xx_l4_hs_hwmod, |
893 | .slave = &dm81xx_sata_hwmod, |
894 | .clk = "sysclk5_ck" , |
895 | .user = OCP_USER_MPU, |
896 | }; |
897 | |
898 | static struct omap_hwmod_class_sysconfig dm81xx_mmc_sysc = { |
899 | .rev_offs = 0x0, |
900 | .sysc_offs = 0x110, |
901 | .syss_offs = 0x114, |
902 | .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | |
903 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
904 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, |
905 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, |
906 | .sysc_fields = &omap_hwmod_sysc_type1, |
907 | }; |
908 | |
909 | static struct omap_hwmod_class dm81xx_mmc_class = { |
910 | .name = "mmc" , |
911 | .sysc = &dm81xx_mmc_sysc, |
912 | }; |
913 | |
914 | static struct omap_hwmod_opt_clk dm81xx_mmc_opt_clks[] = { |
915 | { .role = "dbck" , .clk = "sysclk18_ck" , }, |
916 | }; |
917 | |
918 | static struct omap_hsmmc_dev_attr mmc_dev_attr = { |
919 | }; |
920 | |
921 | static struct omap_hwmod dm814x_mmc1_hwmod = { |
922 | .name = "mmc1" , |
923 | .clkdm_name = "alwon_l3s_clkdm" , |
924 | .opt_clks = dm81xx_mmc_opt_clks, |
925 | .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks), |
926 | .main_clk = "sysclk8_ck" , |
927 | .prcm = { |
928 | .omap4 = { |
929 | .clkctrl_offs = DM814X_CM_ALWON_MMCHS_0_CLKCTRL, |
930 | .modulemode = MODULEMODE_SWCTRL, |
931 | }, |
932 | }, |
933 | .dev_attr = &mmc_dev_attr, |
934 | .class = &dm81xx_mmc_class, |
935 | }; |
936 | |
937 | static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc1 = { |
938 | .master = &dm81xx_l4_ls_hwmod, |
939 | .slave = &dm814x_mmc1_hwmod, |
940 | .clk = "sysclk6_ck" , |
941 | .user = OCP_USER_MPU, |
942 | .flags = OMAP_FIREWALL_L4 |
943 | }; |
944 | |
945 | static struct omap_hwmod dm814x_mmc2_hwmod = { |
946 | .name = "mmc2" , |
947 | .clkdm_name = "alwon_l3s_clkdm" , |
948 | .opt_clks = dm81xx_mmc_opt_clks, |
949 | .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks), |
950 | .main_clk = "sysclk8_ck" , |
951 | .prcm = { |
952 | .omap4 = { |
953 | .clkctrl_offs = DM814X_CM_ALWON_MMCHS_1_CLKCTRL, |
954 | .modulemode = MODULEMODE_SWCTRL, |
955 | }, |
956 | }, |
957 | .dev_attr = &mmc_dev_attr, |
958 | .class = &dm81xx_mmc_class, |
959 | }; |
960 | |
961 | static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc2 = { |
962 | .master = &dm81xx_l4_ls_hwmod, |
963 | .slave = &dm814x_mmc2_hwmod, |
964 | .clk = "sysclk6_ck" , |
965 | .user = OCP_USER_MPU, |
966 | .flags = OMAP_FIREWALL_L4 |
967 | }; |
968 | |
969 | static struct omap_hwmod dm814x_mmc3_hwmod = { |
970 | .name = "mmc3" , |
971 | .clkdm_name = "alwon_l3_med_clkdm" , |
972 | .opt_clks = dm81xx_mmc_opt_clks, |
973 | .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks), |
974 | .main_clk = "sysclk8_ck" , |
975 | .prcm = { |
976 | .omap4 = { |
977 | .clkctrl_offs = DM814X_CM_ALWON_MMCHS_2_CLKCTRL, |
978 | .modulemode = MODULEMODE_SWCTRL, |
979 | }, |
980 | }, |
981 | .dev_attr = &mmc_dev_attr, |
982 | .class = &dm81xx_mmc_class, |
983 | }; |
984 | |
985 | static struct omap_hwmod_ocp_if dm814x_alwon_l3_med__mmc3 = { |
986 | .master = &dm81xx_alwon_l3_med_hwmod, |
987 | .slave = &dm814x_mmc3_hwmod, |
988 | .clk = "sysclk4_ck" , |
989 | .user = OCP_USER_MPU, |
990 | }; |
991 | |
992 | static struct omap_hwmod dm816x_mmc1_hwmod = { |
993 | .name = "mmc1" , |
994 | .clkdm_name = "alwon_l3s_clkdm" , |
995 | .opt_clks = dm81xx_mmc_opt_clks, |
996 | .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks), |
997 | .main_clk = "sysclk10_ck" , |
998 | .prcm = { |
999 | .omap4 = { |
1000 | .clkctrl_offs = DM816X_CM_ALWON_SDIO_CLKCTRL, |
1001 | .modulemode = MODULEMODE_SWCTRL, |
1002 | }, |
1003 | }, |
1004 | .dev_attr = &mmc_dev_attr, |
1005 | .class = &dm81xx_mmc_class, |
1006 | }; |
1007 | |
1008 | static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1 = { |
1009 | .master = &dm81xx_l4_ls_hwmod, |
1010 | .slave = &dm816x_mmc1_hwmod, |
1011 | .clk = "sysclk6_ck" , |
1012 | .user = OCP_USER_MPU, |
1013 | .flags = OMAP_FIREWALL_L4 |
1014 | }; |
1015 | |
1016 | static struct omap_hwmod_class_sysconfig dm816x_mcspi_sysc = { |
1017 | .rev_offs = 0x0, |
1018 | .sysc_offs = 0x110, |
1019 | .syss_offs = 0x114, |
1020 | .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | |
1021 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
1022 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, |
1023 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, |
1024 | .sysc_fields = &omap_hwmod_sysc_type1, |
1025 | }; |
1026 | |
1027 | static struct omap_hwmod_class dm816x_mcspi_class = { |
1028 | .name = "mcspi" , |
1029 | .sysc = &dm816x_mcspi_sysc, |
1030 | }; |
1031 | |
1032 | static struct omap_hwmod dm81xx_mcspi1_hwmod = { |
1033 | .name = "mcspi1" , |
1034 | .clkdm_name = "alwon_l3s_clkdm" , |
1035 | .main_clk = "sysclk10_ck" , |
1036 | .prcm = { |
1037 | .omap4 = { |
1038 | .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL, |
1039 | .modulemode = MODULEMODE_SWCTRL, |
1040 | }, |
1041 | }, |
1042 | .class = &dm816x_mcspi_class, |
1043 | }; |
1044 | |
1045 | static struct omap_hwmod dm81xx_mcspi2_hwmod = { |
1046 | .name = "mcspi2" , |
1047 | .clkdm_name = "alwon_l3s_clkdm" , |
1048 | .main_clk = "sysclk10_ck" , |
1049 | .prcm = { |
1050 | .omap4 = { |
1051 | .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL, |
1052 | .modulemode = MODULEMODE_SWCTRL, |
1053 | }, |
1054 | }, |
1055 | .class = &dm816x_mcspi_class, |
1056 | }; |
1057 | |
1058 | static struct omap_hwmod dm81xx_mcspi3_hwmod = { |
1059 | .name = "mcspi3" , |
1060 | .clkdm_name = "alwon_l3s_clkdm" , |
1061 | .main_clk = "sysclk10_ck" , |
1062 | .prcm = { |
1063 | .omap4 = { |
1064 | .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL, |
1065 | .modulemode = MODULEMODE_SWCTRL, |
1066 | }, |
1067 | }, |
1068 | .class = &dm816x_mcspi_class, |
1069 | }; |
1070 | |
1071 | static struct omap_hwmod dm81xx_mcspi4_hwmod = { |
1072 | .name = "mcspi4" , |
1073 | .clkdm_name = "alwon_l3s_clkdm" , |
1074 | .main_clk = "sysclk10_ck" , |
1075 | .prcm = { |
1076 | .omap4 = { |
1077 | .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL, |
1078 | .modulemode = MODULEMODE_SWCTRL, |
1079 | }, |
1080 | }, |
1081 | .class = &dm816x_mcspi_class, |
1082 | }; |
1083 | |
1084 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = { |
1085 | .master = &dm81xx_l4_ls_hwmod, |
1086 | .slave = &dm81xx_mcspi1_hwmod, |
1087 | .clk = "sysclk6_ck" , |
1088 | .user = OCP_USER_MPU, |
1089 | }; |
1090 | |
1091 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi2 = { |
1092 | .master = &dm81xx_l4_ls_hwmod, |
1093 | .slave = &dm81xx_mcspi2_hwmod, |
1094 | .clk = "sysclk6_ck" , |
1095 | .user = OCP_USER_MPU, |
1096 | }; |
1097 | |
1098 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi3 = { |
1099 | .master = &dm81xx_l4_ls_hwmod, |
1100 | .slave = &dm81xx_mcspi3_hwmod, |
1101 | .clk = "sysclk6_ck" , |
1102 | .user = OCP_USER_MPU, |
1103 | }; |
1104 | |
1105 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi4 = { |
1106 | .master = &dm81xx_l4_ls_hwmod, |
1107 | .slave = &dm81xx_mcspi4_hwmod, |
1108 | .clk = "sysclk6_ck" , |
1109 | .user = OCP_USER_MPU, |
1110 | }; |
1111 | |
1112 | static struct omap_hwmod_class_sysconfig dm81xx_mailbox_sysc = { |
1113 | .rev_offs = 0x000, |
1114 | .sysc_offs = 0x010, |
1115 | .syss_offs = 0x014, |
1116 | .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | |
1117 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE, |
1118 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, |
1119 | .sysc_fields = &omap_hwmod_sysc_type1, |
1120 | }; |
1121 | |
1122 | static struct omap_hwmod_class dm81xx_mailbox_hwmod_class = { |
1123 | .name = "mailbox" , |
1124 | .sysc = &dm81xx_mailbox_sysc, |
1125 | }; |
1126 | |
1127 | static struct omap_hwmod dm81xx_mailbox_hwmod = { |
1128 | .name = "mailbox" , |
1129 | .clkdm_name = "alwon_l3s_clkdm" , |
1130 | .class = &dm81xx_mailbox_hwmod_class, |
1131 | .main_clk = "sysclk6_ck" , |
1132 | .prcm = { |
1133 | .omap4 = { |
1134 | .clkctrl_offs = DM81XX_CM_ALWON_MAILBOX_CLKCTRL, |
1135 | .modulemode = MODULEMODE_SWCTRL, |
1136 | }, |
1137 | }, |
1138 | }; |
1139 | |
1140 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__mailbox = { |
1141 | .master = &dm81xx_l4_ls_hwmod, |
1142 | .slave = &dm81xx_mailbox_hwmod, |
1143 | .clk = "sysclk6_ck" , |
1144 | .user = OCP_USER_MPU, |
1145 | }; |
1146 | |
1147 | static struct omap_hwmod_class_sysconfig dm81xx_spinbox_sysc = { |
1148 | .rev_offs = 0x000, |
1149 | .sysc_offs = 0x010, |
1150 | .syss_offs = 0x014, |
1151 | .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | |
1152 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE, |
1153 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, |
1154 | .sysc_fields = &omap_hwmod_sysc_type1, |
1155 | }; |
1156 | |
1157 | static struct omap_hwmod_class dm81xx_spinbox_hwmod_class = { |
1158 | .name = "spinbox" , |
1159 | .sysc = &dm81xx_spinbox_sysc, |
1160 | }; |
1161 | |
1162 | static struct omap_hwmod dm81xx_spinbox_hwmod = { |
1163 | .name = "spinbox" , |
1164 | .clkdm_name = "alwon_l3s_clkdm" , |
1165 | .class = &dm81xx_spinbox_hwmod_class, |
1166 | .main_clk = "sysclk6_ck" , |
1167 | .prcm = { |
1168 | .omap4 = { |
1169 | .clkctrl_offs = DM81XX_CM_ALWON_SPINBOX_CLKCTRL, |
1170 | .modulemode = MODULEMODE_SWCTRL, |
1171 | }, |
1172 | }, |
1173 | }; |
1174 | |
1175 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__spinbox = { |
1176 | .master = &dm81xx_l4_ls_hwmod, |
1177 | .slave = &dm81xx_spinbox_hwmod, |
1178 | .clk = "sysclk6_ck" , |
1179 | .user = OCP_USER_MPU, |
1180 | }; |
1181 | |
1182 | /* |
1183 | * REVISIT: Test and enable the following once clocks work: |
1184 | * dm81xx_l4_ls__mailbox |
1185 | * |
1186 | * Also note that some devices share a single clkctrl_offs.. |
1187 | * For example, i2c1 and 3 share one, and i2c2 and 4 share one. |
1188 | */ |
1189 | static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = { |
1190 | &dm814x_mpu__alwon_l3_slow, |
1191 | &dm814x_mpu__alwon_l3_med, |
1192 | &dm81xx_alwon_l3_slow__l4_ls, |
1193 | &dm81xx_alwon_l3_slow__l4_hs, |
1194 | &dm81xx_l4_ls__uart1, |
1195 | &dm81xx_l4_ls__uart2, |
1196 | &dm81xx_l4_ls__uart3, |
1197 | &dm81xx_l4_ls__wd_timer1, |
1198 | &dm81xx_l4_ls__i2c1, |
1199 | &dm81xx_l4_ls__i2c2, |
1200 | &dm81xx_l4_ls__gpio1, |
1201 | &dm81xx_l4_ls__gpio2, |
1202 | &dm81xx_l4_ls__gpio3, |
1203 | &dm81xx_l4_ls__gpio4, |
1204 | &dm81xx_l4_ls__elm, |
1205 | &dm81xx_l4_ls__mcspi1, |
1206 | &dm81xx_l4_ls__mcspi2, |
1207 | &dm81xx_l4_ls__mcspi3, |
1208 | &dm81xx_l4_ls__mcspi4, |
1209 | &dm814x_l4_ls__mmc1, |
1210 | &dm814x_l4_ls__mmc2, |
1211 | &ti81xx_l4_ls__rtc, |
1212 | &dm81xx_alwon_l3_slow__gpmc, |
1213 | &dm814x_default_l3_slow__usbss, |
1214 | &dm814x_alwon_l3_med__mmc3, |
1215 | NULL, |
1216 | }; |
1217 | |
1218 | int __init dm814x_hwmod_init(void) |
1219 | { |
1220 | omap_hwmod_init(); |
1221 | return omap_hwmod_register_links(ois: dm814x_hwmod_ocp_ifs); |
1222 | } |
1223 | |
1224 | static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = { |
1225 | &dm816x_mpu__alwon_l3_slow, |
1226 | &dm816x_mpu__alwon_l3_med, |
1227 | &dm81xx_alwon_l3_slow__l4_ls, |
1228 | &dm81xx_alwon_l3_slow__l4_hs, |
1229 | &dm81xx_l4_ls__uart1, |
1230 | &dm81xx_l4_ls__uart2, |
1231 | &dm81xx_l4_ls__uart3, |
1232 | &dm81xx_l4_ls__wd_timer1, |
1233 | &dm81xx_l4_ls__i2c1, |
1234 | &dm81xx_l4_ls__i2c2, |
1235 | &dm81xx_l4_ls__gpio1, |
1236 | &dm81xx_l4_ls__gpio2, |
1237 | &dm81xx_l4_ls__elm, |
1238 | &ti81xx_l4_ls__rtc, |
1239 | &dm816x_l4_ls__mmc1, |
1240 | &dm816x_l4_ls__timer3, |
1241 | &dm816x_l4_ls__timer4, |
1242 | &dm816x_l4_ls__timer5, |
1243 | &dm816x_l4_ls__timer6, |
1244 | &dm816x_l4_ls__timer7, |
1245 | &dm81xx_l4_ls__mcspi1, |
1246 | &dm81xx_l4_ls__mailbox, |
1247 | &dm81xx_l4_ls__spinbox, |
1248 | &dm81xx_l4_hs__emac0, |
1249 | &dm81xx_emac0__mdio, |
1250 | &dm816x_l4_hs__emac1, |
1251 | &dm81xx_l4_hs__sata, |
1252 | &dm81xx_alwon_l3_slow__gpmc, |
1253 | &dm816x_default_l3_slow__usbss, |
1254 | NULL, |
1255 | }; |
1256 | |
1257 | int __init dm816x_hwmod_init(void) |
1258 | { |
1259 | omap_hwmod_init(); |
1260 | return omap_hwmod_register_links(ois: dm816x_hwmod_ocp_ifs); |
1261 | } |
1262 | |