| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * opp2xxx.h - macros for old-style OMAP2xxx "OPP" definitions |
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| 4 | * |
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| 5 | * Copyright (C) 2005-2009 Texas Instruments, Inc. |
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| 6 | * Copyright (C) 2004-2009 Nokia Corporation |
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| 7 | * |
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| 8 | * Richard Woodruff <r-woodruff2@ti.com> |
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| 9 | * |
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| 10 | * The OMAP2 processor can be run at several discrete 'PRCM configurations'. |
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| 11 | * These configurations are characterized by voltage and speed for clocks. |
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| 12 | * The device is only validated for certain combinations. One way to express |
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| 13 | * these combinations is via the 'ratio's' which the clocks operate with |
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| 14 | * respect to each other. These ratio sets are for a given voltage/DPLL |
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| 15 | * setting. All configurations can be described by a DPLL setting and a ratio |
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| 16 | * There are 3 ratio sets for the 2430 and X ratio sets for 2420. |
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| 17 | * |
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| 18 | * 2430 differs from 2420 in that there are no more phase synchronizers used. |
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| 19 | * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs |
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| 20 | * 2430 (iva2.1, NOdsp, mdm) |
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| 21 | * |
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| 22 | * XXX Missing voltage data. |
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| 23 | * |
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| 24 | * THe format described in this file is deprecated. Once a reasonable |
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| 25 | * OPP API exists, the data in this file should be converted to use it. |
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| 26 | * |
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| 27 | * This is technically part of the OMAP2xxx clock code. |
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| 28 | */ |
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| 29 | |
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| 30 | #ifndef __ARCH_ARM_MACH_OMAP2_OPP2XXX_H |
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| 31 | #define __ARCH_ARM_MACH_OMAP2_OPP2XXX_H |
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| 32 | |
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| 33 | /** |
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| 34 | * struct prcm_config - define clock rates on a per-OPP basis (24xx) |
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| 35 | * |
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| 36 | * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. |
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| 37 | * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP |
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| 38 | * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM |
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| 39 | * |
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| 40 | * This is deprecated. As soon as we have a decent OPP API, we should |
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| 41 | * move all this stuff to it. |
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| 42 | */ |
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| 43 | struct prcm_config { |
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| 44 | unsigned long xtal_speed; /* crystal rate */ |
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| 45 | unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */ |
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| 46 | unsigned long mpu_speed; /* speed of MPU */ |
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| 47 | unsigned long cm_clksel_mpu; /* mpu divider */ |
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| 48 | unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */ |
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| 49 | unsigned long cm_clksel_gfx; /* gfx dividers */ |
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| 50 | unsigned long cm_clksel1_core; /* major subsystem dividers */ |
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| 51 | unsigned long cm_clksel1_pll; /* m,n */ |
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| 52 | unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */ |
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| 53 | unsigned long cm_clksel_mdm; /* modem dividers 2430 only */ |
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| 54 | unsigned long base_sdrc_rfr; /* base refresh timing for a set */ |
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| 55 | unsigned short flags; |
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| 56 | }; |
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| 57 | |
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| 58 | |
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| 59 | /* Core fields for cm_clksel, not ratio governed */ |
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| 60 | #define RX_CLKSEL_DSS1 (0x10 << 8) |
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| 61 | #define RX_CLKSEL_DSS2 (0x0 << 13) |
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| 62 | #define RX_CLKSEL_SSI (0x5 << 20) |
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| 63 | |
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| 64 | /*------------------------------------------------------------------------- |
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| 65 | * Voltage/DPLL ratios |
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| 66 | *-------------------------------------------------------------------------*/ |
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| 67 | |
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| 68 | /* 2430 Ratio's, 2430-Ratio Config 1 */ |
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| 69 | #define R1_CLKSEL_L3 (4 << 0) |
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| 70 | #define R1_CLKSEL_L4 (2 << 5) |
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| 71 | #define R1_CLKSEL_USB (4 << 25) |
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| 72 | #define R1_CM_CLKSEL1_CORE_VAL (R1_CLKSEL_USB | RX_CLKSEL_SSI | \ |
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| 73 | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ |
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| 74 | R1_CLKSEL_L4 | R1_CLKSEL_L3) |
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| 75 | #define R1_CLKSEL_MPU (2 << 0) |
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| 76 | #define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU |
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| 77 | #define R1_CLKSEL_DSP (2 << 0) |
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| 78 | #define R1_CLKSEL_DSP_IF (2 << 5) |
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| 79 | #define R1_CM_CLKSEL_DSP_VAL (R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF) |
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| 80 | #define R1_CLKSEL_GFX (2 << 0) |
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| 81 | #define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX |
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| 82 | #define R1_CLKSEL_MDM (4 << 0) |
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| 83 | #define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM |
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| 84 | |
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| 85 | /* 2430-Ratio Config 2 */ |
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| 86 | #define R2_CLKSEL_L3 (6 << 0) |
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| 87 | #define R2_CLKSEL_L4 (2 << 5) |
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| 88 | #define R2_CLKSEL_USB (2 << 25) |
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| 89 | #define R2_CM_CLKSEL1_CORE_VAL (R2_CLKSEL_USB | RX_CLKSEL_SSI | \ |
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| 90 | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ |
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| 91 | R2_CLKSEL_L4 | R2_CLKSEL_L3) |
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| 92 | #define R2_CLKSEL_MPU (2 << 0) |
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| 93 | #define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU |
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| 94 | #define R2_CLKSEL_DSP (2 << 0) |
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| 95 | #define R2_CLKSEL_DSP_IF (3 << 5) |
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| 96 | #define R2_CM_CLKSEL_DSP_VAL (R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF) |
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| 97 | #define R2_CLKSEL_GFX (2 << 0) |
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| 98 | #define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX |
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| 99 | #define R2_CLKSEL_MDM (6 << 0) |
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| 100 | #define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM |
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| 101 | |
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| 102 | /* 2430-Ratio Bootm (BYPASS) */ |
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| 103 | #define RB_CLKSEL_L3 (1 << 0) |
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| 104 | #define RB_CLKSEL_L4 (1 << 5) |
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| 105 | #define RB_CLKSEL_USB (1 << 25) |
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| 106 | #define RB_CM_CLKSEL1_CORE_VAL (RB_CLKSEL_USB | RX_CLKSEL_SSI | \ |
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| 107 | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ |
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| 108 | RB_CLKSEL_L4 | RB_CLKSEL_L3) |
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| 109 | #define RB_CLKSEL_MPU (1 << 0) |
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| 110 | #define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU |
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| 111 | #define RB_CLKSEL_DSP (1 << 0) |
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| 112 | #define RB_CLKSEL_DSP_IF (1 << 5) |
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| 113 | #define RB_CM_CLKSEL_DSP_VAL (RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF) |
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| 114 | #define RB_CLKSEL_GFX (1 << 0) |
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| 115 | #define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX |
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| 116 | #define RB_CLKSEL_MDM (1 << 0) |
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| 117 | #define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM |
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| 118 | |
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| 119 | /* 2420 Ratio Equivalents */ |
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| 120 | #define RXX_CLKSEL_VLYNQ (0x12 << 15) |
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| 121 | #define RXX_CLKSEL_SSI (0x8 << 20) |
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| 122 | |
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| 123 | /* 2420-PRCM III 532MHz core */ |
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| 124 | #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */ |
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| 125 | #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */ |
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| 126 | #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */ |
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| 127 | #define RIII_CM_CLKSEL1_CORE_VAL (RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \ |
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| 128 | RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \ |
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| 129 | RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \ |
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| 130 | RIII_CLKSEL_L3) |
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| 131 | #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */ |
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| 132 | #define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU |
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| 133 | #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */ |
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| 134 | #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */ |
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| 135 | #define RIII_SYNC_DSP (1 << 7) /* Enable sync */ |
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| 136 | #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */ |
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| 137 | #define RIII_SYNC_IVA (1 << 13) /* Enable sync */ |
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| 138 | #define RIII_CM_CLKSEL_DSP_VAL (RIII_SYNC_IVA | RIII_CLKSEL_IVA | \ |
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| 139 | RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \ |
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| 140 | RIII_CLKSEL_DSP) |
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| 141 | #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */ |
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| 142 | #define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX |
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| 143 | |
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| 144 | /* 2420-PRCM II 600MHz core */ |
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| 145 | #define RII_CLKSEL_L3 (6 << 0) /* 100MHz */ |
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| 146 | #define RII_CLKSEL_L4 (2 << 5) /* 50MHz */ |
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| 147 | #define RII_CLKSEL_USB (2 << 25) /* 50MHz */ |
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| 148 | #define RII_CM_CLKSEL1_CORE_VAL (RII_CLKSEL_USB | RXX_CLKSEL_SSI | \ |
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| 149 | RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \ |
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| 150 | RX_CLKSEL_DSS1 | RII_CLKSEL_L4 | \ |
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| 151 | RII_CLKSEL_L3) |
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| 152 | #define RII_CLKSEL_MPU (2 << 0) /* 300MHz */ |
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| 153 | #define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU |
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| 154 | #define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */ |
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| 155 | #define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */ |
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| 156 | #define RII_SYNC_DSP (0 << 7) /* Bypass sync */ |
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| 157 | #define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */ |
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| 158 | #define RII_SYNC_IVA (0 << 13) /* Bypass sync */ |
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| 159 | #define RII_CM_CLKSEL_DSP_VAL (RII_SYNC_IVA | RII_CLKSEL_IVA | \ |
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| 160 | RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \ |
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| 161 | RII_CLKSEL_DSP) |
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| 162 | #define RII_CLKSEL_GFX (2 << 0) /* 50MHz */ |
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| 163 | #define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX |
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| 164 | |
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| 165 | /* 2420-PRCM I 660MHz core */ |
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| 166 | #define RI_CLKSEL_L3 (4 << 0) /* 165MHz */ |
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| 167 | #define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */ |
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| 168 | #define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */ |
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| 169 | #define RI_CM_CLKSEL1_CORE_VAL (RI_CLKSEL_USB | \ |
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| 170 | RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \ |
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| 171 | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ |
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| 172 | RI_CLKSEL_L4 | RI_CLKSEL_L3) |
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| 173 | #define RI_CLKSEL_MPU (2 << 0) /* 330MHz */ |
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| 174 | #define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU |
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| 175 | #define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */ |
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| 176 | #define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */ |
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| 177 | #define RI_SYNC_DSP (1 << 7) /* Activate sync */ |
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| 178 | #define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */ |
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| 179 | #define RI_SYNC_IVA (0 << 13) /* Bypass sync */ |
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| 180 | #define RI_CM_CLKSEL_DSP_VAL (RI_SYNC_IVA | RI_CLKSEL_IVA | \ |
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| 181 | RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \ |
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| 182 | RI_CLKSEL_DSP) |
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| 183 | #define RI_CLKSEL_GFX (1 << 0) /* 165MHz */ |
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| 184 | #define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX |
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| 185 | |
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| 186 | /* 2420-PRCM VII (boot) */ |
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| 187 | #define RVII_CLKSEL_L3 (1 << 0) |
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| 188 | #define RVII_CLKSEL_L4 (1 << 5) |
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| 189 | #define RVII_CLKSEL_DSS1 (1 << 8) |
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| 190 | #define RVII_CLKSEL_DSS2 (0 << 13) |
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| 191 | #define RVII_CLKSEL_VLYNQ (1 << 15) |
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| 192 | #define RVII_CLKSEL_SSI (1 << 20) |
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| 193 | #define RVII_CLKSEL_USB (1 << 25) |
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| 194 | |
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| 195 | #define RVII_CM_CLKSEL1_CORE_VAL (RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \ |
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| 196 | RVII_CLKSEL_VLYNQ | \ |
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| 197 | RVII_CLKSEL_DSS2 | RVII_CLKSEL_DSS1 | \ |
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| 198 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3) |
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| 199 | |
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| 200 | #define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */ |
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| 201 | #define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU |
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| 202 | |
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| 203 | #define RVII_CLKSEL_DSP (1 << 0) |
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| 204 | #define RVII_CLKSEL_DSP_IF (1 << 5) |
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| 205 | #define RVII_SYNC_DSP (0 << 7) |
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| 206 | #define RVII_CLKSEL_IVA (1 << 8) |
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| 207 | #define RVII_SYNC_IVA (0 << 13) |
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| 208 | #define RVII_CM_CLKSEL_DSP_VAL (RVII_SYNC_IVA | RVII_CLKSEL_IVA | \ |
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| 209 | RVII_SYNC_DSP | RVII_CLKSEL_DSP_IF | \ |
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| 210 | RVII_CLKSEL_DSP) |
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| 211 | |
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| 212 | #define RVII_CLKSEL_GFX (1 << 0) |
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| 213 | #define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX |
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| 214 | |
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| 215 | /*------------------------------------------------------------------------- |
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| 216 | * 2430 Target modes: Along with each configuration the CPU has several |
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| 217 | * modes which goes along with them. Modes mainly are the addition of |
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| 218 | * describe DPLL combinations to go along with a ratio. |
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| 219 | *-------------------------------------------------------------------------*/ |
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| 220 | |
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| 221 | /* Hardware governed */ |
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| 222 | #define MX_48M_SRC (0 << 3) |
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| 223 | #define MX_54M_SRC (0 << 5) |
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| 224 | #define MX_APLLS_CLIKIN_12 (3 << 23) |
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| 225 | #define MX_APLLS_CLIKIN_13 (2 << 23) |
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| 226 | #define MX_APLLS_CLIKIN_19_2 (0 << 23) |
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| 227 | |
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| 228 | /* |
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| 229 | * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed |
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| 230 | * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz |
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| 231 | */ |
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| 232 | #define M5A_DPLL_MULT_12 (133 << 12) |
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| 233 | #define M5A_DPLL_DIV_12 (5 << 8) |
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| 234 | #define M5A_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ |
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| 235 | M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \ |
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| 236 | MX_APLLS_CLIKIN_12) |
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| 237 | #define M5A_DPLL_MULT_13 (61 << 12) |
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| 238 | #define M5A_DPLL_DIV_13 (2 << 8) |
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| 239 | #define M5A_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ |
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| 240 | M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \ |
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| 241 | MX_APLLS_CLIKIN_13) |
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| 242 | #define M5A_DPLL_MULT_19 (55 << 12) |
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| 243 | #define M5A_DPLL_DIV_19 (3 << 8) |
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| 244 | #define M5A_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ |
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| 245 | M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \ |
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| 246 | MX_APLLS_CLIKIN_19_2) |
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| 247 | /* #5b (ratio1) target DPLL = 200*2 = 400MHz */ |
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| 248 | #define M5B_DPLL_MULT_12 (50 << 12) |
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| 249 | #define M5B_DPLL_DIV_12 (2 << 8) |
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| 250 | #define M5B_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ |
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| 251 | M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \ |
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| 252 | MX_APLLS_CLIKIN_12) |
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| 253 | #define M5B_DPLL_MULT_13 (200 << 12) |
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| 254 | #define M5B_DPLL_DIV_13 (12 << 8) |
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| 255 | |
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| 256 | #define M5B_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ |
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| 257 | M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \ |
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| 258 | MX_APLLS_CLIKIN_13) |
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| 259 | #define M5B_DPLL_MULT_19 (125 << 12) |
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| 260 | #define M5B_DPLL_DIV_19 (31 << 8) |
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| 261 | #define M5B_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ |
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| 262 | M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \ |
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| 263 | MX_APLLS_CLIKIN_19_2) |
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| 264 | /* |
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| 265 | * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz |
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| 266 | */ |
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| 267 | #define M4_DPLL_MULT_12 (133 << 12) |
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| 268 | #define M4_DPLL_DIV_12 (3 << 8) |
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| 269 | #define M4_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ |
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| 270 | M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \ |
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| 271 | MX_APLLS_CLIKIN_12) |
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| 272 | |
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| 273 | #define M4_DPLL_MULT_13 (399 << 12) |
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| 274 | #define M4_DPLL_DIV_13 (12 << 8) |
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| 275 | #define M4_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ |
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| 276 | M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \ |
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| 277 | MX_APLLS_CLIKIN_13) |
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| 278 | |
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| 279 | #define M4_DPLL_MULT_19 (145 << 12) |
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| 280 | #define M4_DPLL_DIV_19 (6 << 8) |
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| 281 | #define M4_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ |
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| 282 | M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \ |
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| 283 | MX_APLLS_CLIKIN_19_2) |
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| 284 | |
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| 285 | /* |
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| 286 | * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz |
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| 287 | */ |
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| 288 | #define M3_DPLL_MULT_12 (55 << 12) |
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| 289 | #define M3_DPLL_DIV_12 (1 << 8) |
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| 290 | #define M3_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ |
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| 291 | M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \ |
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| 292 | MX_APLLS_CLIKIN_12) |
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| 293 | #define M3_DPLL_MULT_13 (76 << 12) |
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| 294 | #define M3_DPLL_DIV_13 (2 << 8) |
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| 295 | #define M3_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ |
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| 296 | M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \ |
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| 297 | MX_APLLS_CLIKIN_13) |
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| 298 | #define M3_DPLL_MULT_19 (17 << 12) |
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| 299 | #define M3_DPLL_DIV_19 (0 << 8) |
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| 300 | #define M3_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ |
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| 301 | M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \ |
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| 302 | MX_APLLS_CLIKIN_19_2) |
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| 303 | |
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| 304 | /* |
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| 305 | * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz |
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| 306 | */ |
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| 307 | #define M2_DPLL_MULT_12 (55 << 12) |
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| 308 | #define M2_DPLL_DIV_12 (1 << 8) |
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| 309 | #define M2_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ |
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| 310 | M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \ |
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| 311 | MX_APLLS_CLIKIN_12) |
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| 312 | |
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| 313 | /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2, |
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| 314 | * relock time issue */ |
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| 315 | /* Core frequency changed from 330/165 to 329/164 MHz*/ |
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| 316 | #define M2_DPLL_MULT_13 (76 << 12) |
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| 317 | #define M2_DPLL_DIV_13 (2 << 8) |
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| 318 | #define M2_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ |
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| 319 | M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \ |
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| 320 | MX_APLLS_CLIKIN_13) |
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| 321 | |
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| 322 | #define M2_DPLL_MULT_19 (17 << 12) |
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| 323 | #define M2_DPLL_DIV_19 (0 << 8) |
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| 324 | #define M2_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ |
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| 325 | M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \ |
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| 326 | MX_APLLS_CLIKIN_19_2) |
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| 327 | |
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| 328 | /* boot (boot) */ |
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| 329 | #define MB_DPLL_MULT (1 << 12) |
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| 330 | #define MB_DPLL_DIV (0 << 8) |
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| 331 | #define MB_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ |
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| 332 | MB_DPLL_DIV | MB_DPLL_MULT | \ |
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| 333 | MX_APLLS_CLIKIN_12) |
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| 334 | |
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| 335 | #define MB_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ |
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| 336 | MB_DPLL_DIV | MB_DPLL_MULT | \ |
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| 337 | MX_APLLS_CLIKIN_13) |
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| 338 | |
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| 339 | #define MB_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ |
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| 340 | MB_DPLL_DIV | MB_DPLL_MULT | \ |
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| 341 | MX_APLLS_CLIKIN_19) |
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| 342 | |
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| 343 | /* |
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| 344 | * 2430 - chassis (sedna) |
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| 345 | * 165 (ratio1) same as above #2 |
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| 346 | * 150 (ratio1) |
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| 347 | * 133 (ratio2) same as above #4 |
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| 348 | * 110 (ratio2) same as above #3 |
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| 349 | * 104 (ratio2) |
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| 350 | * boot (boot) |
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| 351 | */ |
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| 352 | |
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| 353 | /* PRCM I target DPLL = 2*330MHz = 660MHz */ |
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| 354 | #define MI_DPLL_MULT_12 (55 << 12) |
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| 355 | #define MI_DPLL_DIV_12 (1 << 8) |
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| 356 | #define MI_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ |
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| 357 | MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \ |
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| 358 | MX_APLLS_CLIKIN_12) |
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| 359 | |
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| 360 | /* |
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| 361 | * 2420 Equivalent - mode registers |
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| 362 | * PRCM II , target DPLL = 2*300MHz = 600MHz |
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| 363 | */ |
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| 364 | #define MII_DPLL_MULT_12 (50 << 12) |
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| 365 | #define MII_DPLL_DIV_12 (1 << 8) |
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| 366 | #define MII_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ |
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| 367 | MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \ |
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| 368 | MX_APLLS_CLIKIN_12) |
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| 369 | #define MII_DPLL_MULT_13 (300 << 12) |
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| 370 | #define MII_DPLL_DIV_13 (12 << 8) |
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| 371 | #define MII_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ |
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| 372 | MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \ |
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| 373 | MX_APLLS_CLIKIN_13) |
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| 374 | |
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| 375 | /* PRCM III target DPLL = 2*266 = 532MHz*/ |
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| 376 | #define MIII_DPLL_MULT_12 (133 << 12) |
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| 377 | #define MIII_DPLL_DIV_12 (5 << 8) |
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| 378 | #define MIII_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ |
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| 379 | MIII_DPLL_DIV_12 | \ |
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| 380 | MIII_DPLL_MULT_12 | MX_APLLS_CLIKIN_12) |
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| 381 | #define MIII_DPLL_MULT_13 (266 << 12) |
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| 382 | #define MIII_DPLL_DIV_13 (12 << 8) |
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| 383 | #define MIII_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ |
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| 384 | MIII_DPLL_DIV_13 | \ |
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| 385 | MIII_DPLL_MULT_13 | MX_APLLS_CLIKIN_13) |
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| 386 | |
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| 387 | /* PRCM VII (boot bypass) */ |
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| 388 | #define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL |
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| 389 | #define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL |
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| 390 | |
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| 391 | /* High and low operation value */ |
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| 392 | #define MX_CLKSEL2_PLL_2x_VAL (2 << 0) |
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| 393 | #define MX_CLKSEL2_PLL_1x_VAL (1 << 0) |
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| 394 | |
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| 395 | /* MPU speed defines */ |
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| 396 | #define S12M 12000000 |
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| 397 | #define S13M 13000000 |
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| 398 | #define S19M 19200000 |
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| 399 | #define S26M 26000000 |
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| 400 | #define S100M 100000000 |
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| 401 | #define S133M 133000000 |
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| 402 | #define S150M 150000000 |
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| 403 | #define S164M 164000000 |
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| 404 | #define S165M 165000000 |
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| 405 | #define S199M 199000000 |
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| 406 | #define S200M 200000000 |
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| 407 | #define S266M 266000000 |
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| 408 | #define S300M 300000000 |
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| 409 | #define S329M 329000000 |
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| 410 | #define S330M 330000000 |
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| 411 | #define S399M 399000000 |
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| 412 | #define S400M 400000000 |
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| 413 | #define S532M 532000000 |
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| 414 | #define S600M 600000000 |
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| 415 | #define S658M 658000000 |
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| 416 | #define S660M 660000000 |
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| 417 | #define S798M 798000000 |
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| 418 | |
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| 419 | |
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| 420 | extern const struct prcm_config omap2420_rate_table[]; |
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| 421 | |
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| 422 | #ifdef CONFIG_SOC_OMAP2430 |
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| 423 | extern const struct prcm_config omap2430_rate_table[]; |
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| 424 | #else |
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| 425 | #define omap2430_rate_table NULL |
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| 426 | #endif |
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| 427 | extern const struct prcm_config *rate_table; |
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| 428 | extern const struct prcm_config *curr_prcm_set; |
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| 429 | |
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| 430 | #endif |
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| 431 | |
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