1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * OMAP4+ Power Management Routines |
4 | * |
5 | * Copyright (C) 2010-2013 Texas Instruments, Inc. |
6 | * Rajendra Nayak <rnayak@ti.com> |
7 | * Santosh Shilimkar <santosh.shilimkar@ti.com> |
8 | */ |
9 | |
10 | #include <linux/pm.h> |
11 | #include <linux/suspend.h> |
12 | #include <linux/module.h> |
13 | #include <linux/list.h> |
14 | #include <linux/err.h> |
15 | #include <linux/slab.h> |
16 | #include <asm/system_misc.h> |
17 | |
18 | #include "soc.h" |
19 | #include "common.h" |
20 | #include "clockdomain.h" |
21 | #include "powerdomain.h" |
22 | #include "pm.h" |
23 | |
24 | u16 pm44xx_errata; |
25 | |
26 | struct power_state { |
27 | struct powerdomain *pwrdm; |
28 | u32 next_state; |
29 | u32 next_logic_state; |
30 | #ifdef CONFIG_SUSPEND |
31 | u32 saved_state; |
32 | u32 saved_logic_state; |
33 | #endif |
34 | struct list_head node; |
35 | }; |
36 | |
37 | /** |
38 | * struct static_dep_map - Static dependency map |
39 | * @from: from clockdomain |
40 | * @to: to clockdomain |
41 | */ |
42 | struct static_dep_map { |
43 | const char *from; |
44 | const char *to; |
45 | }; |
46 | |
47 | static u32 cpu_suspend_state = PWRDM_POWER_OFF; |
48 | |
49 | static LIST_HEAD(pwrst_list); |
50 | |
51 | #ifdef CONFIG_SUSPEND |
52 | static int omap4_pm_suspend(void) |
53 | { |
54 | struct power_state *pwrst; |
55 | int state, ret = 0; |
56 | u32 cpu_id = smp_processor_id(); |
57 | |
58 | /* Save current powerdomain state */ |
59 | list_for_each_entry(pwrst, &pwrst_list, node) { |
60 | pwrst->saved_state = pwrdm_read_next_pwrst(pwrdm: pwrst->pwrdm); |
61 | pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrdm: pwrst->pwrdm); |
62 | } |
63 | |
64 | /* Set targeted power domain states by suspend */ |
65 | list_for_each_entry(pwrst, &pwrst_list, node) { |
66 | omap_set_pwrdm_state(pwrdm: pwrst->pwrdm, state: pwrst->next_state); |
67 | pwrdm_set_logic_retst(pwrdm: pwrst->pwrdm, pwrst: pwrst->next_logic_state); |
68 | } |
69 | |
70 | /* |
71 | * For MPUSS to hit power domain retention(CSWR or OSWR), |
72 | * CPU0 and CPU1 power domains need to be in OFF or DORMANT state, |
73 | * since CPU power domain CSWR is not supported by hardware |
74 | * Only master CPU follows suspend path. All other CPUs follow |
75 | * CPU hotplug path in system wide suspend. On OMAP4, CPU power |
76 | * domain CSWR is not supported by hardware. |
77 | * More details can be found in OMAP4430 TRM section 4.3.4.2. |
78 | */ |
79 | omap4_enter_lowpower(cpu: cpu_id, power_state: cpu_suspend_state, rcuidle: false); |
80 | |
81 | /* Restore next powerdomain state */ |
82 | list_for_each_entry(pwrst, &pwrst_list, node) { |
83 | state = pwrdm_read_prev_pwrst(pwrdm: pwrst->pwrdm); |
84 | if (state > pwrst->next_state) { |
85 | pr_info("Powerdomain (%s) didn't enter target state %d\n" , |
86 | pwrst->pwrdm->name, pwrst->next_state); |
87 | ret = -1; |
88 | } |
89 | omap_set_pwrdm_state(pwrdm: pwrst->pwrdm, state: pwrst->saved_state); |
90 | pwrdm_set_logic_retst(pwrdm: pwrst->pwrdm, pwrst: pwrst->saved_logic_state); |
91 | } |
92 | if (ret) { |
93 | pr_crit("Could not enter target state in pm_suspend\n" ); |
94 | /* |
95 | * OMAP4 chip PM currently works only with certain (newer) |
96 | * versions of bootloaders. This is due to missing code in the |
97 | * kernel to properly reset and initialize some devices. |
98 | * Warn the user about the bootloader version being one of the |
99 | * possible causes. |
100 | * http://www.spinics.net/lists/arm-kernel/msg218641.html |
101 | */ |
102 | pr_debug("A possible cause could be an old bootloader - try u-boot >= v2012.07\n" ); |
103 | } else { |
104 | pr_info("Successfully put all powerdomains to target state\n" ); |
105 | } |
106 | |
107 | return 0; |
108 | } |
109 | #else |
110 | #define omap4_pm_suspend NULL |
111 | #endif /* CONFIG_SUSPEND */ |
112 | |
113 | static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) |
114 | { |
115 | struct power_state *pwrst; |
116 | |
117 | if (!pwrdm->pwrsts) |
118 | return 0; |
119 | |
120 | /* |
121 | * Skip CPU0 and CPU1 power domains. CPU1 is programmed |
122 | * through hotplug path and CPU0 explicitly programmed |
123 | * further down in the code path |
124 | */ |
125 | if (!strncmp(pwrdm->name, "cpu" , 3)) { |
126 | if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE)) |
127 | cpu_suspend_state = PWRDM_POWER_RET; |
128 | return 0; |
129 | } |
130 | |
131 | if (!strncmp(pwrdm->name, "core" , 4) || |
132 | !strncmp(pwrdm->name, "l4per" , 5)) |
133 | pwrdm_set_logic_retst(pwrdm, PWRDM_POWER_OFF); |
134 | |
135 | pwrst = kmalloc(size: sizeof(struct power_state), GFP_ATOMIC); |
136 | if (!pwrst) |
137 | return -ENOMEM; |
138 | |
139 | pwrst->pwrdm = pwrdm; |
140 | pwrst->next_state = pwrdm_get_valid_lp_state(pwrdm, is_logic_state: false, |
141 | PWRDM_POWER_RET); |
142 | pwrst->next_logic_state = pwrdm_get_valid_lp_state(pwrdm, is_logic_state: true, |
143 | PWRDM_POWER_OFF); |
144 | |
145 | list_add(new: &pwrst->node, head: &pwrst_list); |
146 | |
147 | return omap_set_pwrdm_state(pwrdm: pwrst->pwrdm, state: pwrst->next_state); |
148 | } |
149 | |
150 | /** |
151 | * omap_default_idle - OMAP4 default ilde routine.' |
152 | * |
153 | * Implements OMAP4 memory, IO ordering requirements which can't be addressed |
154 | * with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPU_IDLE and |
155 | * by secondary CPU with CONFIG_CPU_IDLE. |
156 | */ |
157 | static void omap_default_idle(void) |
158 | { |
159 | omap_do_wfi(); |
160 | } |
161 | |
162 | /* |
163 | * The dynamic dependency between MPUSS -> MEMIF and |
164 | * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as |
165 | * expected. The hardware recommendation is to enable static |
166 | * dependencies for these to avoid system lock ups or random crashes. |
167 | * The L4 wakeup depedency is added to workaround the OCP sync hardware |
168 | * BUG with 32K synctimer which lead to incorrect timer value read |
169 | * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which |
170 | * are part of L4 wakeup clockdomain. |
171 | */ |
172 | static const struct static_dep_map omap4_static_dep_map[] = { |
173 | {.from = "mpuss_clkdm" , .to = "l3_emif_clkdm" }, |
174 | {.from = "mpuss_clkdm" , .to = "l3_1_clkdm" }, |
175 | {.from = "mpuss_clkdm" , .to = "l3_2_clkdm" }, |
176 | {.from = "ducati_clkdm" , .to = "l3_1_clkdm" }, |
177 | {.from = "ducati_clkdm" , .to = "l3_2_clkdm" }, |
178 | {.from = NULL} /* TERMINATION */ |
179 | }; |
180 | |
181 | static const struct static_dep_map omap5_dra7_static_dep_map[] = { |
182 | {.from = "mpu_clkdm" , .to = "emif_clkdm" }, |
183 | {.from = NULL} /* TERMINATION */ |
184 | }; |
185 | |
186 | /** |
187 | * omap4plus_init_static_deps() - Initialize a static dependency map |
188 | * @map: Mapping of clock domains |
189 | */ |
190 | static inline int omap4plus_init_static_deps(const struct static_dep_map *map) |
191 | { |
192 | int ret; |
193 | struct clockdomain *from, *to; |
194 | |
195 | if (!map) |
196 | return 0; |
197 | |
198 | while (map->from) { |
199 | from = clkdm_lookup(name: map->from); |
200 | to = clkdm_lookup(name: map->to); |
201 | if (!from || !to) { |
202 | pr_err("Failed lookup %s or %s for wakeup dependency\n" , |
203 | map->from, map->to); |
204 | return -EINVAL; |
205 | } |
206 | ret = clkdm_add_wkdep(clkdm1: from, clkdm2: to); |
207 | if (ret) { |
208 | pr_err("Failed to add %s -> %s wakeup dependency(%d)\n" , |
209 | map->from, map->to, ret); |
210 | return ret; |
211 | } |
212 | |
213 | map++; |
214 | } |
215 | |
216 | return 0; |
217 | } |
218 | |
219 | /** |
220 | * omap4_pm_init_early - Does early initialization necessary for OMAP4+ devices |
221 | * |
222 | * Initializes basic stuff for power management functionality. |
223 | */ |
224 | int __init omap4_pm_init_early(void) |
225 | { |
226 | if (cpu_is_omap446x()) |
227 | pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD; |
228 | |
229 | if (soc_is_omap54xx() || soc_is_dra7xx()) |
230 | pm44xx_errata |= PM_OMAP4_CPU_OSWR_DISABLE; |
231 | |
232 | return 0; |
233 | } |
234 | |
235 | /** |
236 | * omap4_pm_init - Init routine for OMAP4+ devices |
237 | * |
238 | * Initializes all powerdomain and clockdomain target states |
239 | * and all PRCM settings. |
240 | * Return: Returns the error code returned by called functions. |
241 | */ |
242 | int __init omap4_pm_init(void) |
243 | { |
244 | int ret = 0; |
245 | |
246 | if (omap_rev() == OMAP4430_REV_ES1_0) { |
247 | WARN(1, "Power Management not supported on OMAP4430 ES1.0\n" ); |
248 | return -ENODEV; |
249 | } |
250 | |
251 | pr_info("Power Management for TI OMAP4+ devices.\n" ); |
252 | |
253 | /* |
254 | * OMAP4 chip PM currently works only with certain (newer) |
255 | * versions of bootloaders. This is due to missing code in the |
256 | * kernel to properly reset and initialize some devices. |
257 | * http://www.spinics.net/lists/arm-kernel/msg218641.html |
258 | */ |
259 | if (cpu_is_omap44xx()) |
260 | pr_debug("OMAP4 PM: u-boot >= v2012.07 is required for full PM support\n" ); |
261 | |
262 | ret = pwrdm_for_each(fn: pwrdms_setup, NULL); |
263 | if (ret) { |
264 | pr_err("Failed to setup powerdomains.\n" ); |
265 | goto err2; |
266 | } |
267 | |
268 | if (cpu_is_omap44xx()) |
269 | ret = omap4plus_init_static_deps(map: omap4_static_dep_map); |
270 | else if (soc_is_omap54xx() || soc_is_dra7xx()) |
271 | ret = omap4plus_init_static_deps(map: omap5_dra7_static_dep_map); |
272 | |
273 | if (ret) { |
274 | pr_err("Failed to initialise static dependencies.\n" ); |
275 | goto err2; |
276 | } |
277 | |
278 | ret = omap4_mpuss_init(); |
279 | if (ret) { |
280 | pr_err("Failed to initialise OMAP4 MPUSS\n" ); |
281 | goto err2; |
282 | } |
283 | |
284 | (void) clkdm_for_each(fn: omap_pm_clkdms_setup, NULL); |
285 | |
286 | omap_common_suspend_init(pm_suspend: omap4_pm_suspend); |
287 | |
288 | /* Overwrite the default cpu_do_idle() */ |
289 | arm_pm_idle = omap_default_idle; |
290 | |
291 | if (cpu_is_omap44xx() || soc_is_omap54xx()) |
292 | omap4_idle_init(); |
293 | |
294 | err2: |
295 | return ret; |
296 | } |
297 | |