| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * DRA7xx PRCM MPU instance offset macros |
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| 4 | * |
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| 5 | * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com |
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| 6 | * |
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| 7 | * Generated by code originally written by: |
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| 8 | * Paul Walmsley (paul@pwsan.com) |
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| 9 | * Rajendra Nayak (rnayak@ti.com) |
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| 10 | * Benoit Cousson (b-cousson@ti.com) |
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| 11 | * |
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| 12 | * This file is automatically generated from the OMAP hardware databases. |
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| 13 | * We respectfully ask that any modifications to this file be coordinated |
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| 14 | * with the public linux-omap@vger.kernel.org mailing list and the |
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| 15 | * authors above to ensure that the autogeneration scripts are kept |
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| 16 | * up-to-date with the file contents. |
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| 17 | */ |
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| 18 | |
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| 19 | #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H |
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| 20 | #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H |
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| 21 | |
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| 22 | #include "prcm_mpu_44xx_54xx.h" |
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| 23 | |
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| 24 | #define DRA7XX_PRCM_MPU_BASE 0x48243000 |
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| 25 | |
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| 26 | #define DRA7XX_PRCM_MPU_REGADDR(inst, reg) \ |
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| 27 | OMAP2_L4_IO_ADDRESS(DRA7XX_PRCM_MPU_BASE + (inst) + (reg)) |
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| 28 | |
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| 29 | /* MPU_PRCM instances */ |
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| 30 | #define DRA7XX_MPU_PRCM_OCP_SOCKET_INST 0x0000 |
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| 31 | #define DRA7XX_MPU_PRCM_DEVICE_INST 0x0200 |
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| 32 | #define DRA7XX_MPU_PRCM_PRM_C0_INST 0x0400 |
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| 33 | #define DRA7XX_MPU_PRCM_CM_C0_INST 0x0600 |
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| 34 | #define DRA7XX_MPU_PRCM_PRM_C1_INST 0x0800 |
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| 35 | #define DRA7XX_MPU_PRCM_CM_C1_INST 0x0a00 |
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| 36 | |
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| 37 | /* PRCM_MPU clockdomain register offsets (from instance start) */ |
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| 38 | #define DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS 0x0000 |
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| 39 | #define DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS 0x0000 |
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| 40 | |
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| 41 | |
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| 42 | /* MPU_PRCM */ |
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| 43 | |
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| 44 | /* MPU_PRCM.PRCM_MPU_OCP_SOCKET register offsets */ |
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| 45 | #define DRA7XX_REVISION_PRCM_MPU_OFFSET 0x0000 |
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| 46 | |
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| 47 | /* MPU_PRCM.PRCM_MPU_DEVICE register offsets */ |
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| 48 | #define DRA7XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET 0x0010 |
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| 49 | #define DRA7XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x0014 |
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| 50 | |
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| 51 | /* MPU_PRCM.PRCM_MPU_PRM_C0 register offsets */ |
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| 52 | #define DRA7XX_PM_CPU0_PWRSTCTRL_OFFSET 0x0000 |
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| 53 | #define DRA7XX_PM_CPU0_PWRSTST_OFFSET 0x0004 |
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| 54 | #define DRA7XX_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x0010 |
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| 55 | #define DRA7XX_RM_CPU0_CPU0_RSTST_OFFSET 0x0014 |
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| 56 | #define DRA7XX_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0024 |
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| 57 | |
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| 58 | /* MPU_PRCM.PRCM_MPU_CM_C0 register offsets */ |
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| 59 | #define DRA7XX_CM_CPU0_CLKSTCTRL_OFFSET 0x0000 |
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| 60 | #define DRA7XX_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0020 |
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| 61 | #define DRA7XX_CM_CPU0_CPU0_CLKCTRL DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C0_INST, 0x0020) |
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| 62 | |
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| 63 | /* MPU_PRCM.PRCM_MPU_PRM_C1 register offsets */ |
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| 64 | #define DRA7XX_PM_CPU1_PWRSTCTRL_OFFSET 0x0000 |
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| 65 | #define DRA7XX_PM_CPU1_PWRSTST_OFFSET 0x0004 |
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| 66 | #define DRA7XX_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x0010 |
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| 67 | #define DRA7XX_RM_CPU1_CPU1_RSTST_OFFSET 0x0014 |
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| 68 | #define DRA7XX_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0024 |
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| 69 | |
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| 70 | /* MPU_PRCM.PRCM_MPU_CM_C1 register offsets */ |
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| 71 | #define DRA7XX_CM_CPU1_CLKSTCTRL_OFFSET 0x0000 |
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| 72 | #define DRA7XX_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0020 |
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| 73 | #define DRA7XX_CM_CPU1_CPU1_CLKCTRL DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C1_INST, 0x0020) |
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| 74 | |
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| 75 | #endif |
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| 76 | |
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