1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * OMAP44xx Power Management register bits |
4 | * |
5 | * Copyright (C) 2009-2010 Texas Instruments, Inc. |
6 | * Copyright (C) 2009-2010 Nokia Corporation |
7 | * |
8 | * Paul Walmsley (paul@pwsan.com) |
9 | * Rajendra Nayak (rnayak@ti.com) |
10 | * Benoit Cousson (b-cousson@ti.com) |
11 | * |
12 | * This file is automatically generated from the OMAP hardware databases. |
13 | * We respectfully ask that any modifications to this file be coordinated |
14 | * with the public linux-omap@vger.kernel.org mailing list and the |
15 | * authors above to ensure that the autogeneration scripts are kept |
16 | * up-to-date with the file contents. |
17 | */ |
18 | |
19 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H |
20 | #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H |
21 | |
22 | #define OMAP4430_C2C_RST_SHIFT 10 |
23 | #define OMAP4430_CMDRA_VDD_CORE_L_MASK (0xff << 0) |
24 | #define OMAP4430_CMDRA_VDD_IVA_L_MASK (0xff << 8) |
25 | #define OMAP4430_CMDRA_VDD_MPU_L_MASK (0xff << 16) |
26 | #define OMAP4430_DATA_SHIFT 16 |
27 | #define OMAP4430_ERRORGAIN_MASK (0xff << 16) |
28 | #define OMAP4430_ERROROFFSET_MASK (0xff << 24) |
29 | #define OMAP4430_EXTERNAL_WARM_RST_SHIFT 5 |
30 | #define OMAP4430_FORCEUPDATE_MASK (1 << 1) |
31 | #define OMAP4430_GLOBAL_COLD_RST_SHIFT 0 |
32 | #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1 |
33 | #define OMAP4430_GLOBAL_WUEN_MASK (1 << 16) |
34 | #define OMAP4430_HSMCODE_MASK (0x7 << 0) |
35 | #define OMAP4430_SRMODEEN_MASK (1 << 4) |
36 | #define OMAP4430_HSMODEEN_MASK (1 << 3) |
37 | #define OMAP4430_HSSCLL_SHIFT 24 |
38 | #define OMAP4430_ICEPICK_RST_SHIFT 9 |
39 | #define OMAP4430_INITVDD_MASK (1 << 2) |
40 | #define OMAP4430_INITVOLTAGE_MASK (0xff << 8) |
41 | #define OMAP4430_LASTPOWERSTATEENTERED_SHIFT 24 |
42 | #define OMAP4430_LASTPOWERSTATEENTERED_MASK (0x3 << 24) |
43 | #define OMAP4430_LOGICRETSTATE_SHIFT 2 |
44 | #define OMAP4430_LOGICRETSTATE_MASK (1 << 2) |
45 | #define OMAP4430_LOGICSTATEST_SHIFT 2 |
46 | #define OMAP4430_LOGICSTATEST_MASK (1 << 2) |
47 | #define OMAP4430_LOSTCONTEXT_DFF_MASK (1 << 0) |
48 | #define OMAP4430_LOSTMEM_AESSMEM_MASK (1 << 8) |
49 | #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 4 |
50 | #define OMAP4430_LOWPOWERSTATECHANGE_MASK (1 << 4) |
51 | #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 2 |
52 | #define OMAP4430_MPU_WDT_RST_SHIFT 3 |
53 | #define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24) |
54 | #define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK (1 << 12) |
55 | #define OMAP4430_OCP_NRET_BANK_STATEST_MASK (0x3 << 12) |
56 | #define OMAP4430_OFF_SHIFT 0 |
57 | #define OMAP4430_ON_SHIFT 24 |
58 | #define OMAP4430_ON_MASK (0xff << 24) |
59 | #define OMAP4430_ONLP_SHIFT 16 |
60 | #define OMAP4430_RAMP_DOWN_COUNT_SHIFT 16 |
61 | #define OMAP4430_RAMP_UP_COUNT_SHIFT 0 |
62 | #define OMAP4430_RAMP_UP_PRESCAL_SHIFT 8 |
63 | #define OMAP4430_REGADDR_SHIFT 8 |
64 | #define OMAP4430_RET_SHIFT 8 |
65 | #define OMAP4430_RST_GLOBAL_WARM_SW_MASK (1 << 0) |
66 | #define OMAP4430_SA_VDD_CORE_L_SHIFT 0 |
67 | #define OMAP4430_SA_VDD_CORE_L_0_6_MASK (0x7f << 0) |
68 | #define OMAP4430_SA_VDD_IVA_L_SHIFT 8 |
69 | #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK (0x7f << 8) |
70 | #define OMAP4430_SA_VDD_MPU_L_SHIFT 16 |
71 | #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK (0x7f << 16) |
72 | #define OMAP4430_SCLH_SHIFT 0 |
73 | #define OMAP4430_SCLL_SHIFT 8 |
74 | #define OMAP4430_SECURE_WDT_RST_SHIFT 4 |
75 | #define OMAP4430_SLAVEADDR_SHIFT 0 |
76 | #define OMAP4430_SMPSWAITTIMEMAX_SHIFT 8 |
77 | #define OMAP4430_SMPSWAITTIMEMIN_SHIFT 8 |
78 | #define OMAP4430_TIMEOUT_SHIFT 0 |
79 | #define OMAP4430_TIMEOUTEN_MASK (1 << 3) |
80 | #define OMAP4430_VALID_MASK (1 << 24) |
81 | #define OMAP4430_VDDMAX_SHIFT 24 |
82 | #define OMAP4430_VDDMIN_SHIFT 16 |
83 | #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT 8 |
84 | #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT 7 |
85 | #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT 6 |
86 | #define OMAP4430_VOLRA_VDD_CORE_L_MASK (0xff << 0) |
87 | #define OMAP4430_VOLRA_VDD_IVA_L_MASK (0xff << 8) |
88 | #define OMAP4430_VOLRA_VDD_MPU_L_MASK (0xff << 16) |
89 | #define OMAP4430_VPENABLE_MASK (1 << 0) |
90 | #define OMAP4430_VPVOLTAGE_MASK (0xff << 0) |
91 | #define OMAP4430_VP_CORE_TRANXDONE_ST_MASK (1 << 21) |
92 | #define OMAP4430_VP_IVA_TRANXDONE_ST_MASK (1 << 29) |
93 | #define OMAP4430_VP_MPU_TRANXDONE_ST_MASK (1 << 5) |
94 | #define OMAP4430_VSTEPMAX_SHIFT 0 |
95 | #define OMAP4430_VSTEPMIN_SHIFT 0 |
96 | #define OMAP4430_WUCLK_CTRL_MASK (1 << 8) |
97 | #define OMAP4430_WUCLK_STATUS_SHIFT 9 |
98 | #define OMAP4430_WUCLK_STATUS_MASK (1 << 9) |
99 | #endif |
100 | |