1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * OMAP2/3/4 Power/Reset Management (PRM) bitfield definitions |
4 | * |
5 | * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc. |
6 | * Copyright (C) 2010 Nokia Corporation |
7 | * |
8 | * Paul Walmsley |
9 | */ |
10 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM_H |
11 | #define __ARCH_ARM_MACH_OMAP2_PRM_H |
12 | |
13 | #include "prcm-common.h" |
14 | |
15 | # ifndef __ASSEMBLER__ |
16 | extern struct omap_domain_base prm_base; |
17 | extern u16 prm_features; |
18 | int omap_prcm_init(void); |
19 | int omap2_prcm_base_init(void); |
20 | # endif |
21 | |
22 | /* |
23 | * prm_features flag values |
24 | * |
25 | * PRM_HAS_IO_WAKEUP: has IO wakeup capability |
26 | * PRM_HAS_VOLTAGE: has voltage domains |
27 | */ |
28 | #define PRM_HAS_IO_WAKEUP BIT(0) |
29 | #define PRM_HAS_VOLTAGE BIT(1) |
30 | |
31 | /* |
32 | * MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP |
33 | * module to softreset |
34 | */ |
35 | #define MAX_MODULE_SOFTRESET_WAIT 10000 |
36 | |
37 | /* |
38 | * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP |
39 | * submodule to exit hardreset |
40 | */ |
41 | #define MAX_MODULE_HARDRESET_WAIT 10000 |
42 | |
43 | /* |
44 | * Register bitfields |
45 | */ |
46 | |
47 | /* |
48 | * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP |
49 | * |
50 | * 2430: PM_PWSTST_MDM |
51 | * |
52 | * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX, |
53 | * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU, |
54 | * PM_PWSTST_NEON |
55 | */ |
56 | #define OMAP_INTRANSITION_MASK (1 << 20) |
57 | |
58 | |
59 | /* |
60 | * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP |
61 | * |
62 | * 2430: PM_PWSTST_MDM |
63 | * |
64 | * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX, |
65 | * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU, |
66 | * PM_PWSTST_NEON |
67 | */ |
68 | #define OMAP_POWERSTATEST_SHIFT 0 |
69 | #define OMAP_POWERSTATEST_MASK (0x3 << 0) |
70 | |
71 | /* |
72 | * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, |
73 | * PM_PWSTCTRL_DSP, PM_PWSTST_MPU |
74 | * |
75 | * 2430: PM_PWSTCTRL_MDM shared bits |
76 | * |
77 | * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, |
78 | * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER, |
79 | * PM_PWSTCTRL_NEON shared bits |
80 | */ |
81 | #define OMAP_POWERSTATE_SHIFT 0 |
82 | #define OMAP_POWERSTATE_MASK (0x3 << 0) |
83 | |
84 | /* |
85 | * Standardized OMAP reset source bits |
86 | * |
87 | * To the extent these happen to match the hardware register bit |
88 | * shifts, it's purely coincidental. Used by omap-wdt.c. |
89 | * OMAP_UNKNOWN_RST_SRC_ID_SHIFT is a special value, used whenever |
90 | * there are any bits remaining in the global PRM_RSTST register that |
91 | * haven't been identified, or when the PRM code for the current SoC |
92 | * doesn't know how to interpret the register. |
93 | */ |
94 | #define OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT 0 |
95 | #define OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT 1 |
96 | #define OMAP_SECU_VIOL_RST_SRC_ID_SHIFT 2 |
97 | #define OMAP_MPU_WD_RST_SRC_ID_SHIFT 3 |
98 | #define OMAP_SECU_WD_RST_SRC_ID_SHIFT 4 |
99 | #define OMAP_EXTWARM_RST_SRC_ID_SHIFT 5 |
100 | #define OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT 6 |
101 | #define OMAP_VDD_IVA_VM_RST_SRC_ID_SHIFT 7 |
102 | #define OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT 8 |
103 | #define OMAP_ICEPICK_RST_SRC_ID_SHIFT 9 |
104 | #define OMAP_ICECRUSHER_RST_SRC_ID_SHIFT 10 |
105 | #define OMAP_C2C_RST_SRC_ID_SHIFT 11 |
106 | #define OMAP_UNKNOWN_RST_SRC_ID_SHIFT 12 |
107 | |
108 | #ifndef __ASSEMBLER__ |
109 | |
110 | /** |
111 | * struct prm_reset_src_map - map register bitshifts to standard bitshifts |
112 | * @reg_shift: bitshift in the PRM reset source register |
113 | * @std_shift: bitshift equivalent in the standard reset source list |
114 | * |
115 | * The fields are signed because -1 is used as a terminator. |
116 | */ |
117 | struct prm_reset_src_map { |
118 | s8 reg_shift; |
119 | s8 std_shift; |
120 | }; |
121 | |
122 | /** |
123 | * struct prm_ll_data - fn ptrs to per-SoC PRM function implementations |
124 | * @read_reset_sources: ptr to the SoC PRM-specific get_reset_source impl |
125 | * @was_any_context_lost_old: ptr to the SoC PRM context loss test fn |
126 | * @clear_context_loss_flags_old: ptr to the SoC PRM context loss flag clear fn |
127 | * @late_init: ptr to the late init function |
128 | * @assert_hardreset: ptr to the SoC PRM hardreset assert impl |
129 | * @deassert_hardreset: ptr to the SoC PRM hardreset deassert impl |
130 | * |
131 | * XXX @was_any_context_lost_old and @clear_context_loss_flags_old are |
132 | * deprecated. |
133 | */ |
134 | struct prm_ll_data { |
135 | u32 (*read_reset_sources)(void); |
136 | bool (*was_any_context_lost_old)(u8 part, s16 inst, u16 idx); |
137 | void (*clear_context_loss_flags_old)(u8 part, s16 inst, u16 idx); |
138 | int (*late_init)(void); |
139 | int (*assert_hardreset)(u8 shift, u8 part, s16 prm_mod, u16 offset); |
140 | int (*deassert_hardreset)(u8 shift, u8 st_shift, u8 part, s16 prm_mod, |
141 | u16 offset, u16 st_offset); |
142 | int (*is_hardreset_asserted)(u8 shift, u8 part, s16 prm_mod, |
143 | u16 offset); |
144 | void (*reset_system)(void); |
145 | int (*clear_mod_irqs)(s16 module, u8 regs, u32 wkst_mask); |
146 | u32 (*vp_check_txdone)(u8 vp_id); |
147 | void (*vp_clear_txdone)(u8 vp_id); |
148 | }; |
149 | |
150 | extern int prm_register(struct prm_ll_data *pld); |
151 | extern int prm_unregister(struct prm_ll_data *pld); |
152 | |
153 | int omap_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod, u16 offset); |
154 | int omap_prm_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 prm_mod, |
155 | u16 offset, u16 st_offset); |
156 | int omap_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset); |
157 | extern bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx); |
158 | extern void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx); |
159 | void omap_prm_reset_system(void); |
160 | |
161 | int omap_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask); |
162 | |
163 | /* |
164 | * Voltage Processor (VP) identifiers |
165 | */ |
166 | #define OMAP3_VP_VDD_MPU_ID 0 |
167 | #define OMAP3_VP_VDD_CORE_ID 1 |
168 | #define OMAP4_VP_VDD_CORE_ID 0 |
169 | #define OMAP4_VP_VDD_IVA_ID 1 |
170 | #define OMAP4_VP_VDD_MPU_ID 2 |
171 | |
172 | u32 omap_prm_vp_check_txdone(u8 vp_id); |
173 | void omap_prm_vp_clear_txdone(u8 vp_id); |
174 | |
175 | #endif |
176 | |
177 | |
178 | #endif |
179 | |