1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * OMAP2xxx/3xxx-common Power/Reset Management (PRM) register definitions |
4 | * |
5 | * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc. |
6 | * Copyright (C) 2008-2010 Nokia Corporation |
7 | * Paul Walmsley |
8 | * |
9 | * The PRM hardware modules on the OMAP2/3 are quite similar to each |
10 | * other. The PRM on OMAP4 has a new register layout, and is handled |
11 | * in a separate file. |
12 | */ |
13 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H |
14 | #define __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H |
15 | |
16 | #include "prcm-common.h" |
17 | #include "prm.h" |
18 | |
19 | /* |
20 | * Module specific PRM register offsets from PRM_BASE + domain offset |
21 | * |
22 | * Use prm_{read,write}_mod_reg() with these registers. |
23 | * |
24 | * With a few exceptions, these are the register names beginning with |
25 | * {PM,RM}_* on both OMAP2/3 SoC families.. (The exceptions are the |
26 | * IRQSTATUS and IRQENABLE bits.) |
27 | */ |
28 | |
29 | /* Register offsets appearing on both OMAP2 and OMAP3 */ |
30 | |
31 | #define OMAP2_RM_RSTCTRL 0x0050 |
32 | #define OMAP2_RM_RSTTIME 0x0054 |
33 | #define OMAP2_RM_RSTST 0x0058 |
34 | #define OMAP2_PM_PWSTCTRL 0x00e0 |
35 | #define OMAP2_PM_PWSTST 0x00e4 |
36 | |
37 | #define PM_WKEN 0x00a0 |
38 | #define PM_WKEN1 PM_WKEN |
39 | #define PM_WKST 0x00b0 |
40 | #define PM_WKST1 PM_WKST |
41 | #define PM_WKDEP 0x00c8 |
42 | #define PM_EVGENCTRL 0x00d4 |
43 | #define PM_EVGENONTIM 0x00d8 |
44 | #define PM_EVGENOFFTIM 0x00dc |
45 | |
46 | |
47 | #ifndef __ASSEMBLER__ |
48 | |
49 | #include <linux/io.h> |
50 | #include "powerdomain.h" |
51 | |
52 | /* Power/reset management domain register get/set */ |
53 | static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx) |
54 | { |
55 | return readl_relaxed(prm_base.va + module + idx); |
56 | } |
57 | |
58 | static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx) |
59 | { |
60 | writel_relaxed(val, prm_base.va + module + idx); |
61 | } |
62 | |
63 | /* Read-modify-write a register in a PRM module. Caller must lock */ |
64 | static inline u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, |
65 | s16 idx) |
66 | { |
67 | u32 v; |
68 | |
69 | v = omap2_prm_read_mod_reg(module, idx); |
70 | v &= ~mask; |
71 | v |= bits; |
72 | omap2_prm_write_mod_reg(val: v, module, idx); |
73 | |
74 | return v; |
75 | } |
76 | |
77 | /* Read a PRM register, AND it, and shift the result down to bit 0 */ |
78 | static inline u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) |
79 | { |
80 | u32 v; |
81 | |
82 | v = omap2_prm_read_mod_reg(module: domain, idx); |
83 | v &= mask; |
84 | v >>= __ffs(mask); |
85 | |
86 | return v; |
87 | } |
88 | |
89 | static inline u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) |
90 | { |
91 | return omap2_prm_rmw_mod_reg_bits(mask: bits, bits, module, idx); |
92 | } |
93 | |
94 | static inline u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) |
95 | { |
96 | return omap2_prm_rmw_mod_reg_bits(mask: bits, bits: 0x0, module, idx); |
97 | } |
98 | |
99 | /* These omap2_ PRM functions apply to both OMAP2 and 3 */ |
100 | int omap2_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset); |
101 | int omap2_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod, |
102 | u16 offset); |
103 | int omap2_prm_deassert_hardreset(u8 rst_shift, u8 st_shift, u8 part, |
104 | s16 prm_mod, u16 reset_offset, |
105 | u16 st_offset); |
106 | |
107 | extern int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, |
108 | u8 pwrst); |
109 | extern int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, |
110 | u8 pwrst); |
111 | extern int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank); |
112 | extern int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank); |
113 | extern int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst); |
114 | extern int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm); |
115 | |
116 | extern int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1, |
117 | struct clockdomain *clkdm2); |
118 | extern int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1, |
119 | struct clockdomain *clkdm2); |
120 | extern int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1, |
121 | struct clockdomain *clkdm2); |
122 | extern int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm); |
123 | |
124 | #endif /* __ASSEMBLER */ |
125 | |
126 | /* |
127 | * Bits common to specific registers |
128 | * |
129 | * The 3430 register and bit names are generally used, |
130 | * since they tend to make more sense |
131 | */ |
132 | |
133 | /* PM_EVGENONTIM_MPU */ |
134 | /* Named PM_EVEGENONTIM_MPU on the 24XX */ |
135 | #define OMAP_ONTIMEVAL_SHIFT 0 |
136 | #define OMAP_ONTIMEVAL_MASK (0xffffffff << 0) |
137 | |
138 | /* PM_EVGENOFFTIM_MPU */ |
139 | /* Named PM_EVEGENOFFTIM_MPU on the 24XX */ |
140 | #define OMAP_OFFTIMEVAL_SHIFT 0 |
141 | #define OMAP_OFFTIMEVAL_MASK (0xffffffff << 0) |
142 | |
143 | /* PRM_CLKSETUP and PRCM_VOLTSETUP */ |
144 | /* Named PRCM_CLKSSETUP on the 24XX */ |
145 | #define OMAP_SETUP_TIME_SHIFT 0 |
146 | #define OMAP_SETUP_TIME_MASK (0xffff << 0) |
147 | |
148 | /* PRM_CLKSRC_CTRL */ |
149 | /* Named PRCM_CLKSRC_CTRL on the 24XX */ |
150 | #define OMAP_SYSCLKDIV_SHIFT 6 |
151 | #define OMAP_SYSCLKDIV_MASK (0x3 << 6) |
152 | #define OMAP_SYSCLKDIV_WIDTH 2 |
153 | #define OMAP_AUTOEXTCLKMODE_SHIFT 3 |
154 | #define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3) |
155 | #define OMAP_SYSCLKSEL_SHIFT 0 |
156 | #define OMAP_SYSCLKSEL_MASK (0x3 << 0) |
157 | |
158 | /* PM_EVGENCTRL_MPU */ |
159 | #define OMAP_OFFLOADMODE_SHIFT 3 |
160 | #define OMAP_OFFLOADMODE_MASK (0x3 << 3) |
161 | #define OMAP_ONLOADMODE_SHIFT 1 |
162 | #define OMAP_ONLOADMODE_MASK (0x3 << 1) |
163 | #define OMAP_ENABLE_MASK (1 << 0) |
164 | |
165 | /* PRM_RSTTIME */ |
166 | /* Named RM_RSTTIME_WKUP on the 24xx */ |
167 | #define OMAP_RSTTIME2_SHIFT 8 |
168 | #define OMAP_RSTTIME2_MASK (0x1f << 8) |
169 | #define OMAP_RSTTIME1_SHIFT 0 |
170 | #define OMAP_RSTTIME1_MASK (0xff << 0) |
171 | |
172 | /* PRM_RSTCTRL */ |
173 | /* Named RM_RSTCTRL_WKUP on the 24xx */ |
174 | /* 2420 calls RST_DPLL3 'RST_DPLL' */ |
175 | #define OMAP_RST_DPLL3_MASK (1 << 2) |
176 | #define OMAP_RST_GS_MASK (1 << 1) |
177 | |
178 | |
179 | /* |
180 | * Bits common to module-shared registers |
181 | * |
182 | * Not all registers of a particular type support all of these bits - |
183 | * check TRM if you are unsure |
184 | */ |
185 | |
186 | /* |
187 | * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is |
188 | * called 'COREWKUP_RST' |
189 | * |
190 | * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS, |
191 | * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON |
192 | */ |
193 | #define OMAP_COREDOMAINWKUP_RST_MASK (1 << 3) |
194 | |
195 | /* |
196 | * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP |
197 | * |
198 | * 2430: RM_RSTST_MDM |
199 | * |
200 | * 3430: RM_RSTST_CORE, RM_RSTST_EMU |
201 | */ |
202 | #define OMAP_DOMAINWKUP_RST_MASK (1 << 2) |
203 | |
204 | /* |
205 | * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP |
206 | * On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'. |
207 | * |
208 | * 2430: RM_RSTST_MDM |
209 | * |
210 | * 3430: RM_RSTST_CORE, RM_RSTST_EMU |
211 | */ |
212 | #define OMAP_GLOBALWARM_RST_SHIFT 1 |
213 | #define OMAP_GLOBALWARM_RST_MASK (1 << 1) |
214 | #define OMAP_GLOBALCOLD_RST_SHIFT 0 |
215 | #define OMAP_GLOBALCOLD_RST_MASK (1 << 0) |
216 | |
217 | /* |
218 | * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP |
219 | * 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP" |
220 | * |
221 | * 2430: PM_WKDEP_MDM |
222 | * |
223 | * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM, |
224 | * PM_WKDEP_PER |
225 | */ |
226 | #define OMAP_EN_WKUP_SHIFT 4 |
227 | #define OMAP_EN_WKUP_MASK (1 << 4) |
228 | |
229 | /* |
230 | * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, |
231 | * PM_PWSTCTRL_DSP |
232 | * |
233 | * 2430: PM_PWSTCTRL_MDM |
234 | * |
235 | * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, |
236 | * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER, |
237 | * PM_PWSTCTRL_NEON |
238 | */ |
239 | #define OMAP_LOGICRETSTATE_MASK (1 << 2) |
240 | |
241 | |
242 | #endif |
243 | |