1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * OMAP3xxx Power/Reset Management (PRM) register definitions |
4 | * |
5 | * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc. |
6 | * Copyright (C) 2008-2010 Nokia Corporation |
7 | * Paul Walmsley |
8 | * |
9 | * The PRM hardware modules on the OMAP2/3 are quite similar to each |
10 | * other. The PRM on OMAP4 has a new register layout, and is handled |
11 | * in a separate file. |
12 | */ |
13 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM3XXX_H |
14 | #define __ARCH_ARM_MACH_OMAP2_PRM3XXX_H |
15 | |
16 | #include "prcm-common.h" |
17 | #include "prm.h" |
18 | #include "prm2xxx_3xxx.h" |
19 | |
20 | #define OMAP34XX_PRM_REGADDR(module, reg) \ |
21 | OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) |
22 | |
23 | |
24 | /* |
25 | * OMAP3-specific global PRM registers |
26 | * Use {read,write}l_relaxed() with these registers. |
27 | * |
28 | * With a few exceptions, these are the register names beginning with |
29 | * PRM_* on 34xx. (The exceptions are the IRQSTATUS and IRQENABLE |
30 | * bits.) |
31 | */ |
32 | |
33 | #define OMAP3_PRM_REVISION_OFFSET 0x0004 |
34 | #define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004) |
35 | #define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014 |
36 | #define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014) |
37 | |
38 | #define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018 |
39 | #define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018) |
40 | #define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c |
41 | #define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c) |
42 | |
43 | |
44 | #define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020 |
45 | #define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020) |
46 | #define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024 |
47 | #define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024) |
48 | #define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028 |
49 | #define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028) |
50 | #define OMAP3_PRM_VC_CMD_VAL_0_OFFSET 0x002c |
51 | #define OMAP3430_PRM_VC_CMD_VAL_0 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c) |
52 | #define OMAP3_PRM_VC_CMD_VAL_1_OFFSET 0x0030 |
53 | #define OMAP3430_PRM_VC_CMD_VAL_1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030) |
54 | #define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034 |
55 | #define OMAP3430_PRM_VC_CH_CONF OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034) |
56 | #define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038 |
57 | #define OMAP3430_PRM_VC_I2C_CFG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038) |
58 | #define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c |
59 | #define OMAP3430_PRM_VC_BYPASS_VAL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c) |
60 | #define OMAP3_PRM_RSTCTRL_OFFSET 0x0050 |
61 | #define OMAP3430_PRM_RSTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050) |
62 | #define OMAP3_PRM_RSTTIME_OFFSET 0x0054 |
63 | #define OMAP3430_PRM_RSTTIME OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054) |
64 | #define OMAP3_PRM_RSTST_OFFSET 0x0058 |
65 | #define OMAP3430_PRM_RSTST OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058) |
66 | #define OMAP3_PRM_VOLTCTRL_OFFSET 0x0060 |
67 | #define OMAP3430_PRM_VOLTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060) |
68 | #define OMAP3_PRM_SRAM_PCHARGE_OFFSET 0x0064 |
69 | #define OMAP3430_PRM_SRAM_PCHARGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064) |
70 | #define OMAP3_PRM_CLKSRC_CTRL_OFFSET 0x0070 |
71 | #define OMAP3430_PRM_CLKSRC_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070) |
72 | #define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090 |
73 | #define OMAP3430_PRM_VOLTSETUP1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090) |
74 | #define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094 |
75 | #define OMAP3430_PRM_VOLTOFFSET OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094) |
76 | #define OMAP3_PRM_CLKSETUP_OFFSET 0x0098 |
77 | #define OMAP3430_PRM_CLKSETUP OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098) |
78 | #define OMAP3_PRM_POLCTRL_OFFSET 0x009c |
79 | #define OMAP3430_PRM_POLCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c) |
80 | #define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0 |
81 | #define OMAP3430_PRM_VOLTSETUP2 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0) |
82 | #define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0 |
83 | #define OMAP3430_PRM_VP1_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0) |
84 | #define OMAP3_PRM_VP1_VSTEPMIN_OFFSET 0x00b4 |
85 | #define OMAP3430_PRM_VP1_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4) |
86 | #define OMAP3_PRM_VP1_VSTEPMAX_OFFSET 0x00b8 |
87 | #define OMAP3430_PRM_VP1_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8) |
88 | #define OMAP3_PRM_VP1_VLIMITTO_OFFSET 0x00bc |
89 | #define OMAP3430_PRM_VP1_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc) |
90 | #define OMAP3_PRM_VP1_VOLTAGE_OFFSET 0x00c0 |
91 | #define OMAP3430_PRM_VP1_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0) |
92 | #define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4 |
93 | #define OMAP3430_PRM_VP1_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4) |
94 | #define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0 |
95 | #define OMAP3430_PRM_VP2_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0) |
96 | #define OMAP3_PRM_VP2_VSTEPMIN_OFFSET 0x00d4 |
97 | #define OMAP3430_PRM_VP2_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4) |
98 | #define OMAP3_PRM_VP2_VSTEPMAX_OFFSET 0x00d8 |
99 | #define OMAP3430_PRM_VP2_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8) |
100 | #define OMAP3_PRM_VP2_VLIMITTO_OFFSET 0x00dc |
101 | #define OMAP3430_PRM_VP2_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc) |
102 | #define OMAP3_PRM_VP2_VOLTAGE_OFFSET 0x00e0 |
103 | #define OMAP3430_PRM_VP2_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0) |
104 | #define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4 |
105 | #define OMAP3430_PRM_VP2_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4) |
106 | |
107 | #define OMAP3_PRM_CLKSEL_OFFSET 0x0040 |
108 | #define OMAP3430_PRM_CLKSEL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040) |
109 | #define OMAP3_PRM_CLKOUT_CTRL_OFFSET 0x0070 |
110 | #define OMAP3430_PRM_CLKOUT_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070) |
111 | |
112 | /* OMAP3 specific register offsets */ |
113 | #define OMAP3430ES2_PM_WKEN3 0x00f0 |
114 | #define OMAP3430ES2_PM_WKST3 0x00b8 |
115 | |
116 | #define OMAP3430_PM_MPUGRPSEL 0x00a4 |
117 | #define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL |
118 | #define OMAP3430ES2_PM_MPUGRPSEL3 0x00f8 |
119 | |
120 | #define OMAP3430_PM_IVAGRPSEL 0x00a8 |
121 | #define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL |
122 | #define OMAP3430ES2_PM_IVAGRPSEL3 0x00f4 |
123 | |
124 | #define OMAP3430_PM_PREPWSTST 0x00e8 |
125 | |
126 | #define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8 |
127 | #define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc |
128 | |
129 | |
130 | #ifndef __ASSEMBLER__ |
131 | |
132 | /* |
133 | * OMAP3 access functions for voltage controller (VC) and |
134 | * voltage proccessor (VP) in the PRM. |
135 | */ |
136 | extern u32 omap3_prm_vcvp_read(u8 offset); |
137 | extern void omap3_prm_vcvp_write(u32 val, u8 offset); |
138 | extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); |
139 | |
140 | int __init omap3xxx_prm_init(const struct omap_prcm_init_data *data); |
141 | int omap3xxx_prm_clear_global_cold_reset(void); |
142 | void omap3_prm_save_scratchpad_contents(u32 *ptr); |
143 | void omap3_prm_init_pm(bool has_uart4, bool has_iva); |
144 | |
145 | #endif /* __ASSEMBLER */ |
146 | |
147 | |
148 | #endif |
149 | |