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1 | /* SPDX-License-Identifier: GPL-2.0 */ |
---|---|
2 | /* |
3 | * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima |
4 | * Copyright (C) 2002 Paul Mundt |
5 | */ |
6 | #ifndef __ASM_SH_BARRIER_H |
7 | #define __ASM_SH_BARRIER_H |
8 | |
9 | #if defined(CONFIG_CPU_SH4A) |
10 | #include <asm/cache_insns.h> |
11 | #endif |
12 | |
13 | /* |
14 | * A brief note on ctrl_barrier(), the control register write barrier. |
15 | * |
16 | * Legacy SH cores typically require a sequence of 8 nops after |
17 | * modification of a control register in order for the changes to take |
18 | * effect. On newer cores (like the sh4a and sh5) this is accomplished |
19 | * with icbi. |
20 | * |
21 | * Also note that on sh4a in the icbi case we can forego a synco for the |
22 | * write barrier, as it's not necessary for control registers. |
23 | * |
24 | * Historically we have only done this type of barrier for the MMUCR, but |
25 | * it's also necessary for the CCR, so we make it generic here instead. |
26 | */ |
27 | #if defined(CONFIG_CPU_SH4A) |
28 | #define mb() __asm__ __volatile__ ("synco": : :"memory") |
29 | #define rmb() mb() |
30 | #define wmb() mb() |
31 | #define ctrl_barrier() __icbi(PAGE_OFFSET) |
32 | #else |
33 | #if defined(CONFIG_CPU_J2) && defined(CONFIG_SMP) |
34 | #define __smp_mb() do { int tmp = 0; __asm__ __volatile__ ("cas.l %0,%0,@%1" : "+r"(tmp) : "z"(&tmp) : "memory", "t"); } while(0) |
35 | #define __smp_rmb() __smp_mb() |
36 | #define __smp_wmb() __smp_mb() |
37 | #endif |
38 | #define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop") |
39 | #endif |
40 | |
41 | #define __smp_store_mb(var, value) do { (void)xchg(&var, value); } while (0) |
42 | |
43 | #include <asm-generic/barrier.h> |
44 | |
45 | #endif /* __ASM_SH_BARRIER_H */ |
46 |
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