1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_X86_APICDEF_H
3#define _ASM_X86_APICDEF_H
4
5#include <linux/bits.h>
6
7/*
8 * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
9 *
10 * Alan Cox <Alan.Cox@linux.org>, 1995.
11 * Ingo Molnar <mingo@redhat.com>, 1999, 2000
12 */
13
14#define IO_APIC_DEFAULT_PHYS_BASE 0xfec00000
15#define APIC_DEFAULT_PHYS_BASE 0xfee00000
16
17/*
18 * This is the IO-APIC register space as specified
19 * by Intel docs:
20 */
21#define IO_APIC_SLOT_SIZE 1024
22
23#define APIC_ID 0x20
24
25#define APIC_LVR 0x30
26#define APIC_LVR_MASK 0xFF00FF
27#define APIC_LVR_DIRECTED_EOI (1 << 24)
28#define GET_APIC_VERSION(x) ((x) & 0xFFu)
29#define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu)
30#ifdef CONFIG_X86_32
31# define APIC_INTEGRATED(x) ((x) & 0xF0u)
32#else
33# define APIC_INTEGRATED(x) (1)
34#endif
35#define APIC_XAPIC(x) ((x) >= 0x14)
36#define APIC_EXT_SPACE(x) ((x) & 0x80000000)
37#define APIC_TASKPRI 0x80
38#define APIC_TPRI_MASK 0xFFu
39#define APIC_ARBPRI 0x90
40#define APIC_ARBPRI_MASK 0xFFu
41#define APIC_PROCPRI 0xA0
42#define APIC_EOI 0xB0
43#define APIC_EOI_ACK 0x0 /* Docs say 0 for future compat. */
44#define APIC_RRR 0xC0
45#define APIC_LDR 0xD0
46#define APIC_LDR_MASK (0xFFu << 24)
47#define GET_APIC_LOGICAL_ID(x) (((x) >> 24) & 0xFFu)
48#define SET_APIC_LOGICAL_ID(x) (((x) << 24))
49#define APIC_ALL_CPUS 0xFFu
50#define APIC_DFR 0xE0
51#define APIC_DFR_CLUSTER 0x0FFFFFFFul
52#define APIC_DFR_FLAT 0xFFFFFFFFul
53#define APIC_SPIV 0xF0
54#define APIC_SPIV_DIRECTED_EOI (1 << 12)
55#define APIC_SPIV_FOCUS_DISABLED (1 << 9)
56#define APIC_SPIV_APIC_ENABLED (1 << 8)
57#define APIC_ISR 0x100
58#define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */
59#define APIC_TMR 0x180
60#define APIC_IRR 0x200
61#define APIC_ESR 0x280
62#define APIC_ESR_SEND_CS 0x00001
63#define APIC_ESR_RECV_CS 0x00002
64#define APIC_ESR_SEND_ACC 0x00004
65#define APIC_ESR_RECV_ACC 0x00008
66#define APIC_ESR_SENDILL 0x00020
67#define APIC_ESR_RECVILL 0x00040
68#define APIC_ESR_ILLREGA 0x00080
69#define APIC_LVTCMCI 0x2f0
70#define APIC_ICR 0x300
71#define APIC_DEST_SELF 0x40000
72#define APIC_DEST_ALLINC 0x80000
73#define APIC_DEST_ALLBUT 0xC0000
74#define APIC_ICR_RR_MASK 0x30000
75#define APIC_ICR_RR_INVALID 0x00000
76#define APIC_ICR_RR_INPROG 0x10000
77#define APIC_ICR_RR_VALID 0x20000
78#define APIC_INT_LEVELTRIG 0x08000
79#define APIC_INT_ASSERT 0x04000
80#define APIC_ICR_BUSY 0x01000
81#define APIC_DEST_LOGICAL 0x00800
82#define APIC_DEST_PHYSICAL 0x00000
83#define APIC_DM_FIXED 0x00000
84#define APIC_DM_FIXED_MASK 0x00700
85#define APIC_DM_LOWEST 0x00100
86#define APIC_DM_SMI 0x00200
87#define APIC_DM_REMRD 0x00300
88#define APIC_DM_NMI 0x00400
89#define APIC_DM_INIT 0x00500
90#define APIC_DM_STARTUP 0x00600
91#define APIC_DM_EXTINT 0x00700
92#define APIC_VECTOR_MASK 0x000FF
93#define APIC_ICR2 0x310
94#define GET_XAPIC_DEST_FIELD(x) (((x) >> 24) & 0xFF)
95#define SET_XAPIC_DEST_FIELD(x) ((x) << 24)
96#define APIC_LVTT 0x320
97#define APIC_LVTTHMR 0x330
98#define APIC_LVTPC 0x340
99#define APIC_LVT0 0x350
100#define APIC_LVT_TIMER_ONESHOT (0 << 17)
101#define APIC_LVT_TIMER_PERIODIC (1 << 17)
102#define APIC_LVT_TIMER_TSCDEADLINE (2 << 17)
103#define APIC_LVT_MASKED (1 << 16)
104#define APIC_LVT_LEVEL_TRIGGER (1 << 15)
105#define APIC_LVT_REMOTE_IRR (1 << 14)
106#define APIC_INPUT_POLARITY (1 << 13)
107#define APIC_SEND_PENDING (1 << 12)
108#define APIC_MODE_MASK 0x700
109#define GET_APIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7)
110#define SET_APIC_DELIVERY_MODE(x, y) (((x) & ~0x700) | ((y) << 8))
111#define APIC_MODE_FIXED 0x0
112#define APIC_MODE_NMI 0x4
113#define APIC_MODE_EXTINT 0x7
114#define APIC_LVT1 0x360
115#define APIC_LVTERR 0x370
116#define APIC_TMICT 0x380
117#define APIC_TMCCT 0x390
118#define APIC_TDCR 0x3E0
119#define APIC_SELF_IPI 0x3F0
120#define APIC_TDR_DIV_TMBASE (1 << 2)
121#define APIC_TDR_DIV_1 0xB
122#define APIC_TDR_DIV_2 0x0
123#define APIC_TDR_DIV_4 0x1
124#define APIC_TDR_DIV_8 0x2
125#define APIC_TDR_DIV_16 0x3
126#define APIC_TDR_DIV_32 0x8
127#define APIC_TDR_DIV_64 0x9
128#define APIC_TDR_DIV_128 0xA
129#define APIC_EFEAT 0x400
130#define APIC_ECTRL 0x410
131#define APIC_EILVTn(n) (0x500 + 0x10 * n)
132#define APIC_EILVT_NR_AMD_K8 1 /* # of extended interrupts */
133#define APIC_EILVT_NR_AMD_10H 4
134#define APIC_EILVT_NR_MAX APIC_EILVT_NR_AMD_10H
135#define APIC_EILVT_LVTOFF(x) (((x) >> 4) & 0xF)
136#define APIC_EILVT_MSG_FIX 0x0
137#define APIC_EILVT_MSG_SMI 0x2
138#define APIC_EILVT_MSG_NMI 0x4
139#define APIC_EILVT_MSG_EXT 0x7
140#define APIC_EILVT_MASKED (1 << 16)
141
142#define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
143#define APIC_BASE_MSR 0x800
144#define APIC_X2APIC_ID_MSR 0x802
145#define XAPIC_ENABLE BIT(11)
146#define X2APIC_ENABLE BIT(10)
147
148#ifdef CONFIG_X86_32
149# define MAX_IO_APICS 64
150# define MAX_LOCAL_APIC 256
151#else
152# define MAX_IO_APICS 128
153# define MAX_LOCAL_APIC 32768
154#endif
155
156/*
157 * All x86-64 systems are xAPIC compatible.
158 * In the following, "apicid" is a physical APIC ID.
159 */
160#define XAPIC_DEST_CPUS_SHIFT 4
161#define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
162#define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
163#define APIC_CLUSTER(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK)
164#define APIC_CLUSTERID(apicid) (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT)
165#define APIC_CPUID(apicid) ((apicid) & XAPIC_DEST_CPUS_MASK)
166#define NUM_APIC_CLUSTERS ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT)
167
168#ifndef __ASSEMBLY__
169/*
170 * the local APIC register structure, memory mapped. Not terribly well
171 * tested, but we might eventually use this one in the future - the
172 * problem why we cannot use it right now is the P5 APIC, it has an
173 * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
174 */
175#define u32 unsigned int
176
177struct local_apic {
178
179/*000*/ struct { u32 __reserved[4]; } __reserved_01;
180
181/*010*/ struct { u32 __reserved[4]; } __reserved_02;
182
183/*020*/ struct { /* APIC ID Register */
184 u32 __reserved_1 : 24,
185 phys_apic_id : 4,
186 __reserved_2 : 4;
187 u32 __reserved[3];
188 } id;
189
190/*030*/ const
191 struct { /* APIC Version Register */
192 u32 version : 8,
193 __reserved_1 : 8,
194 max_lvt : 8,
195 __reserved_2 : 8;
196 u32 __reserved[3];
197 } version;
198
199/*040*/ struct { u32 __reserved[4]; } __reserved_03;
200
201/*050*/ struct { u32 __reserved[4]; } __reserved_04;
202
203/*060*/ struct { u32 __reserved[4]; } __reserved_05;
204
205/*070*/ struct { u32 __reserved[4]; } __reserved_06;
206
207/*080*/ struct { /* Task Priority Register */
208 u32 priority : 8,
209 __reserved_1 : 24;
210 u32 __reserved_2[3];
211 } tpr;
212
213/*090*/ const
214 struct { /* Arbitration Priority Register */
215 u32 priority : 8,
216 __reserved_1 : 24;
217 u32 __reserved_2[3];
218 } apr;
219
220/*0A0*/ const
221 struct { /* Processor Priority Register */
222 u32 priority : 8,
223 __reserved_1 : 24;
224 u32 __reserved_2[3];
225 } ppr;
226
227/*0B0*/ struct { /* End Of Interrupt Register */
228 u32 eoi;
229 u32 __reserved[3];
230 } eoi;
231
232/*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
233
234/*0D0*/ struct { /* Logical Destination Register */
235 u32 __reserved_1 : 24,
236 logical_dest : 8;
237 u32 __reserved_2[3];
238 } ldr;
239
240/*0E0*/ struct { /* Destination Format Register */
241 u32 __reserved_1 : 28,
242 model : 4;
243 u32 __reserved_2[3];
244 } dfr;
245
246/*0F0*/ struct { /* Spurious Interrupt Vector Register */
247 u32 spurious_vector : 8,
248 apic_enabled : 1,
249 focus_cpu : 1,
250 __reserved_2 : 22;
251 u32 __reserved_3[3];
252 } svr;
253
254/*100*/ struct { /* In Service Register */
255/*170*/ u32 bitfield;
256 u32 __reserved[3];
257 } isr [8];
258
259/*180*/ struct { /* Trigger Mode Register */
260/*1F0*/ u32 bitfield;
261 u32 __reserved[3];
262 } tmr [8];
263
264/*200*/ struct { /* Interrupt Request Register */
265/*270*/ u32 bitfield;
266 u32 __reserved[3];
267 } irr [8];
268
269/*280*/ union { /* Error Status Register */
270 struct {
271 u32 send_cs_error : 1,
272 receive_cs_error : 1,
273 send_accept_error : 1,
274 receive_accept_error : 1,
275 __reserved_1 : 1,
276 send_illegal_vector : 1,
277 receive_illegal_vector : 1,
278 illegal_register_address : 1,
279 __reserved_2 : 24;
280 u32 __reserved_3[3];
281 } error_bits;
282 struct {
283 u32 errors;
284 u32 __reserved_3[3];
285 } all_errors;
286 } esr;
287
288/*290*/ struct { u32 __reserved[4]; } __reserved_08;
289
290/*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
291
292/*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
293
294/*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
295
296/*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
297
298/*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
299
300/*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
301
302/*300*/ struct { /* Interrupt Command Register 1 */
303 u32 vector : 8,
304 delivery_mode : 3,
305 destination_mode : 1,
306 delivery_status : 1,
307 __reserved_1 : 1,
308 level : 1,
309 trigger : 1,
310 __reserved_2 : 2,
311 shorthand : 2,
312 __reserved_3 : 12;
313 u32 __reserved_4[3];
314 } icr1;
315
316/*310*/ struct { /* Interrupt Command Register 2 */
317 union {
318 u32 __reserved_1 : 24,
319 phys_dest : 4,
320 __reserved_2 : 4;
321 u32 __reserved_3 : 24,
322 logical_dest : 8;
323 } dest;
324 u32 __reserved_4[3];
325 } icr2;
326
327/*320*/ struct { /* LVT - Timer */
328 u32 vector : 8,
329 __reserved_1 : 4,
330 delivery_status : 1,
331 __reserved_2 : 3,
332 mask : 1,
333 timer_mode : 1,
334 __reserved_3 : 14;
335 u32 __reserved_4[3];
336 } lvt_timer;
337
338/*330*/ struct { /* LVT - Thermal Sensor */
339 u32 vector : 8,
340 delivery_mode : 3,
341 __reserved_1 : 1,
342 delivery_status : 1,
343 __reserved_2 : 3,
344 mask : 1,
345 __reserved_3 : 15;
346 u32 __reserved_4[3];
347 } lvt_thermal;
348
349/*340*/ struct { /* LVT - Performance Counter */
350 u32 vector : 8,
351 delivery_mode : 3,
352 __reserved_1 : 1,
353 delivery_status : 1,
354 __reserved_2 : 3,
355 mask : 1,
356 __reserved_3 : 15;
357 u32 __reserved_4[3];
358 } lvt_pc;
359
360/*350*/ struct { /* LVT - LINT0 */
361 u32 vector : 8,
362 delivery_mode : 3,
363 __reserved_1 : 1,
364 delivery_status : 1,
365 polarity : 1,
366 remote_irr : 1,
367 trigger : 1,
368 mask : 1,
369 __reserved_2 : 15;
370 u32 __reserved_3[3];
371 } lvt_lint0;
372
373/*360*/ struct { /* LVT - LINT1 */
374 u32 vector : 8,
375 delivery_mode : 3,
376 __reserved_1 : 1,
377 delivery_status : 1,
378 polarity : 1,
379 remote_irr : 1,
380 trigger : 1,
381 mask : 1,
382 __reserved_2 : 15;
383 u32 __reserved_3[3];
384 } lvt_lint1;
385
386/*370*/ struct { /* LVT - Error */
387 u32 vector : 8,
388 __reserved_1 : 4,
389 delivery_status : 1,
390 __reserved_2 : 3,
391 mask : 1,
392 __reserved_3 : 15;
393 u32 __reserved_4[3];
394 } lvt_error;
395
396/*380*/ struct { /* Timer Initial Count Register */
397 u32 initial_count;
398 u32 __reserved_2[3];
399 } timer_icr;
400
401/*390*/ const
402 struct { /* Timer Current Count Register */
403 u32 curr_count;
404 u32 __reserved_2[3];
405 } timer_ccr;
406
407/*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
408
409/*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
410
411/*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
412
413/*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
414
415/*3E0*/ struct { /* Timer Divide Configuration Register */
416 u32 divisor : 4,
417 __reserved_1 : 28;
418 u32 __reserved_2[3];
419 } timer_dcr;
420
421/*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
422
423} __attribute__ ((packed));
424
425#undef u32
426
427#ifdef CONFIG_X86_32
428 #define BAD_APICID 0xFFu
429#else
430 #define BAD_APICID 0xFFFFu
431#endif
432
433enum apic_delivery_modes {
434 APIC_DELIVERY_MODE_FIXED = 0,
435 APIC_DELIVERY_MODE_LOWESTPRIO = 1,
436 APIC_DELIVERY_MODE_SMI = 2,
437 APIC_DELIVERY_MODE_NMI = 4,
438 APIC_DELIVERY_MODE_INIT = 5,
439 APIC_DELIVERY_MODE_EXTINT = 7,
440};
441
442#endif /* !__ASSEMBLY__ */
443#endif /* _ASM_X86_APICDEF_H */
444

source code of linux/arch/x86/include/asm/apicdef.h