1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * imr.h: Isolated Memory Region API |
4 | * |
5 | * Copyright(c) 2013 Intel Corporation. |
6 | * Copyright(c) 2015 Bryan O'Donoghue <pure.logic@nexus-software.ie> |
7 | */ |
8 | #ifndef _IMR_H |
9 | #define _IMR_H |
10 | |
11 | #include <linux/types.h> |
12 | |
13 | /* |
14 | * IMR agent access mask bits |
15 | * See section 12.7.4.7 from quark-x1000-datasheet.pdf for register |
16 | * definitions. |
17 | */ |
18 | #define IMR_ESRAM_FLUSH BIT(31) |
19 | #define IMR_CPU_SNOOP BIT(30) /* Applicable only to write */ |
20 | #define IMR_RMU BIT(29) |
21 | #define IMR_VC1_SAI_ID3 BIT(15) |
22 | #define IMR_VC1_SAI_ID2 BIT(14) |
23 | #define IMR_VC1_SAI_ID1 BIT(13) |
24 | #define IMR_VC1_SAI_ID0 BIT(12) |
25 | #define IMR_VC0_SAI_ID3 BIT(11) |
26 | #define IMR_VC0_SAI_ID2 BIT(10) |
27 | #define IMR_VC0_SAI_ID1 BIT(9) |
28 | #define IMR_VC0_SAI_ID0 BIT(8) |
29 | #define IMR_CPU_0 BIT(1) /* SMM mode */ |
30 | #define IMR_CPU BIT(0) /* Non SMM mode */ |
31 | #define IMR_ACCESS_NONE 0 |
32 | |
33 | /* |
34 | * Read/Write access-all bits here include some reserved bits |
35 | * These are the values firmware uses and are accepted by hardware. |
36 | * The kernel defines read/write access-all in the same way as firmware |
37 | * in order to have a consistent and crisp definition across firmware, |
38 | * bootloader and kernel. |
39 | */ |
40 | #define IMR_READ_ACCESS_ALL 0xBFFFFFFF |
41 | #define IMR_WRITE_ACCESS_ALL 0xFFFFFFFF |
42 | |
43 | /* Number of IMRs provided by Quark X1000 SoC */ |
44 | #define QUARK_X1000_IMR_MAX 0x08 |
45 | #define QUARK_X1000_IMR_REGBASE 0x40 |
46 | |
47 | /* IMR alignment bits - only bits 31:10 are checked for IMR validity */ |
48 | #define IMR_ALIGN 0x400 |
49 | #define IMR_MASK (IMR_ALIGN - 1) |
50 | |
51 | int imr_add_range(phys_addr_t base, size_t size, |
52 | unsigned int rmask, unsigned int wmask); |
53 | |
54 | int imr_remove_range(phys_addr_t base, size_t size); |
55 | |
56 | #endif /* _IMR_H */ |
57 | |