1#ifndef _ASM_X86_INSN_H
2#define _ASM_X86_INSN_H
3/*
4 * x86 instruction analysis
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 *
20 * Copyright (C) IBM Corporation, 2009
21 */
22
23/* insn_attr_t is defined in inat.h */
24#include <asm/inat.h>
25
26struct insn_field {
27 union {
28 insn_value_t value;
29 insn_byte_t bytes[4];
30 };
31 /* !0 if we've run insn_get_xxx() for this field */
32 unsigned char got;
33 unsigned char nbytes;
34};
35
36struct insn {
37 struct insn_field prefixes; /*
38 * Prefixes
39 * prefixes.bytes[3]: last prefix
40 */
41 struct insn_field rex_prefix; /* REX prefix */
42 struct insn_field vex_prefix; /* VEX prefix */
43 struct insn_field opcode; /*
44 * opcode.bytes[0]: opcode1
45 * opcode.bytes[1]: opcode2
46 * opcode.bytes[2]: opcode3
47 */
48 struct insn_field modrm;
49 struct insn_field sib;
50 struct insn_field displacement;
51 union {
52 struct insn_field immediate;
53 struct insn_field moffset1; /* for 64bit MOV */
54 struct insn_field immediate1; /* for 64bit imm or off16/32 */
55 };
56 union {
57 struct insn_field moffset2; /* for 64bit MOV */
58 struct insn_field immediate2; /* for 64bit imm or seg16 */
59 };
60
61 insn_attr_t attr;
62 unsigned char opnd_bytes;
63 unsigned char addr_bytes;
64 unsigned char length;
65 unsigned char x86_64;
66
67 const insn_byte_t *kaddr; /* kernel address of insn to analyze */
68 const insn_byte_t *end_kaddr; /* kernel address of last insn in buffer */
69 const insn_byte_t *next_byte;
70};
71
72#define MAX_INSN_SIZE 15
73
74#define X86_MODRM_MOD(modrm) (((modrm) & 0xc0) >> 6)
75#define X86_MODRM_REG(modrm) (((modrm) & 0x38) >> 3)
76#define X86_MODRM_RM(modrm) ((modrm) & 0x07)
77
78#define X86_SIB_SCALE(sib) (((sib) & 0xc0) >> 6)
79#define X86_SIB_INDEX(sib) (((sib) & 0x38) >> 3)
80#define X86_SIB_BASE(sib) ((sib) & 0x07)
81
82#define X86_REX_W(rex) ((rex) & 8)
83#define X86_REX_R(rex) ((rex) & 4)
84#define X86_REX_X(rex) ((rex) & 2)
85#define X86_REX_B(rex) ((rex) & 1)
86
87/* VEX bit flags */
88#define X86_VEX_W(vex) ((vex) & 0x80) /* VEX3 Byte2 */
89#define X86_VEX_R(vex) ((vex) & 0x80) /* VEX2/3 Byte1 */
90#define X86_VEX_X(vex) ((vex) & 0x40) /* VEX3 Byte1 */
91#define X86_VEX_B(vex) ((vex) & 0x20) /* VEX3 Byte1 */
92#define X86_VEX_L(vex) ((vex) & 0x04) /* VEX3 Byte2, VEX2 Byte1 */
93/* VEX bit fields */
94#define X86_EVEX_M(vex) ((vex) & 0x03) /* EVEX Byte1 */
95#define X86_VEX3_M(vex) ((vex) & 0x1f) /* VEX3 Byte1 */
96#define X86_VEX2_M 1 /* VEX2.M always 1 */
97#define X86_VEX_V(vex) (((vex) & 0x78) >> 3) /* VEX3 Byte2, VEX2 Byte1 */
98#define X86_VEX_P(vex) ((vex) & 0x03) /* VEX3 Byte2, VEX2 Byte1 */
99#define X86_VEX_M_MAX 0x1f /* VEX3.M Maximum value */
100
101extern void insn_init(struct insn *insn, const void *kaddr, int buf_len, int x86_64);
102extern void insn_get_prefixes(struct insn *insn);
103extern void insn_get_opcode(struct insn *insn);
104extern void insn_get_modrm(struct insn *insn);
105extern void insn_get_sib(struct insn *insn);
106extern void insn_get_displacement(struct insn *insn);
107extern void insn_get_immediate(struct insn *insn);
108extern void insn_get_length(struct insn *insn);
109
110/* Attribute will be determined after getting ModRM (for opcode groups) */
111static inline void insn_get_attribute(struct insn *insn)
112{
113 insn_get_modrm(insn);
114}
115
116/* Instruction uses RIP-relative addressing */
117extern int insn_rip_relative(struct insn *insn);
118
119/* Init insn for kernel text */
120static inline void kernel_insn_init(struct insn *insn,
121 const void *kaddr, int buf_len)
122{
123#ifdef CONFIG_X86_64
124 insn_init(insn, kaddr, buf_len, 1);
125#else /* CONFIG_X86_32 */
126 insn_init(insn, kaddr, buf_len, 0);
127#endif
128}
129
130static inline int insn_is_avx(struct insn *insn)
131{
132 if (!insn->prefixes.got)
133 insn_get_prefixes(insn);
134 return (insn->vex_prefix.value != 0);
135}
136
137static inline int insn_is_evex(struct insn *insn)
138{
139 if (!insn->prefixes.got)
140 insn_get_prefixes(insn);
141 return (insn->vex_prefix.nbytes == 4);
142}
143
144/* Ensure this instruction is decoded completely */
145static inline int insn_complete(struct insn *insn)
146{
147 return insn->opcode.got && insn->modrm.got && insn->sib.got &&
148 insn->displacement.got && insn->immediate.got;
149}
150
151static inline insn_byte_t insn_vex_m_bits(struct insn *insn)
152{
153 if (insn->vex_prefix.nbytes == 2) /* 2 bytes VEX */
154 return X86_VEX2_M;
155 else if (insn->vex_prefix.nbytes == 3) /* 3 bytes VEX */
156 return X86_VEX3_M(insn->vex_prefix.bytes[1]);
157 else /* EVEX */
158 return X86_EVEX_M(insn->vex_prefix.bytes[1]);
159}
160
161static inline insn_byte_t insn_vex_p_bits(struct insn *insn)
162{
163 if (insn->vex_prefix.nbytes == 2) /* 2 bytes VEX */
164 return X86_VEX_P(insn->vex_prefix.bytes[1]);
165 else
166 return X86_VEX_P(insn->vex_prefix.bytes[2]);
167}
168
169/* Get the last prefix id from last prefix or VEX prefix */
170static inline int insn_last_prefix_id(struct insn *insn)
171{
172 if (insn_is_avx(insn))
173 return insn_vex_p_bits(insn); /* VEX_p is a SIMD prefix id */
174
175 if (insn->prefixes.bytes[3])
176 return inat_get_last_prefix_id(insn->prefixes.bytes[3]);
177
178 return 0;
179}
180
181/* Offset of each field from kaddr */
182static inline int insn_offset_rex_prefix(struct insn *insn)
183{
184 return insn->prefixes.nbytes;
185}
186static inline int insn_offset_vex_prefix(struct insn *insn)
187{
188 return insn_offset_rex_prefix(insn) + insn->rex_prefix.nbytes;
189}
190static inline int insn_offset_opcode(struct insn *insn)
191{
192 return insn_offset_vex_prefix(insn) + insn->vex_prefix.nbytes;
193}
194static inline int insn_offset_modrm(struct insn *insn)
195{
196 return insn_offset_opcode(insn) + insn->opcode.nbytes;
197}
198static inline int insn_offset_sib(struct insn *insn)
199{
200 return insn_offset_modrm(insn) + insn->modrm.nbytes;
201}
202static inline int insn_offset_displacement(struct insn *insn)
203{
204 return insn_offset_sib(insn) + insn->sib.nbytes;
205}
206static inline int insn_offset_immediate(struct insn *insn)
207{
208 return insn_offset_displacement(insn) + insn->displacement.nbytes;
209}
210
211#define POP_SS_OPCODE 0x1f
212#define MOV_SREG_OPCODE 0x8e
213
214/*
215 * Intel SDM Vol.3A 6.8.3 states;
216 * "Any single-step trap that would be delivered following the MOV to SS
217 * instruction or POP to SS instruction (because EFLAGS.TF is 1) is
218 * suppressed."
219 * This function returns true if @insn is MOV SS or POP SS. On these
220 * instructions, single stepping is suppressed.
221 */
222static inline int insn_masking_exception(struct insn *insn)
223{
224 return insn->opcode.bytes[0] == POP_SS_OPCODE ||
225 (insn->opcode.bytes[0] == MOV_SREG_OPCODE &&
226 X86_MODRM_REG(insn->modrm.bytes[0]) == 2);
227}
228
229#endif /* _ASM_X86_INSN_H */
230