1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | #ifndef _ASM_X86_INTEL_FAMILY_H |
3 | #define _ASM_X86_INTEL_FAMILY_H |
4 | |
5 | /* |
6 | * "Big Core" Processors (Branded as Core, Xeon, etc...) |
7 | * |
8 | * The "_X" parts are generally the EP and EX Xeons, or the |
9 | * "Extreme" ones, like Broadwell-E, or Atom microserver. |
10 | * |
11 | * While adding a new CPUID for a new microarchitecture, add a new |
12 | * group to keep logically sorted out in chronological order. Within |
13 | * that group keep the CPUID for the variants sorted by model number. |
14 | */ |
15 | |
16 | #define INTEL_FAM6_CORE_YONAH 0x0E |
17 | |
18 | #define INTEL_FAM6_CORE2_MEROM 0x0F |
19 | #define INTEL_FAM6_CORE2_MEROM_L 0x16 |
20 | #define INTEL_FAM6_CORE2_PENRYN 0x17 |
21 | #define INTEL_FAM6_CORE2_DUNNINGTON 0x1D |
22 | |
23 | #define INTEL_FAM6_NEHALEM 0x1E |
24 | #define INTEL_FAM6_NEHALEM_G 0x1F /* Auburndale / Havendale */ |
25 | #define INTEL_FAM6_NEHALEM_EP 0x1A |
26 | #define INTEL_FAM6_NEHALEM_EX 0x2E |
27 | |
28 | #define INTEL_FAM6_WESTMERE 0x25 |
29 | #define INTEL_FAM6_WESTMERE_EP 0x2C |
30 | #define INTEL_FAM6_WESTMERE_EX 0x2F |
31 | |
32 | #define INTEL_FAM6_SANDYBRIDGE 0x2A |
33 | #define INTEL_FAM6_SANDYBRIDGE_X 0x2D |
34 | #define INTEL_FAM6_IVYBRIDGE 0x3A |
35 | #define INTEL_FAM6_IVYBRIDGE_X 0x3E |
36 | |
37 | #define INTEL_FAM6_HASWELL_CORE 0x3C |
38 | #define INTEL_FAM6_HASWELL_X 0x3F |
39 | #define INTEL_FAM6_HASWELL_ULT 0x45 |
40 | #define INTEL_FAM6_HASWELL_GT3E 0x46 |
41 | |
42 | #define INTEL_FAM6_BROADWELL_CORE 0x3D |
43 | #define INTEL_FAM6_BROADWELL_GT3E 0x47 |
44 | #define INTEL_FAM6_BROADWELL_X 0x4F |
45 | #define INTEL_FAM6_BROADWELL_XEON_D 0x56 |
46 | |
47 | #define INTEL_FAM6_SKYLAKE_MOBILE 0x4E |
48 | #define INTEL_FAM6_SKYLAKE_DESKTOP 0x5E |
49 | #define INTEL_FAM6_SKYLAKE_X 0x55 |
50 | #define INTEL_FAM6_KABYLAKE_MOBILE 0x8E |
51 | #define INTEL_FAM6_KABYLAKE_DESKTOP 0x9E |
52 | |
53 | #define INTEL_FAM6_CANNONLAKE_MOBILE 0x66 |
54 | |
55 | #define INTEL_FAM6_ICELAKE_MOBILE 0x7E |
56 | |
57 | /* "Small Core" Processors (Atom) */ |
58 | |
59 | #define INTEL_FAM6_ATOM_BONNELL 0x1C /* Diamondville, Pineview */ |
60 | #define INTEL_FAM6_ATOM_BONNELL_MID 0x26 /* Silverthorne, Lincroft */ |
61 | |
62 | #define INTEL_FAM6_ATOM_SALTWELL 0x36 /* Cedarview */ |
63 | #define INTEL_FAM6_ATOM_SALTWELL_MID 0x27 /* Penwell */ |
64 | #define INTEL_FAM6_ATOM_SALTWELL_TABLET 0x35 /* Cloverview */ |
65 | |
66 | #define INTEL_FAM6_ATOM_SILVERMONT 0x37 /* Bay Trail, Valleyview */ |
67 | #define INTEL_FAM6_ATOM_SILVERMONT_X 0x4D /* Avaton, Rangely */ |
68 | #define INTEL_FAM6_ATOM_SILVERMONT_MID 0x4A /* Merriefield */ |
69 | |
70 | #define INTEL_FAM6_ATOM_AIRMONT 0x4C /* Cherry Trail, Braswell */ |
71 | #define INTEL_FAM6_ATOM_AIRMONT_MID 0x5A /* Moorefield */ |
72 | |
73 | #define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */ |
74 | #define INTEL_FAM6_ATOM_GOLDMONT_X 0x5F /* Denverton */ |
75 | #define INTEL_FAM6_ATOM_GOLDMONT_PLUS 0x7A /* Gemini Lake */ |
76 | #define INTEL_FAM6_ATOM_TREMONT_X 0x86 /* Jacobsville */ |
77 | |
78 | /* Xeon Phi */ |
79 | |
80 | #define INTEL_FAM6_XEON_PHI_KNL 0x57 /* Knights Landing */ |
81 | #define INTEL_FAM6_XEON_PHI_KNM 0x85 /* Knights Mill */ |
82 | |
83 | /* Useful macros */ |
84 | #define INTEL_CPU_FAM_ANY(_family, _model, _driver_data) \ |
85 | { \ |
86 | .vendor = X86_VENDOR_INTEL, \ |
87 | .family = _family, \ |
88 | .model = _model, \ |
89 | .feature = X86_FEATURE_ANY, \ |
90 | .driver_data = (kernel_ulong_t)&_driver_data \ |
91 | } |
92 | |
93 | #define INTEL_CPU_FAM6(_model, _driver_data) \ |
94 | INTEL_CPU_FAM_ANY(6, INTEL_FAM6_##_model, _driver_data) |
95 | |
96 | #endif /* _ASM_X86_INTEL_FAMILY_H */ |
97 | |