1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | #ifndef _ASM_X86_IO_APIC_H |
3 | #define _ASM_X86_IO_APIC_H |
4 | |
5 | #include <linux/types.h> |
6 | #include <asm/mpspec.h> |
7 | #include <asm/apicdef.h> |
8 | #include <asm/irq_vectors.h> |
9 | #include <asm/x86_init.h> |
10 | /* |
11 | * Intel IO-APIC support for SMP and UP systems. |
12 | * |
13 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar |
14 | */ |
15 | |
16 | /* I/O Unit Redirection Table */ |
17 | #define IO_APIC_REDIR_VECTOR_MASK 0x000FF |
18 | #define IO_APIC_REDIR_DEST_LOGICAL 0x00800 |
19 | #define IO_APIC_REDIR_DEST_PHYSICAL 0x00000 |
20 | #define IO_APIC_REDIR_SEND_PENDING (1 << 12) |
21 | #define IO_APIC_REDIR_REMOTE_IRR (1 << 14) |
22 | #define IO_APIC_REDIR_LEVEL_TRIGGER (1 << 15) |
23 | #define IO_APIC_REDIR_MASKED (1 << 16) |
24 | |
25 | /* |
26 | * The structure of the IO-APIC: |
27 | */ |
28 | union IO_APIC_reg_00 { |
29 | u32 raw; |
30 | struct { |
31 | u32 __reserved_2 : 14, |
32 | LTS : 1, |
33 | delivery_type : 1, |
34 | __reserved_1 : 8, |
35 | ID : 8; |
36 | } __attribute__ ((packed)) bits; |
37 | }; |
38 | |
39 | union IO_APIC_reg_01 { |
40 | u32 raw; |
41 | struct { |
42 | u32 version : 8, |
43 | __reserved_2 : 7, |
44 | PRQ : 1, |
45 | entries : 8, |
46 | __reserved_1 : 8; |
47 | } __attribute__ ((packed)) bits; |
48 | }; |
49 | |
50 | union IO_APIC_reg_02 { |
51 | u32 raw; |
52 | struct { |
53 | u32 __reserved_2 : 24, |
54 | arbitration : 4, |
55 | __reserved_1 : 4; |
56 | } __attribute__ ((packed)) bits; |
57 | }; |
58 | |
59 | union IO_APIC_reg_03 { |
60 | u32 raw; |
61 | struct { |
62 | u32 boot_DT : 1, |
63 | __reserved_1 : 31; |
64 | } __attribute__ ((packed)) bits; |
65 | }; |
66 | |
67 | struct IO_APIC_route_entry { |
68 | __u32 vector : 8, |
69 | delivery_mode : 3, /* 000: FIXED |
70 | * 001: lowest prio |
71 | * 111: ExtINT |
72 | */ |
73 | dest_mode : 1, /* 0: physical, 1: logical */ |
74 | delivery_status : 1, |
75 | polarity : 1, |
76 | irr : 1, |
77 | trigger : 1, /* 0: edge, 1: level */ |
78 | mask : 1, /* 0: enabled, 1: disabled */ |
79 | __reserved_2 : 15; |
80 | |
81 | __u32 __reserved_3 : 24, |
82 | dest : 8; |
83 | } __attribute__ ((packed)); |
84 | |
85 | struct IR_IO_APIC_route_entry { |
86 | __u64 vector : 8, |
87 | zero : 3, |
88 | index2 : 1, |
89 | delivery_status : 1, |
90 | polarity : 1, |
91 | irr : 1, |
92 | trigger : 1, |
93 | mask : 1, |
94 | reserved : 31, |
95 | format : 1, |
96 | index : 15; |
97 | } __attribute__ ((packed)); |
98 | |
99 | struct irq_alloc_info; |
100 | struct ioapic_domain_cfg; |
101 | |
102 | #define IOAPIC_AUTO -1 |
103 | #define IOAPIC_EDGE 0 |
104 | #define IOAPIC_LEVEL 1 |
105 | |
106 | #define IOAPIC_MASKED 1 |
107 | #define IOAPIC_UNMASKED 0 |
108 | |
109 | #define IOAPIC_POL_HIGH 0 |
110 | #define IOAPIC_POL_LOW 1 |
111 | |
112 | #define IOAPIC_DEST_MODE_PHYSICAL 0 |
113 | #define IOAPIC_DEST_MODE_LOGICAL 1 |
114 | |
115 | #define IOAPIC_MAP_ALLOC 0x1 |
116 | #define IOAPIC_MAP_CHECK 0x2 |
117 | |
118 | #ifdef CONFIG_X86_IO_APIC |
119 | |
120 | /* |
121 | * # of IO-APICs and # of IRQ routing registers |
122 | */ |
123 | extern int nr_ioapics; |
124 | |
125 | extern int mpc_ioapic_id(int ioapic); |
126 | extern unsigned int mpc_ioapic_addr(int ioapic); |
127 | |
128 | /* # of MP IRQ source entries */ |
129 | extern int mp_irq_entries; |
130 | |
131 | /* MP IRQ source entries */ |
132 | extern struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
133 | |
134 | /* 1 if "noapic" boot option passed */ |
135 | extern int skip_ioapic_setup; |
136 | |
137 | /* 1 if "noapic" boot option passed */ |
138 | extern int noioapicquirk; |
139 | |
140 | /* -1 if "noapic" boot option passed */ |
141 | extern int noioapicreroute; |
142 | |
143 | extern u32 gsi_top; |
144 | |
145 | extern unsigned long io_apic_irqs; |
146 | |
147 | #define IO_APIC_IRQ(x) (((x) >= NR_IRQS_LEGACY) || ((1 << (x)) & io_apic_irqs)) |
148 | |
149 | /* |
150 | * If we use the IO-APIC for IRQ routing, disable automatic |
151 | * assignment of PCI IRQ's. |
152 | */ |
153 | #define io_apic_assign_pci_irqs \ |
154 | (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs) |
155 | |
156 | struct irq_cfg; |
157 | extern void ioapic_insert_resources(void); |
158 | extern int arch_early_ioapic_init(void); |
159 | |
160 | extern int save_ioapic_entries(void); |
161 | extern void mask_ioapic_entries(void); |
162 | extern int restore_ioapic_entries(void); |
163 | |
164 | extern void setup_ioapic_ids_from_mpc(void); |
165 | extern void setup_ioapic_ids_from_mpc_nocheck(void); |
166 | |
167 | extern int mp_find_ioapic(u32 gsi); |
168 | extern int mp_find_ioapic_pin(int ioapic, u32 gsi); |
169 | extern int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, |
170 | struct irq_alloc_info *info); |
171 | extern void mp_unmap_irq(int irq); |
172 | extern int mp_register_ioapic(int id, u32 address, u32 gsi_base, |
173 | struct ioapic_domain_cfg *cfg); |
174 | extern int mp_unregister_ioapic(u32 gsi_base); |
175 | extern int mp_ioapic_registered(u32 gsi_base); |
176 | |
177 | extern void ioapic_set_alloc_attr(struct irq_alloc_info *info, |
178 | int node, int trigger, int polarity); |
179 | |
180 | extern void mp_save_irq(struct mpc_intsrc *m); |
181 | |
182 | extern void disable_ioapic_support(void); |
183 | |
184 | extern void __init io_apic_init_mappings(void); |
185 | extern unsigned int native_io_apic_read(unsigned int apic, unsigned int reg); |
186 | extern void native_restore_boot_irq_mode(void); |
187 | |
188 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) |
189 | { |
190 | return x86_apic_ops.io_apic_read(apic, reg); |
191 | } |
192 | |
193 | extern void setup_IO_APIC(void); |
194 | extern void enable_IO_APIC(void); |
195 | extern void clear_IO_APIC(void); |
196 | extern void restore_boot_irq_mode(void); |
197 | extern int IO_APIC_get_PCI_irq_vector(int bus, int devfn, int pin); |
198 | extern void print_IO_APICs(void); |
199 | #else /* !CONFIG_X86_IO_APIC */ |
200 | |
201 | #define IO_APIC_IRQ(x) 0 |
202 | #define io_apic_assign_pci_irqs 0 |
203 | #define setup_ioapic_ids_from_mpc x86_init_noop |
204 | static inline void ioapic_insert_resources(void) { } |
205 | static inline int arch_early_ioapic_init(void) { return 0; } |
206 | static inline void print_IO_APICs(void) {} |
207 | #define gsi_top (NR_IRQS_LEGACY) |
208 | static inline int mp_find_ioapic(u32 gsi) { return 0; } |
209 | static inline int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, |
210 | struct irq_alloc_info *info) |
211 | { |
212 | return gsi; |
213 | } |
214 | |
215 | static inline void mp_unmap_irq(int irq) { } |
216 | |
217 | static inline int save_ioapic_entries(void) |
218 | { |
219 | return -ENOMEM; |
220 | } |
221 | |
222 | static inline void mask_ioapic_entries(void) { } |
223 | static inline int restore_ioapic_entries(void) |
224 | { |
225 | return -ENOMEM; |
226 | } |
227 | |
228 | static inline void mp_save_irq(struct mpc_intsrc *m) { } |
229 | static inline void disable_ioapic_support(void) { } |
230 | static inline void io_apic_init_mappings(void) { } |
231 | #define native_io_apic_read NULL |
232 | #define native_restore_boot_irq_mode NULL |
233 | |
234 | static inline void setup_IO_APIC(void) { } |
235 | static inline void enable_IO_APIC(void) { } |
236 | static inline void restore_boot_irq_mode(void) { } |
237 | |
238 | #endif |
239 | |
240 | #endif /* _ASM_X86_IO_APIC_H */ |
241 | |