1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | #ifndef _ASM_X86_MSR_INDEX_H |
3 | #define _ASM_X86_MSR_INDEX_H |
4 | |
5 | #include <linux/bits.h> |
6 | |
7 | /* CPU model specific register (MSR) numbers. */ |
8 | |
9 | /* x86-64 specific MSRs */ |
10 | #define MSR_EFER 0xc0000080 /* extended feature register */ |
11 | #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ |
12 | #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ |
13 | #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ |
14 | #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ |
15 | #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ |
16 | #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ |
17 | #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ |
18 | #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ |
19 | |
20 | /* EFER bits: */ |
21 | #define _EFER_SCE 0 /* SYSCALL/SYSRET */ |
22 | #define _EFER_LME 8 /* Long mode enable */ |
23 | #define _EFER_LMA 10 /* Long mode active (read-only) */ |
24 | #define _EFER_NX 11 /* No execute enable */ |
25 | #define _EFER_SVME 12 /* Enable virtualization */ |
26 | #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ |
27 | #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ |
28 | #define _EFER_AUTOIBRS 21 /* Enable Automatic IBRS */ |
29 | |
30 | #define EFER_SCE (1<<_EFER_SCE) |
31 | #define EFER_LME (1<<_EFER_LME) |
32 | #define EFER_LMA (1<<_EFER_LMA) |
33 | #define EFER_NX (1<<_EFER_NX) |
34 | #define EFER_SVME (1<<_EFER_SVME) |
35 | #define EFER_LMSLE (1<<_EFER_LMSLE) |
36 | #define EFER_FFXSR (1<<_EFER_FFXSR) |
37 | #define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS) |
38 | |
39 | /* Intel MSRs. Some also available on other CPUs */ |
40 | |
41 | #define MSR_TEST_CTRL 0x00000033 |
42 | #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29 |
43 | #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT) |
44 | |
45 | #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ |
46 | #define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */ |
47 | #define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ |
48 | #define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */ |
49 | #define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */ |
50 | #define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ |
51 | #define SPEC_CTRL_RRSBA_DIS_S_SHIFT 6 /* Disable RRSBA behavior */ |
52 | #define SPEC_CTRL_RRSBA_DIS_S BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT) |
53 | |
54 | /* A mask for bits which the kernel toggles when controlling mitigations */ |
55 | #define SPEC_CTRL_MITIGATIONS_MASK (SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD \ |
56 | | SPEC_CTRL_RRSBA_DIS_S) |
57 | |
58 | #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ |
59 | #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */ |
60 | #define PRED_CMD_SBPB BIT(7) /* Selective Branch Prediction Barrier */ |
61 | |
62 | #define MSR_PPIN_CTL 0x0000004e |
63 | #define MSR_PPIN 0x0000004f |
64 | |
65 | #define MSR_IA32_PERFCTR0 0x000000c1 |
66 | #define MSR_IA32_PERFCTR1 0x000000c2 |
67 | #define MSR_FSB_FREQ 0x000000cd |
68 | #define MSR_PLATFORM_INFO 0x000000ce |
69 | #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 |
70 | #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) |
71 | |
72 | #define MSR_IA32_UMWAIT_CONTROL 0xe1 |
73 | #define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0) |
74 | #define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1) |
75 | /* |
76 | * The time field is bit[31:2], but representing a 32bit value with |
77 | * bit[1:0] zero. |
78 | */ |
79 | #define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U) |
80 | |
81 | /* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */ |
82 | #define MSR_IA32_CORE_CAPS 0x000000cf |
83 | #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT 2 |
84 | #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS BIT(MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT) |
85 | #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5 |
86 | #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT) |
87 | |
88 | #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 |
89 | #define NHM_C3_AUTO_DEMOTE (1UL << 25) |
90 | #define NHM_C1_AUTO_DEMOTE (1UL << 26) |
91 | #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) |
92 | #define SNB_C3_AUTO_UNDEMOTE (1UL << 27) |
93 | #define SNB_C1_AUTO_UNDEMOTE (1UL << 28) |
94 | |
95 | #define MSR_MTRRcap 0x000000fe |
96 | |
97 | #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a |
98 | #define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */ |
99 | #define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */ |
100 | #define ARCH_CAP_RSBA BIT(2) /* RET may use alternative branch predictors */ |
101 | #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */ |
102 | #define ARCH_CAP_SSB_NO BIT(4) /* |
103 | * Not susceptible to Speculative Store Bypass |
104 | * attack, so no Speculative Store Bypass |
105 | * control required. |
106 | */ |
107 | #define ARCH_CAP_MDS_NO BIT(5) /* |
108 | * Not susceptible to |
109 | * Microarchitectural Data |
110 | * Sampling (MDS) vulnerabilities. |
111 | */ |
112 | #define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /* |
113 | * The processor is not susceptible to a |
114 | * machine check error due to modifying the |
115 | * code page size along with either the |
116 | * physical address or cache type |
117 | * without TLB invalidation. |
118 | */ |
119 | #define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */ |
120 | #define ARCH_CAP_TAA_NO BIT(8) /* |
121 | * Not susceptible to |
122 | * TSX Async Abort (TAA) vulnerabilities. |
123 | */ |
124 | #define ARCH_CAP_SBDR_SSDP_NO BIT(13) /* |
125 | * Not susceptible to SBDR and SSDP |
126 | * variants of Processor MMIO stale data |
127 | * vulnerabilities. |
128 | */ |
129 | #define ARCH_CAP_FBSDP_NO BIT(14) /* |
130 | * Not susceptible to FBSDP variant of |
131 | * Processor MMIO stale data |
132 | * vulnerabilities. |
133 | */ |
134 | #define ARCH_CAP_PSDP_NO BIT(15) /* |
135 | * Not susceptible to PSDP variant of |
136 | * Processor MMIO stale data |
137 | * vulnerabilities. |
138 | */ |
139 | #define ARCH_CAP_FB_CLEAR BIT(17) /* |
140 | * VERW clears CPU fill buffer |
141 | * even on MDS_NO CPUs. |
142 | */ |
143 | #define ARCH_CAP_FB_CLEAR_CTRL BIT(18) /* |
144 | * MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS] |
145 | * bit available to control VERW |
146 | * behavior. |
147 | */ |
148 | #define ARCH_CAP_RRSBA BIT(19) /* |
149 | * Indicates RET may use predictors |
150 | * other than the RSB. With eIBRS |
151 | * enabled predictions in kernel mode |
152 | * are restricted to targets in |
153 | * kernel. |
154 | */ |
155 | #define ARCH_CAP_PBRSB_NO BIT(24) /* |
156 | * Not susceptible to Post-Barrier |
157 | * Return Stack Buffer Predictions. |
158 | */ |
159 | #define ARCH_CAP_GDS_CTRL BIT(25) /* |
160 | * CPU is vulnerable to Gather |
161 | * Data Sampling (GDS) and |
162 | * has controls for mitigation. |
163 | */ |
164 | #define ARCH_CAP_GDS_NO BIT(26) /* |
165 | * CPU is not vulnerable to Gather |
166 | * Data Sampling (GDS). |
167 | */ |
168 | |
169 | #define ARCH_CAP_XAPIC_DISABLE BIT(21) /* |
170 | * IA32_XAPIC_DISABLE_STATUS MSR |
171 | * supported |
172 | */ |
173 | |
174 | #define MSR_IA32_FLUSH_CMD 0x0000010b |
175 | #define L1D_FLUSH BIT(0) /* |
176 | * Writeback and invalidate the |
177 | * L1 data cache. |
178 | */ |
179 | |
180 | #define MSR_IA32_BBL_CR_CTL 0x00000119 |
181 | #define MSR_IA32_BBL_CR_CTL3 0x0000011e |
182 | |
183 | #define MSR_IA32_TSX_CTRL 0x00000122 |
184 | #define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */ |
185 | #define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */ |
186 | |
187 | #define MSR_IA32_MCU_OPT_CTRL 0x00000123 |
188 | #define RNGDS_MITG_DIS BIT(0) /* SRBDS support */ |
189 | #define RTM_ALLOW BIT(1) /* TSX development mode */ |
190 | #define FB_CLEAR_DIS BIT(3) /* CPU Fill buffer clear disable */ |
191 | #define GDS_MITG_DIS BIT(4) /* Disable GDS mitigation */ |
192 | #define GDS_MITG_LOCKED BIT(5) /* GDS mitigation locked */ |
193 | |
194 | #define MSR_IA32_SYSENTER_CS 0x00000174 |
195 | #define MSR_IA32_SYSENTER_ESP 0x00000175 |
196 | #define MSR_IA32_SYSENTER_EIP 0x00000176 |
197 | |
198 | #define MSR_IA32_MCG_CAP 0x00000179 |
199 | #define MSR_IA32_MCG_STATUS 0x0000017a |
200 | #define MSR_IA32_MCG_CTL 0x0000017b |
201 | #define MSR_ERROR_CONTROL 0x0000017f |
202 | #define MSR_IA32_MCG_EXT_CTL 0x000004d0 |
203 | |
204 | #define MSR_OFFCORE_RSP_0 0x000001a6 |
205 | #define MSR_OFFCORE_RSP_1 0x000001a7 |
206 | #define MSR_TURBO_RATIO_LIMIT 0x000001ad |
207 | #define MSR_TURBO_RATIO_LIMIT1 0x000001ae |
208 | #define MSR_TURBO_RATIO_LIMIT2 0x000001af |
209 | |
210 | #define MSR_SNOOP_RSP_0 0x00001328 |
211 | #define MSR_SNOOP_RSP_1 0x00001329 |
212 | |
213 | #define MSR_LBR_SELECT 0x000001c8 |
214 | #define MSR_LBR_TOS 0x000001c9 |
215 | |
216 | #define MSR_IA32_POWER_CTL 0x000001fc |
217 | #define MSR_IA32_POWER_CTL_BIT_EE 19 |
218 | |
219 | /* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */ |
220 | #define MSR_INTEGRITY_CAPS 0x000002d9 |
221 | #define MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT 2 |
222 | #define MSR_INTEGRITY_CAPS_ARRAY_BIST BIT(MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT) |
223 | #define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT 4 |
224 | #define MSR_INTEGRITY_CAPS_PERIODIC_BIST BIT(MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT) |
225 | #define MSR_INTEGRITY_CAPS_SAF_GEN_MASK GENMASK_ULL(10, 9) |
226 | |
227 | #define MSR_LBR_NHM_FROM 0x00000680 |
228 | #define MSR_LBR_NHM_TO 0x000006c0 |
229 | #define MSR_LBR_CORE_FROM 0x00000040 |
230 | #define MSR_LBR_CORE_TO 0x00000060 |
231 | |
232 | #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ |
233 | #define LBR_INFO_MISPRED BIT_ULL(63) |
234 | #define LBR_INFO_IN_TX BIT_ULL(62) |
235 | #define LBR_INFO_ABORT BIT_ULL(61) |
236 | #define LBR_INFO_CYC_CNT_VALID BIT_ULL(60) |
237 | #define LBR_INFO_CYCLES 0xffff |
238 | #define LBR_INFO_BR_TYPE_OFFSET 56 |
239 | #define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET) |
240 | |
241 | #define MSR_ARCH_LBR_CTL 0x000014ce |
242 | #define ARCH_LBR_CTL_LBREN BIT(0) |
243 | #define ARCH_LBR_CTL_CPL_OFFSET 1 |
244 | #define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET) |
245 | #define ARCH_LBR_CTL_STACK_OFFSET 3 |
246 | #define ARCH_LBR_CTL_STACK (0x1ull << ARCH_LBR_CTL_STACK_OFFSET) |
247 | #define ARCH_LBR_CTL_FILTER_OFFSET 16 |
248 | #define ARCH_LBR_CTL_FILTER (0x7full << ARCH_LBR_CTL_FILTER_OFFSET) |
249 | #define MSR_ARCH_LBR_DEPTH 0x000014cf |
250 | #define MSR_ARCH_LBR_FROM_0 0x00001500 |
251 | #define MSR_ARCH_LBR_TO_0 0x00001600 |
252 | #define MSR_ARCH_LBR_INFO_0 0x00001200 |
253 | |
254 | #define MSR_IA32_PEBS_ENABLE 0x000003f1 |
255 | #define MSR_PEBS_DATA_CFG 0x000003f2 |
256 | #define MSR_IA32_DS_AREA 0x00000600 |
257 | #define MSR_IA32_PERF_CAPABILITIES 0x00000345 |
258 | #define PERF_CAP_METRICS_IDX 15 |
259 | #define PERF_CAP_PT_IDX 16 |
260 | |
261 | #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 |
262 | #define PERF_CAP_PEBS_TRAP BIT_ULL(6) |
263 | #define PERF_CAP_ARCH_REG BIT_ULL(7) |
264 | #define PERF_CAP_PEBS_FORMAT 0xf00 |
265 | #define PERF_CAP_PEBS_BASELINE BIT_ULL(14) |
266 | #define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \ |
267 | PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE) |
268 | |
269 | #define MSR_IA32_RTIT_CTL 0x00000570 |
270 | #define RTIT_CTL_TRACEEN BIT(0) |
271 | #define RTIT_CTL_CYCLEACC BIT(1) |
272 | #define RTIT_CTL_OS BIT(2) |
273 | #define RTIT_CTL_USR BIT(3) |
274 | #define RTIT_CTL_PWR_EVT_EN BIT(4) |
275 | #define RTIT_CTL_FUP_ON_PTW BIT(5) |
276 | #define RTIT_CTL_FABRIC_EN BIT(6) |
277 | #define RTIT_CTL_CR3EN BIT(7) |
278 | #define RTIT_CTL_TOPA BIT(8) |
279 | #define RTIT_CTL_MTC_EN BIT(9) |
280 | #define RTIT_CTL_TSC_EN BIT(10) |
281 | #define RTIT_CTL_DISRETC BIT(11) |
282 | #define RTIT_CTL_PTW_EN BIT(12) |
283 | #define RTIT_CTL_BRANCH_EN BIT(13) |
284 | #define RTIT_CTL_EVENT_EN BIT(31) |
285 | #define RTIT_CTL_NOTNT BIT_ULL(55) |
286 | #define RTIT_CTL_MTC_RANGE_OFFSET 14 |
287 | #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) |
288 | #define RTIT_CTL_CYC_THRESH_OFFSET 19 |
289 | #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) |
290 | #define RTIT_CTL_PSB_FREQ_OFFSET 24 |
291 | #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) |
292 | #define RTIT_CTL_ADDR0_OFFSET 32 |
293 | #define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET) |
294 | #define RTIT_CTL_ADDR1_OFFSET 36 |
295 | #define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET) |
296 | #define RTIT_CTL_ADDR2_OFFSET 40 |
297 | #define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET) |
298 | #define RTIT_CTL_ADDR3_OFFSET 44 |
299 | #define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET) |
300 | #define MSR_IA32_RTIT_STATUS 0x00000571 |
301 | #define RTIT_STATUS_FILTEREN BIT(0) |
302 | #define RTIT_STATUS_CONTEXTEN BIT(1) |
303 | #define RTIT_STATUS_TRIGGEREN BIT(2) |
304 | #define RTIT_STATUS_BUFFOVF BIT(3) |
305 | #define RTIT_STATUS_ERROR BIT(4) |
306 | #define RTIT_STATUS_STOPPED BIT(5) |
307 | #define RTIT_STATUS_BYTECNT_OFFSET 32 |
308 | #define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET) |
309 | #define MSR_IA32_RTIT_ADDR0_A 0x00000580 |
310 | #define MSR_IA32_RTIT_ADDR0_B 0x00000581 |
311 | #define MSR_IA32_RTIT_ADDR1_A 0x00000582 |
312 | #define MSR_IA32_RTIT_ADDR1_B 0x00000583 |
313 | #define MSR_IA32_RTIT_ADDR2_A 0x00000584 |
314 | #define MSR_IA32_RTIT_ADDR2_B 0x00000585 |
315 | #define MSR_IA32_RTIT_ADDR3_A 0x00000586 |
316 | #define MSR_IA32_RTIT_ADDR3_B 0x00000587 |
317 | #define MSR_IA32_RTIT_CR3_MATCH 0x00000572 |
318 | #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 |
319 | #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 |
320 | |
321 | #define MSR_MTRRfix64K_00000 0x00000250 |
322 | #define MSR_MTRRfix16K_80000 0x00000258 |
323 | #define MSR_MTRRfix16K_A0000 0x00000259 |
324 | #define MSR_MTRRfix4K_C0000 0x00000268 |
325 | #define MSR_MTRRfix4K_C8000 0x00000269 |
326 | #define MSR_MTRRfix4K_D0000 0x0000026a |
327 | #define MSR_MTRRfix4K_D8000 0x0000026b |
328 | #define MSR_MTRRfix4K_E0000 0x0000026c |
329 | #define MSR_MTRRfix4K_E8000 0x0000026d |
330 | #define MSR_MTRRfix4K_F0000 0x0000026e |
331 | #define MSR_MTRRfix4K_F8000 0x0000026f |
332 | #define MSR_MTRRdefType 0x000002ff |
333 | |
334 | #define MSR_IA32_CR_PAT 0x00000277 |
335 | |
336 | #define MSR_IA32_DEBUGCTLMSR 0x000001d9 |
337 | #define MSR_IA32_LASTBRANCHFROMIP 0x000001db |
338 | #define MSR_IA32_LASTBRANCHTOIP 0x000001dc |
339 | #define MSR_IA32_LASTINTFROMIP 0x000001dd |
340 | #define MSR_IA32_LASTINTTOIP 0x000001de |
341 | |
342 | #define MSR_IA32_PASID 0x00000d93 |
343 | #define MSR_IA32_PASID_VALID BIT_ULL(31) |
344 | |
345 | /* DEBUGCTLMSR bits (others vary by model): */ |
346 | #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ |
347 | #define DEBUGCTLMSR_BTF_SHIFT 1 |
348 | #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ |
349 | #define DEBUGCTLMSR_BUS_LOCK_DETECT (1UL << 2) |
350 | #define DEBUGCTLMSR_TR (1UL << 6) |
351 | #define DEBUGCTLMSR_BTS (1UL << 7) |
352 | #define DEBUGCTLMSR_BTINT (1UL << 8) |
353 | #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) |
354 | #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) |
355 | #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) |
356 | #define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12) |
357 | #define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14 |
358 | #define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT) |
359 | |
360 | #define MSR_PEBS_FRONTEND 0x000003f7 |
361 | |
362 | #define MSR_IA32_MC0_CTL 0x00000400 |
363 | #define MSR_IA32_MC0_STATUS 0x00000401 |
364 | #define MSR_IA32_MC0_ADDR 0x00000402 |
365 | #define MSR_IA32_MC0_MISC 0x00000403 |
366 | |
367 | /* C-state Residency Counters */ |
368 | #define MSR_PKG_C3_RESIDENCY 0x000003f8 |
369 | #define MSR_PKG_C6_RESIDENCY 0x000003f9 |
370 | #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa |
371 | #define MSR_PKG_C7_RESIDENCY 0x000003fa |
372 | #define MSR_CORE_C3_RESIDENCY 0x000003fc |
373 | #define MSR_CORE_C6_RESIDENCY 0x000003fd |
374 | #define MSR_CORE_C7_RESIDENCY 0x000003fe |
375 | #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff |
376 | #define MSR_PKG_C2_RESIDENCY 0x0000060d |
377 | #define MSR_PKG_C8_RESIDENCY 0x00000630 |
378 | #define MSR_PKG_C9_RESIDENCY 0x00000631 |
379 | #define MSR_PKG_C10_RESIDENCY 0x00000632 |
380 | |
381 | /* Interrupt Response Limit */ |
382 | #define MSR_PKGC3_IRTL 0x0000060a |
383 | #define MSR_PKGC6_IRTL 0x0000060b |
384 | #define MSR_PKGC7_IRTL 0x0000060c |
385 | #define MSR_PKGC8_IRTL 0x00000633 |
386 | #define MSR_PKGC9_IRTL 0x00000634 |
387 | #define MSR_PKGC10_IRTL 0x00000635 |
388 | |
389 | /* Run Time Average Power Limiting (RAPL) Interface */ |
390 | |
391 | #define MSR_VR_CURRENT_CONFIG 0x00000601 |
392 | #define MSR_RAPL_POWER_UNIT 0x00000606 |
393 | |
394 | #define MSR_PKG_POWER_LIMIT 0x00000610 |
395 | #define MSR_PKG_ENERGY_STATUS 0x00000611 |
396 | #define MSR_PKG_PERF_STATUS 0x00000613 |
397 | #define MSR_PKG_POWER_INFO 0x00000614 |
398 | |
399 | #define MSR_DRAM_POWER_LIMIT 0x00000618 |
400 | #define MSR_DRAM_ENERGY_STATUS 0x00000619 |
401 | #define MSR_DRAM_PERF_STATUS 0x0000061b |
402 | #define MSR_DRAM_POWER_INFO 0x0000061c |
403 | |
404 | #define MSR_PP0_POWER_LIMIT 0x00000638 |
405 | #define MSR_PP0_ENERGY_STATUS 0x00000639 |
406 | #define MSR_PP0_POLICY 0x0000063a |
407 | #define MSR_PP0_PERF_STATUS 0x0000063b |
408 | |
409 | #define MSR_PP1_POWER_LIMIT 0x00000640 |
410 | #define MSR_PP1_ENERGY_STATUS 0x00000641 |
411 | #define MSR_PP1_POLICY 0x00000642 |
412 | |
413 | #define MSR_AMD_RAPL_POWER_UNIT 0xc0010299 |
414 | #define MSR_AMD_CORE_ENERGY_STATUS 0xc001029a |
415 | #define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b |
416 | |
417 | /* Config TDP MSRs */ |
418 | #define MSR_CONFIG_TDP_NOMINAL 0x00000648 |
419 | #define MSR_CONFIG_TDP_LEVEL_1 0x00000649 |
420 | #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A |
421 | #define MSR_CONFIG_TDP_CONTROL 0x0000064B |
422 | #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C |
423 | |
424 | #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D |
425 | #define MSR_SECONDARY_TURBO_RATIO_LIMIT 0x00000650 |
426 | |
427 | #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 |
428 | #define MSR_PKG_ANY_CORE_C0_RES 0x00000659 |
429 | #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A |
430 | #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B |
431 | |
432 | #define MSR_CORE_C1_RES 0x00000660 |
433 | #define MSR_MODULE_C6_RES_MS 0x00000664 |
434 | |
435 | #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 |
436 | #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 |
437 | |
438 | #define MSR_ATOM_CORE_RATIOS 0x0000066a |
439 | #define MSR_ATOM_CORE_VIDS 0x0000066b |
440 | #define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c |
441 | #define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d |
442 | |
443 | #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 |
444 | #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 |
445 | #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 |
446 | |
447 | /* Control-flow Enforcement Technology MSRs */ |
448 | #define MSR_IA32_U_CET 0x000006a0 /* user mode cet */ |
449 | #define MSR_IA32_S_CET 0x000006a2 /* kernel mode cet */ |
450 | #define CET_SHSTK_EN BIT_ULL(0) |
451 | #define BIT_ULL(1) |
452 | #define CET_ENDBR_EN BIT_ULL(2) |
453 | #define CET_LEG_IW_EN BIT_ULL(3) |
454 | #define CET_NO_TRACK_EN BIT_ULL(4) |
455 | #define CET_SUPPRESS_DISABLE BIT_ULL(5) |
456 | #define CET_RESERVED (BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9)) |
457 | #define CET_SUPPRESS BIT_ULL(10) |
458 | #define CET_WAIT_ENDBR BIT_ULL(11) |
459 | |
460 | #define MSR_IA32_PL0_SSP 0x000006a4 /* ring-0 shadow stack pointer */ |
461 | #define MSR_IA32_PL1_SSP 0x000006a5 /* ring-1 shadow stack pointer */ |
462 | #define MSR_IA32_PL2_SSP 0x000006a6 /* ring-2 shadow stack pointer */ |
463 | #define MSR_IA32_PL3_SSP 0x000006a7 /* ring-3 shadow stack pointer */ |
464 | #define MSR_IA32_INT_SSP_TAB 0x000006a8 /* exception shadow stack table */ |
465 | |
466 | /* Hardware P state interface */ |
467 | #define MSR_PPERF 0x0000064e |
468 | #define MSR_PERF_LIMIT_REASONS 0x0000064f |
469 | #define MSR_PM_ENABLE 0x00000770 |
470 | #define MSR_HWP_CAPABILITIES 0x00000771 |
471 | #define MSR_HWP_REQUEST_PKG 0x00000772 |
472 | #define MSR_HWP_INTERRUPT 0x00000773 |
473 | #define MSR_HWP_REQUEST 0x00000774 |
474 | #define MSR_HWP_STATUS 0x00000777 |
475 | |
476 | /* CPUID.6.EAX */ |
477 | #define HWP_BASE_BIT (1<<7) |
478 | #define HWP_NOTIFICATIONS_BIT (1<<8) |
479 | #define HWP_ACTIVITY_WINDOW_BIT (1<<9) |
480 | #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) |
481 | #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) |
482 | |
483 | /* IA32_HWP_CAPABILITIES */ |
484 | #define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff) |
485 | #define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff) |
486 | #define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff) |
487 | #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) |
488 | |
489 | /* IA32_HWP_REQUEST */ |
490 | #define HWP_MIN_PERF(x) (x & 0xff) |
491 | #define HWP_MAX_PERF(x) ((x & 0xff) << 8) |
492 | #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) |
493 | #define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24) |
494 | #define HWP_EPP_PERFORMANCE 0x00 |
495 | #define HWP_EPP_BALANCE_PERFORMANCE 0x80 |
496 | #define HWP_EPP_BALANCE_POWERSAVE 0xC0 |
497 | #define HWP_EPP_POWERSAVE 0xFF |
498 | #define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32) |
499 | #define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42) |
500 | |
501 | /* IA32_HWP_STATUS */ |
502 | #define HWP_GUARANTEED_CHANGE(x) (x & 0x1) |
503 | #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) |
504 | |
505 | /* IA32_HWP_INTERRUPT */ |
506 | #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) |
507 | #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) |
508 | |
509 | #define MSR_AMD64_MC0_MASK 0xc0010044 |
510 | |
511 | #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) |
512 | #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) |
513 | #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) |
514 | #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) |
515 | |
516 | #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) |
517 | |
518 | /* These are consecutive and not in the normal 4er MCE bank block */ |
519 | #define MSR_IA32_MC0_CTL2 0x00000280 |
520 | #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) |
521 | |
522 | #define MSR_P6_PERFCTR0 0x000000c1 |
523 | #define MSR_P6_PERFCTR1 0x000000c2 |
524 | #define MSR_P6_EVNTSEL0 0x00000186 |
525 | #define MSR_P6_EVNTSEL1 0x00000187 |
526 | |
527 | #define MSR_KNC_PERFCTR0 0x00000020 |
528 | #define MSR_KNC_PERFCTR1 0x00000021 |
529 | #define MSR_KNC_EVNTSEL0 0x00000028 |
530 | #define MSR_KNC_EVNTSEL1 0x00000029 |
531 | |
532 | /* Alternative perfctr range with full access. */ |
533 | #define MSR_IA32_PMC0 0x000004c1 |
534 | |
535 | /* Auto-reload via MSR instead of DS area */ |
536 | #define MSR_RELOAD_PMC0 0x000014c1 |
537 | #define MSR_RELOAD_FIXED_CTR0 0x00001309 |
538 | |
539 | /* |
540 | * AMD64 MSRs. Not complete. See the architecture manual for a more |
541 | * complete list. |
542 | */ |
543 | #define MSR_AMD64_PATCH_LEVEL 0x0000008b |
544 | #define MSR_AMD64_TSC_RATIO 0xc0000104 |
545 | #define MSR_AMD64_NB_CFG 0xc001001f |
546 | #define MSR_AMD64_PATCH_LOADER 0xc0010020 |
547 | #define MSR_AMD_PERF_CTL 0xc0010062 |
548 | #define MSR_AMD_PERF_STATUS 0xc0010063 |
549 | #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 |
550 | #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 |
551 | #define MSR_AMD64_OSVW_STATUS 0xc0010141 |
552 | #define MSR_AMD_PPIN_CTL 0xc00102f0 |
553 | #define MSR_AMD_PPIN 0xc00102f1 |
554 | #define MSR_AMD64_CPUID_FN_1 0xc0011004 |
555 | #define MSR_AMD64_LS_CFG 0xc0011020 |
556 | #define MSR_AMD64_DC_CFG 0xc0011022 |
557 | #define MSR_AMD64_TW_CFG 0xc0011023 |
558 | |
559 | #define MSR_AMD64_DE_CFG 0xc0011029 |
560 | #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1 |
561 | #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT) |
562 | #define MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT 9 |
563 | |
564 | #define MSR_AMD64_BU_CFG2 0xc001102a |
565 | #define MSR_AMD64_IBSFETCHCTL 0xc0011030 |
566 | #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 |
567 | #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 |
568 | #define MSR_AMD64_IBSFETCH_REG_COUNT 3 |
569 | #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) |
570 | #define MSR_AMD64_IBSOPCTL 0xc0011033 |
571 | #define MSR_AMD64_IBSOPRIP 0xc0011034 |
572 | #define MSR_AMD64_IBSOPDATA 0xc0011035 |
573 | #define MSR_AMD64_IBSOPDATA2 0xc0011036 |
574 | #define MSR_AMD64_IBSOPDATA3 0xc0011037 |
575 | #define MSR_AMD64_IBSDCLINAD 0xc0011038 |
576 | #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 |
577 | #define MSR_AMD64_IBSOP_REG_COUNT 7 |
578 | #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) |
579 | #define MSR_AMD64_IBSCTL 0xc001103a |
580 | #define MSR_AMD64_IBSBRTARGET 0xc001103b |
581 | #define MSR_AMD64_ICIBSEXTDCTL 0xc001103c |
582 | #define MSR_AMD64_IBSOPDATA4 0xc001103d |
583 | #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ |
584 | #define MSR_AMD64_SVM_AVIC_DOORBELL 0xc001011b |
585 | #define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e |
586 | #define MSR_AMD64_SEV_ES_GHCB 0xc0010130 |
587 | #define MSR_AMD64_SEV 0xc0010131 |
588 | #define MSR_AMD64_SEV_ENABLED_BIT 0 |
589 | #define MSR_AMD64_SEV_ES_ENABLED_BIT 1 |
590 | #define MSR_AMD64_SEV_SNP_ENABLED_BIT 2 |
591 | #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) |
592 | #define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) |
593 | #define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT) |
594 | |
595 | /* SNP feature bits enabled by the hypervisor */ |
596 | #define MSR_AMD64_SNP_VTOM BIT_ULL(3) |
597 | #define MSR_AMD64_SNP_REFLECT_VC BIT_ULL(4) |
598 | #define MSR_AMD64_SNP_RESTRICTED_INJ BIT_ULL(5) |
599 | #define MSR_AMD64_SNP_ALT_INJ BIT_ULL(6) |
600 | #define MSR_AMD64_SNP_DEBUG_SWAP BIT_ULL(7) |
601 | #define MSR_AMD64_SNP_PREVENT_HOST_IBS BIT_ULL(8) |
602 | #define MSR_AMD64_SNP_BTB_ISOLATION BIT_ULL(9) |
603 | #define MSR_AMD64_SNP_VMPL_SSS BIT_ULL(10) |
604 | #define MSR_AMD64_SNP_SECURE_TSC BIT_ULL(11) |
605 | #define MSR_AMD64_SNP_VMGEXIT_PARAM BIT_ULL(12) |
606 | #define MSR_AMD64_SNP_IBS_VIRT BIT_ULL(14) |
607 | #define MSR_AMD64_SNP_VMSA_REG_PROTECTION BIT_ULL(16) |
608 | #define MSR_AMD64_SNP_SMT_PROTECTION BIT_ULL(17) |
609 | |
610 | /* SNP feature bits reserved for future use. */ |
611 | #define MSR_AMD64_SNP_RESERVED_BIT13 BIT_ULL(13) |
612 | #define MSR_AMD64_SNP_RESERVED_BIT15 BIT_ULL(15) |
613 | #define MSR_AMD64_SNP_RESERVED_MASK GENMASK_ULL(63, 18) |
614 | |
615 | #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f |
616 | |
617 | /* AMD Collaborative Processor Performance Control MSRs */ |
618 | #define MSR_AMD_CPPC_CAP1 0xc00102b0 |
619 | #define MSR_AMD_CPPC_ENABLE 0xc00102b1 |
620 | #define MSR_AMD_CPPC_CAP2 0xc00102b2 |
621 | #define MSR_AMD_CPPC_REQ 0xc00102b3 |
622 | #define MSR_AMD_CPPC_STATUS 0xc00102b4 |
623 | |
624 | #define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff) |
625 | #define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) |
626 | #define AMD_CPPC_NOMINAL_PERF(x) (((x) >> 16) & 0xff) |
627 | #define AMD_CPPC_HIGHEST_PERF(x) (((x) >> 24) & 0xff) |
628 | |
629 | #define AMD_CPPC_MAX_PERF(x) (((x) & 0xff) << 0) |
630 | #define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8) |
631 | #define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16) |
632 | #define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) |
633 | |
634 | /* AMD Performance Counter Global Status and Control MSRs */ |
635 | #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300 |
636 | #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 |
637 | #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 |
638 | |
639 | /* AMD Last Branch Record MSRs */ |
640 | #define MSR_AMD64_LBR_SELECT 0xc000010e |
641 | |
642 | /* Zen4 */ |
643 | #define MSR_ZEN4_BP_CFG 0xc001102e |
644 | #define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5 |
645 | |
646 | /* Fam 19h MSRs */ |
647 | #define MSR_F19H_UMC_PERF_CTL 0xc0010800 |
648 | #define MSR_F19H_UMC_PERF_CTR 0xc0010801 |
649 | |
650 | /* Zen 2 */ |
651 | #define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3 |
652 | #define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1) |
653 | |
654 | /* Fam 17h MSRs */ |
655 | #define MSR_F17H_IRPERF 0xc00000e9 |
656 | |
657 | /* Fam 16h MSRs */ |
658 | #define MSR_F16H_L2I_PERF_CTL 0xc0010230 |
659 | #define MSR_F16H_L2I_PERF_CTR 0xc0010231 |
660 | #define MSR_F16H_DR1_ADDR_MASK 0xc0011019 |
661 | #define MSR_F16H_DR2_ADDR_MASK 0xc001101a |
662 | #define MSR_F16H_DR3_ADDR_MASK 0xc001101b |
663 | #define MSR_F16H_DR0_ADDR_MASK 0xc0011027 |
664 | |
665 | /* Fam 15h MSRs */ |
666 | #define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a |
667 | #define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b |
668 | #define MSR_F15H_PERF_CTL 0xc0010200 |
669 | #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL |
670 | #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) |
671 | #define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4) |
672 | #define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6) |
673 | #define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8) |
674 | #define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10) |
675 | |
676 | #define MSR_F15H_PERF_CTR 0xc0010201 |
677 | #define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR |
678 | #define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2) |
679 | #define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4) |
680 | #define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6) |
681 | #define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8) |
682 | #define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10) |
683 | |
684 | #define MSR_F15H_NB_PERF_CTL 0xc0010240 |
685 | #define MSR_F15H_NB_PERF_CTR 0xc0010241 |
686 | #define MSR_F15H_PTSC 0xc0010280 |
687 | #define MSR_F15H_IC_CFG 0xc0011021 |
688 | #define MSR_F15H_EX_CFG 0xc001102c |
689 | |
690 | /* Fam 10h MSRs */ |
691 | #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 |
692 | #define FAM10H_MMIO_CONF_ENABLE (1<<0) |
693 | #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf |
694 | #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 |
695 | #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL |
696 | #define FAM10H_MMIO_CONF_BASE_SHIFT 20 |
697 | #define MSR_FAM10H_NODE_ID 0xc001100c |
698 | |
699 | /* K8 MSRs */ |
700 | #define MSR_K8_TOP_MEM1 0xc001001a |
701 | #define MSR_K8_TOP_MEM2 0xc001001d |
702 | #define MSR_AMD64_SYSCFG 0xc0010010 |
703 | #define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23 |
704 | #define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT) |
705 | #define MSR_K8_INT_PENDING_MSG 0xc0010055 |
706 | /* C1E active bits in int pending message */ |
707 | #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 |
708 | #define MSR_K8_TSEG_ADDR 0xc0010112 |
709 | #define MSR_K8_TSEG_MASK 0xc0010113 |
710 | #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ |
711 | #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ |
712 | #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ |
713 | |
714 | /* K7 MSRs */ |
715 | #define MSR_K7_EVNTSEL0 0xc0010000 |
716 | #define MSR_K7_PERFCTR0 0xc0010004 |
717 | #define MSR_K7_EVNTSEL1 0xc0010001 |
718 | #define MSR_K7_PERFCTR1 0xc0010005 |
719 | #define MSR_K7_EVNTSEL2 0xc0010002 |
720 | #define MSR_K7_PERFCTR2 0xc0010006 |
721 | #define MSR_K7_EVNTSEL3 0xc0010003 |
722 | #define MSR_K7_PERFCTR3 0xc0010007 |
723 | #define MSR_K7_CLK_CTL 0xc001001b |
724 | #define MSR_K7_HWCR 0xc0010015 |
725 | #define MSR_K7_HWCR_SMMLOCK_BIT 0 |
726 | #define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT) |
727 | #define MSR_K7_HWCR_IRPERF_EN_BIT 30 |
728 | #define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) |
729 | #define MSR_K7_FID_VID_CTL 0xc0010041 |
730 | #define MSR_K7_FID_VID_STATUS 0xc0010042 |
731 | |
732 | /* K6 MSRs */ |
733 | #define MSR_K6_WHCR 0xc0000082 |
734 | #define MSR_K6_UWCCR 0xc0000085 |
735 | #define MSR_K6_EPMR 0xc0000086 |
736 | #define MSR_K6_PSOR 0xc0000087 |
737 | #define MSR_K6_PFIR 0xc0000088 |
738 | |
739 | /* Centaur-Hauls/IDT defined MSRs. */ |
740 | #define MSR_IDT_FCR1 0x00000107 |
741 | #define MSR_IDT_FCR2 0x00000108 |
742 | #define MSR_IDT_FCR3 0x00000109 |
743 | #define MSR_IDT_FCR4 0x0000010a |
744 | |
745 | #define MSR_IDT_MCR0 0x00000110 |
746 | #define MSR_IDT_MCR1 0x00000111 |
747 | #define MSR_IDT_MCR2 0x00000112 |
748 | #define MSR_IDT_MCR3 0x00000113 |
749 | #define MSR_IDT_MCR4 0x00000114 |
750 | #define MSR_IDT_MCR5 0x00000115 |
751 | #define MSR_IDT_MCR6 0x00000116 |
752 | #define MSR_IDT_MCR7 0x00000117 |
753 | #define MSR_IDT_MCR_CTRL 0x00000120 |
754 | |
755 | /* VIA Cyrix defined MSRs*/ |
756 | #define MSR_VIA_FCR 0x00001107 |
757 | #define MSR_VIA_LONGHAUL 0x0000110a |
758 | #define MSR_VIA_RNG 0x0000110b |
759 | #define MSR_VIA_BCR2 0x00001147 |
760 | |
761 | /* Transmeta defined MSRs */ |
762 | #define MSR_TMTA_LONGRUN_CTRL 0x80868010 |
763 | #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 |
764 | #define MSR_TMTA_LRTI_READOUT 0x80868018 |
765 | #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a |
766 | |
767 | /* Intel defined MSRs. */ |
768 | #define MSR_IA32_P5_MC_ADDR 0x00000000 |
769 | #define MSR_IA32_P5_MC_TYPE 0x00000001 |
770 | #define MSR_IA32_TSC 0x00000010 |
771 | #define MSR_IA32_PLATFORM_ID 0x00000017 |
772 | #define MSR_IA32_EBL_CR_POWERON 0x0000002a |
773 | #define MSR_EBC_FREQUENCY_ID 0x0000002c |
774 | #define MSR_SMI_COUNT 0x00000034 |
775 | |
776 | /* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */ |
777 | #define MSR_IA32_FEAT_CTL 0x0000003a |
778 | #define FEAT_CTL_LOCKED BIT(0) |
779 | #define FEAT_CTL_VMX_ENABLED_INSIDE_SMX BIT(1) |
780 | #define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX BIT(2) |
781 | #define FEAT_CTL_SGX_LC_ENABLED BIT(17) |
782 | #define FEAT_CTL_SGX_ENABLED BIT(18) |
783 | #define FEAT_CTL_LMCE_ENABLED BIT(20) |
784 | |
785 | #define MSR_IA32_TSC_ADJUST 0x0000003b |
786 | #define MSR_IA32_BNDCFGS 0x00000d90 |
787 | |
788 | #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc |
789 | |
790 | #define MSR_IA32_XFD 0x000001c4 |
791 | #define MSR_IA32_XFD_ERR 0x000001c5 |
792 | #define MSR_IA32_XSS 0x00000da0 |
793 | |
794 | #define MSR_IA32_APICBASE 0x0000001b |
795 | #define MSR_IA32_APICBASE_BSP (1<<8) |
796 | #define MSR_IA32_APICBASE_ENABLE (1<<11) |
797 | #define MSR_IA32_APICBASE_BASE (0xfffff<<12) |
798 | |
799 | #define MSR_IA32_UCODE_WRITE 0x00000079 |
800 | #define MSR_IA32_UCODE_REV 0x0000008b |
801 | |
802 | /* Intel SGX Launch Enclave Public Key Hash MSRs */ |
803 | #define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C |
804 | #define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D |
805 | #define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E |
806 | #define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F |
807 | |
808 | #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b |
809 | #define MSR_IA32_SMBASE 0x0000009e |
810 | |
811 | #define MSR_IA32_PERF_STATUS 0x00000198 |
812 | #define MSR_IA32_PERF_CTL 0x00000199 |
813 | #define INTEL_PERF_CTL_MASK 0xffff |
814 | |
815 | /* AMD Branch Sampling configuration */ |
816 | #define MSR_AMD_DBG_EXTN_CFG 0xc000010f |
817 | #define MSR_AMD_SAMP_BR_FROM 0xc0010300 |
818 | |
819 | #define DBG_EXTN_CFG_LBRV2EN BIT_ULL(6) |
820 | |
821 | #define MSR_IA32_MPERF 0x000000e7 |
822 | #define MSR_IA32_APERF 0x000000e8 |
823 | |
824 | #define MSR_IA32_THERM_CONTROL 0x0000019a |
825 | #define MSR_IA32_THERM_INTERRUPT 0x0000019b |
826 | |
827 | #define THERM_INT_HIGH_ENABLE (1 << 0) |
828 | #define THERM_INT_LOW_ENABLE (1 << 1) |
829 | #define THERM_INT_PLN_ENABLE (1 << 24) |
830 | |
831 | #define MSR_IA32_THERM_STATUS 0x0000019c |
832 | |
833 | #define THERM_STATUS_PROCHOT (1 << 0) |
834 | #define THERM_STATUS_POWER_LIMIT (1 << 10) |
835 | |
836 | #define MSR_THERM2_CTL 0x0000019d |
837 | |
838 | #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) |
839 | |
840 | #define MSR_IA32_MISC_ENABLE 0x000001a0 |
841 | |
842 | #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 |
843 | |
844 | #define MSR_MISC_FEATURE_CONTROL 0x000001a4 |
845 | #define MSR_MISC_PWR_MGMT 0x000001aa |
846 | |
847 | #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 |
848 | #define ENERGY_PERF_BIAS_PERFORMANCE 0 |
849 | #define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4 |
850 | #define ENERGY_PERF_BIAS_NORMAL 6 |
851 | #define ENERGY_PERF_BIAS_NORMAL_POWERSAVE 7 |
852 | #define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8 |
853 | #define ENERGY_PERF_BIAS_POWERSAVE 15 |
854 | |
855 | #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 |
856 | |
857 | #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) |
858 | #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) |
859 | #define PACKAGE_THERM_STATUS_HFI_UPDATED (1 << 26) |
860 | |
861 | #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 |
862 | |
863 | #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) |
864 | #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) |
865 | #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) |
866 | #define PACKAGE_THERM_INT_HFI_ENABLE (1 << 25) |
867 | |
868 | /* Thermal Thresholds Support */ |
869 | #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) |
870 | #define THERM_SHIFT_THRESHOLD0 8 |
871 | #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) |
872 | #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) |
873 | #define THERM_SHIFT_THRESHOLD1 16 |
874 | #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) |
875 | #define THERM_STATUS_THRESHOLD0 (1 << 6) |
876 | #define THERM_LOG_THRESHOLD0 (1 << 7) |
877 | #define THERM_STATUS_THRESHOLD1 (1 << 8) |
878 | #define THERM_LOG_THRESHOLD1 (1 << 9) |
879 | |
880 | /* MISC_ENABLE bits: architectural */ |
881 | #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 |
882 | #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) |
883 | #define MSR_IA32_MISC_ENABLE_TCC_BIT 1 |
884 | #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) |
885 | #define MSR_IA32_MISC_ENABLE_EMON_BIT 7 |
886 | #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) |
887 | #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 |
888 | #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) |
889 | #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 |
890 | #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) |
891 | #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 |
892 | #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) |
893 | #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 |
894 | #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) |
895 | #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 |
896 | #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) |
897 | #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 |
898 | #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) |
899 | #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 |
900 | #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) |
901 | |
902 | /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ |
903 | #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 |
904 | #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) |
905 | #define MSR_IA32_MISC_ENABLE_TM1_BIT 3 |
906 | #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) |
907 | #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 |
908 | #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) |
909 | #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 |
910 | #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) |
911 | #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 |
912 | #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) |
913 | #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 |
914 | #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) |
915 | #define MSR_IA32_MISC_ENABLE_FERR_BIT 10 |
916 | #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) |
917 | #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 |
918 | #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) |
919 | #define MSR_IA32_MISC_ENABLE_TM2_BIT 13 |
920 | #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) |
921 | #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 |
922 | #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) |
923 | #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 |
924 | #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) |
925 | #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 |
926 | #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) |
927 | #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 |
928 | #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) |
929 | #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 |
930 | #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) |
931 | #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 |
932 | #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) |
933 | |
934 | /* MISC_FEATURES_ENABLES non-architectural features */ |
935 | #define MSR_MISC_FEATURES_ENABLES 0x00000140 |
936 | |
937 | #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0 |
938 | #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT) |
939 | #define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1 |
940 | |
941 | #define MSR_IA32_TSC_DEADLINE 0x000006E0 |
942 | |
943 | |
944 | #define MSR_TSX_FORCE_ABORT 0x0000010F |
945 | |
946 | #define MSR_TFA_RTM_FORCE_ABORT_BIT 0 |
947 | #define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT) |
948 | #define MSR_TFA_TSX_CPUID_CLEAR_BIT 1 |
949 | #define MSR_TFA_TSX_CPUID_CLEAR BIT_ULL(MSR_TFA_TSX_CPUID_CLEAR_BIT) |
950 | #define MSR_TFA_SDV_ENABLE_RTM_BIT 2 |
951 | #define MSR_TFA_SDV_ENABLE_RTM BIT_ULL(MSR_TFA_SDV_ENABLE_RTM_BIT) |
952 | |
953 | /* P4/Xeon+ specific */ |
954 | #define MSR_IA32_MCG_EAX 0x00000180 |
955 | #define MSR_IA32_MCG_EBX 0x00000181 |
956 | #define MSR_IA32_MCG_ECX 0x00000182 |
957 | #define MSR_IA32_MCG_EDX 0x00000183 |
958 | #define MSR_IA32_MCG_ESI 0x00000184 |
959 | #define MSR_IA32_MCG_EDI 0x00000185 |
960 | #define MSR_IA32_MCG_EBP 0x00000186 |
961 | #define MSR_IA32_MCG_ESP 0x00000187 |
962 | #define MSR_IA32_MCG_EFLAGS 0x00000188 |
963 | #define MSR_IA32_MCG_EIP 0x00000189 |
964 | #define MSR_IA32_MCG_RESERVED 0x0000018a |
965 | |
966 | /* Pentium IV performance counter MSRs */ |
967 | #define MSR_P4_BPU_PERFCTR0 0x00000300 |
968 | #define MSR_P4_BPU_PERFCTR1 0x00000301 |
969 | #define MSR_P4_BPU_PERFCTR2 0x00000302 |
970 | #define MSR_P4_BPU_PERFCTR3 0x00000303 |
971 | #define MSR_P4_MS_PERFCTR0 0x00000304 |
972 | #define MSR_P4_MS_PERFCTR1 0x00000305 |
973 | #define MSR_P4_MS_PERFCTR2 0x00000306 |
974 | #define MSR_P4_MS_PERFCTR3 0x00000307 |
975 | #define MSR_P4_FLAME_PERFCTR0 0x00000308 |
976 | #define MSR_P4_FLAME_PERFCTR1 0x00000309 |
977 | #define MSR_P4_FLAME_PERFCTR2 0x0000030a |
978 | #define MSR_P4_FLAME_PERFCTR3 0x0000030b |
979 | #define MSR_P4_IQ_PERFCTR0 0x0000030c |
980 | #define MSR_P4_IQ_PERFCTR1 0x0000030d |
981 | #define MSR_P4_IQ_PERFCTR2 0x0000030e |
982 | #define MSR_P4_IQ_PERFCTR3 0x0000030f |
983 | #define MSR_P4_IQ_PERFCTR4 0x00000310 |
984 | #define MSR_P4_IQ_PERFCTR5 0x00000311 |
985 | #define MSR_P4_BPU_CCCR0 0x00000360 |
986 | #define MSR_P4_BPU_CCCR1 0x00000361 |
987 | #define MSR_P4_BPU_CCCR2 0x00000362 |
988 | #define MSR_P4_BPU_CCCR3 0x00000363 |
989 | #define MSR_P4_MS_CCCR0 0x00000364 |
990 | #define MSR_P4_MS_CCCR1 0x00000365 |
991 | #define MSR_P4_MS_CCCR2 0x00000366 |
992 | #define MSR_P4_MS_CCCR3 0x00000367 |
993 | #define MSR_P4_FLAME_CCCR0 0x00000368 |
994 | #define MSR_P4_FLAME_CCCR1 0x00000369 |
995 | #define MSR_P4_FLAME_CCCR2 0x0000036a |
996 | #define MSR_P4_FLAME_CCCR3 0x0000036b |
997 | #define MSR_P4_IQ_CCCR0 0x0000036c |
998 | #define MSR_P4_IQ_CCCR1 0x0000036d |
999 | #define MSR_P4_IQ_CCCR2 0x0000036e |
1000 | #define MSR_P4_IQ_CCCR3 0x0000036f |
1001 | #define MSR_P4_IQ_CCCR4 0x00000370 |
1002 | #define MSR_P4_IQ_CCCR5 0x00000371 |
1003 | #define MSR_P4_ALF_ESCR0 0x000003ca |
1004 | #define MSR_P4_ALF_ESCR1 0x000003cb |
1005 | #define MSR_P4_BPU_ESCR0 0x000003b2 |
1006 | #define MSR_P4_BPU_ESCR1 0x000003b3 |
1007 | #define MSR_P4_BSU_ESCR0 0x000003a0 |
1008 | #define MSR_P4_BSU_ESCR1 0x000003a1 |
1009 | #define MSR_P4_CRU_ESCR0 0x000003b8 |
1010 | #define MSR_P4_CRU_ESCR1 0x000003b9 |
1011 | #define MSR_P4_CRU_ESCR2 0x000003cc |
1012 | #define MSR_P4_CRU_ESCR3 0x000003cd |
1013 | #define MSR_P4_CRU_ESCR4 0x000003e0 |
1014 | #define MSR_P4_CRU_ESCR5 0x000003e1 |
1015 | #define MSR_P4_DAC_ESCR0 0x000003a8 |
1016 | #define MSR_P4_DAC_ESCR1 0x000003a9 |
1017 | #define MSR_P4_FIRM_ESCR0 0x000003a4 |
1018 | #define MSR_P4_FIRM_ESCR1 0x000003a5 |
1019 | #define MSR_P4_FLAME_ESCR0 0x000003a6 |
1020 | #define MSR_P4_FLAME_ESCR1 0x000003a7 |
1021 | #define MSR_P4_FSB_ESCR0 0x000003a2 |
1022 | #define MSR_P4_FSB_ESCR1 0x000003a3 |
1023 | #define MSR_P4_IQ_ESCR0 0x000003ba |
1024 | #define MSR_P4_IQ_ESCR1 0x000003bb |
1025 | #define MSR_P4_IS_ESCR0 0x000003b4 |
1026 | #define MSR_P4_IS_ESCR1 0x000003b5 |
1027 | #define MSR_P4_ITLB_ESCR0 0x000003b6 |
1028 | #define MSR_P4_ITLB_ESCR1 0x000003b7 |
1029 | #define MSR_P4_IX_ESCR0 0x000003c8 |
1030 | #define MSR_P4_IX_ESCR1 0x000003c9 |
1031 | #define MSR_P4_MOB_ESCR0 0x000003aa |
1032 | #define MSR_P4_MOB_ESCR1 0x000003ab |
1033 | #define MSR_P4_MS_ESCR0 0x000003c0 |
1034 | #define MSR_P4_MS_ESCR1 0x000003c1 |
1035 | #define MSR_P4_PMH_ESCR0 0x000003ac |
1036 | #define MSR_P4_PMH_ESCR1 0x000003ad |
1037 | #define MSR_P4_RAT_ESCR0 0x000003bc |
1038 | #define MSR_P4_RAT_ESCR1 0x000003bd |
1039 | #define MSR_P4_SAAT_ESCR0 0x000003ae |
1040 | #define MSR_P4_SAAT_ESCR1 0x000003af |
1041 | #define MSR_P4_SSU_ESCR0 0x000003be |
1042 | #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ |
1043 | |
1044 | #define MSR_P4_TBPU_ESCR0 0x000003c2 |
1045 | #define MSR_P4_TBPU_ESCR1 0x000003c3 |
1046 | #define MSR_P4_TC_ESCR0 0x000003c4 |
1047 | #define MSR_P4_TC_ESCR1 0x000003c5 |
1048 | #define MSR_P4_U2L_ESCR0 0x000003b0 |
1049 | #define MSR_P4_U2L_ESCR1 0x000003b1 |
1050 | |
1051 | #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 |
1052 | |
1053 | /* Intel Core-based CPU performance counters */ |
1054 | #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 |
1055 | #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a |
1056 | #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b |
1057 | #define MSR_CORE_PERF_FIXED_CTR3 0x0000030c |
1058 | #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d |
1059 | #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e |
1060 | #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f |
1061 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 |
1062 | |
1063 | #define MSR_PERF_METRICS 0x00000329 |
1064 | |
1065 | /* PERF_GLOBAL_OVF_CTL bits */ |
1066 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT 55 |
1067 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT) |
1068 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT 62 |
1069 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT) |
1070 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63 |
1071 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT) |
1072 | |
1073 | /* Geode defined MSRs */ |
1074 | #define MSR_GEODE_BUSCONT_CONF0 0x00001900 |
1075 | |
1076 | /* Intel VT MSRs */ |
1077 | #define MSR_IA32_VMX_BASIC 0x00000480 |
1078 | #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 |
1079 | #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 |
1080 | #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 |
1081 | #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 |
1082 | #define MSR_IA32_VMX_MISC 0x00000485 |
1083 | #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 |
1084 | #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 |
1085 | #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 |
1086 | #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 |
1087 | #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a |
1088 | #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b |
1089 | #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c |
1090 | #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d |
1091 | #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e |
1092 | #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f |
1093 | #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 |
1094 | #define MSR_IA32_VMX_VMFUNC 0x00000491 |
1095 | #define MSR_IA32_VMX_PROCBASED_CTLS3 0x00000492 |
1096 | |
1097 | /* VMX_BASIC bits and bitmasks */ |
1098 | #define VMX_BASIC_VMCS_SIZE_SHIFT 32 |
1099 | #define VMX_BASIC_TRUE_CTLS (1ULL << 55) |
1100 | #define VMX_BASIC_64 0x0001000000000000LLU |
1101 | #define VMX_BASIC_MEM_TYPE_SHIFT 50 |
1102 | #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU |
1103 | #define VMX_BASIC_MEM_TYPE_WB 6LLU |
1104 | #define VMX_BASIC_INOUT 0x0040000000000000LLU |
1105 | |
1106 | /* Resctrl MSRs: */ |
1107 | /* - Intel: */ |
1108 | #define MSR_IA32_L3_QOS_CFG 0xc81 |
1109 | #define MSR_IA32_L2_QOS_CFG 0xc82 |
1110 | #define MSR_IA32_QM_EVTSEL 0xc8d |
1111 | #define MSR_IA32_QM_CTR 0xc8e |
1112 | #define MSR_IA32_PQR_ASSOC 0xc8f |
1113 | #define MSR_IA32_L3_CBM_BASE 0xc90 |
1114 | #define MSR_IA32_L2_CBM_BASE 0xd10 |
1115 | #define MSR_IA32_MBA_THRTL_BASE 0xd50 |
1116 | |
1117 | /* - AMD: */ |
1118 | #define MSR_IA32_MBA_BW_BASE 0xc0000200 |
1119 | #define MSR_IA32_SMBA_BW_BASE 0xc0000280 |
1120 | #define MSR_IA32_EVT_CFG_BASE 0xc0000400 |
1121 | |
1122 | /* MSR_IA32_VMX_MISC bits */ |
1123 | #define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) |
1124 | #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) |
1125 | #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F |
1126 | |
1127 | /* AMD-V MSRs */ |
1128 | #define MSR_VM_CR 0xc0010114 |
1129 | #define MSR_VM_IGNNE 0xc0010115 |
1130 | #define MSR_VM_HSAVE_PA 0xc0010117 |
1131 | |
1132 | #define SVM_VM_CR_VALID_MASK 0x001fULL |
1133 | #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL |
1134 | #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL |
1135 | |
1136 | /* Hardware Feedback Interface */ |
1137 | #define MSR_IA32_HW_FEEDBACK_PTR 0x17d0 |
1138 | #define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1 |
1139 | |
1140 | /* x2APIC locked status */ |
1141 | #define MSR_IA32_XAPIC_DISABLE_STATUS 0xBD |
1142 | #define LEGACY_XAPIC_DISABLED BIT(0) /* |
1143 | * x2APIC mode is locked and |
1144 | * disabling x2APIC will cause |
1145 | * a #GP |
1146 | */ |
1147 | |
1148 | #endif /* _ASM_X86_MSR_INDEX_H */ |
1149 | |