1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * Low-Level PCI Access for i386 machines. |
4 | * |
5 | * (c) 1999 Martin Mares <mj@ucw.cz> |
6 | */ |
7 | |
8 | #include <linux/ioport.h> |
9 | |
10 | #undef DEBUG |
11 | |
12 | #ifdef DEBUG |
13 | #define DBG(fmt, ...) printk(fmt, ##__VA_ARGS__) |
14 | #else |
15 | #define DBG(fmt, ...) \ |
16 | do { \ |
17 | if (0) \ |
18 | printk(fmt, ##__VA_ARGS__); \ |
19 | } while (0) |
20 | #endif |
21 | |
22 | #define PCI_PROBE_BIOS 0x0001 |
23 | #define PCI_PROBE_CONF1 0x0002 |
24 | #define PCI_PROBE_CONF2 0x0004 |
25 | #define PCI_PROBE_MMCONF 0x0008 |
26 | #define PCI_PROBE_MASK 0x000f |
27 | #define PCI_PROBE_NOEARLY 0x0010 |
28 | |
29 | #define PCI_NO_CHECKS 0x0400 |
30 | #define PCI_USE_PIRQ_MASK 0x0800 |
31 | #define PCI_ASSIGN_ROMS 0x1000 |
32 | #define PCI_BIOS_IRQ_SCAN 0x2000 |
33 | #define PCI_ASSIGN_ALL_BUSSES 0x4000 |
34 | #define PCI_CAN_SKIP_ISA_ALIGN 0x8000 |
35 | #define PCI_USE__CRS 0x10000 |
36 | #define PCI_CHECK_ENABLE_AMD_MMCONF 0x20000 |
37 | #define PCI_HAS_IO_ECS 0x40000 |
38 | #define PCI_NOASSIGN_ROMS 0x80000 |
39 | #define PCI_ROOT_NO_CRS 0x100000 |
40 | #define PCI_NOASSIGN_BARS 0x200000 |
41 | #define PCI_BIG_ROOT_WINDOW 0x400000 |
42 | |
43 | extern unsigned int pci_probe; |
44 | extern unsigned long pirq_table_addr; |
45 | |
46 | enum pci_bf_sort_state { |
47 | pci_bf_sort_default, |
48 | pci_force_nobf, |
49 | pci_force_bf, |
50 | pci_dmi_bf, |
51 | }; |
52 | |
53 | /* pci-i386.c */ |
54 | |
55 | void pcibios_resource_survey(void); |
56 | void pcibios_set_cache_line_size(void); |
57 | |
58 | /* pci-pc.c */ |
59 | |
60 | extern int pcibios_last_bus; |
61 | extern struct pci_ops pci_root_ops; |
62 | |
63 | void pcibios_scan_specific_bus(int busn); |
64 | |
65 | /* pci-irq.c */ |
66 | |
67 | struct irq_info { |
68 | u8 bus, devfn; /* Bus, device and function */ |
69 | struct { |
70 | u8 link; /* IRQ line ID, chipset dependent, |
71 | 0 = not routed */ |
72 | u16 bitmap; /* Available IRQs */ |
73 | } __attribute__((packed)) irq[4]; |
74 | u8 slot; /* Slot number, 0=onboard */ |
75 | u8 rfu; |
76 | } __attribute__((packed)); |
77 | |
78 | struct irq_routing_table { |
79 | u32 signature; /* PIRQ_SIGNATURE should be here */ |
80 | u16 version; /* PIRQ_VERSION */ |
81 | u16 size; /* Table size in bytes */ |
82 | u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */ |
83 | u16 exclusive_irqs; /* IRQs devoted exclusively to |
84 | PCI usage */ |
85 | u16 rtr_vendor, rtr_device; /* Vendor and device ID of |
86 | interrupt router */ |
87 | u32 miniport_data; /* Crap */ |
88 | u8 rfu[11]; |
89 | u8 checksum; /* Modulo 256 checksum must give 0 */ |
90 | struct irq_info slots[0]; |
91 | } __attribute__((packed)); |
92 | |
93 | extern unsigned int pcibios_irq_mask; |
94 | |
95 | extern raw_spinlock_t pci_config_lock; |
96 | |
97 | extern int (*pcibios_enable_irq)(struct pci_dev *dev); |
98 | extern void (*pcibios_disable_irq)(struct pci_dev *dev); |
99 | |
100 | extern bool mp_should_keep_irq(struct device *dev); |
101 | |
102 | struct pci_raw_ops { |
103 | int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn, |
104 | int reg, int len, u32 *val); |
105 | int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn, |
106 | int reg, int len, u32 val); |
107 | }; |
108 | |
109 | extern const struct pci_raw_ops *raw_pci_ops; |
110 | extern const struct pci_raw_ops *raw_pci_ext_ops; |
111 | |
112 | extern const struct pci_raw_ops pci_mmcfg; |
113 | extern const struct pci_raw_ops pci_direct_conf1; |
114 | extern bool port_cf9_safe; |
115 | |
116 | /* arch_initcall level */ |
117 | extern int pci_direct_probe(void); |
118 | extern void pci_direct_init(int type); |
119 | extern void pci_pcbios_init(void); |
120 | extern void __init dmi_check_pciprobe(void); |
121 | extern void __init dmi_check_skip_isa_align(void); |
122 | |
123 | /* some common used subsys_initcalls */ |
124 | #ifdef CONFIG_PCI |
125 | extern int __init pci_acpi_init(void); |
126 | #else |
127 | static inline int __init pci_acpi_init(void) |
128 | { |
129 | return -EINVAL; |
130 | } |
131 | #endif |
132 | extern void __init pcibios_irq_init(void); |
133 | extern int __init pcibios_init(void); |
134 | extern int pci_legacy_init(void); |
135 | extern void pcibios_fixup_irqs(void); |
136 | |
137 | /* pci-mmconfig.c */ |
138 | |
139 | /* "PCI MMCONFIG %04x [bus %02x-%02x]" */ |
140 | #define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2) |
141 | |
142 | struct pci_mmcfg_region { |
143 | struct list_head list; |
144 | struct resource res; |
145 | u64 address; |
146 | char __iomem *virt; |
147 | u16 segment; |
148 | u8 start_bus; |
149 | u8 end_bus; |
150 | char name[PCI_MMCFG_RESOURCE_NAME_LEN]; |
151 | }; |
152 | |
153 | extern int __init pci_mmcfg_arch_init(void); |
154 | extern void __init pci_mmcfg_arch_free(void); |
155 | extern int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg); |
156 | extern void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg); |
157 | extern int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end, |
158 | phys_addr_t addr); |
159 | extern int pci_mmconfig_delete(u16 seg, u8 start, u8 end); |
160 | extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus); |
161 | extern struct pci_mmcfg_region *__init pci_mmconfig_add(int segment, int start, |
162 | int end, u64 addr); |
163 | |
164 | extern struct list_head pci_mmcfg_list; |
165 | |
166 | #define PCI_MMCFG_BUS_OFFSET(bus) ((bus) << 20) |
167 | |
168 | /* |
169 | * On AMD Fam10h CPUs, all PCI MMIO configuration space accesses must use |
170 | * %eax. No other source or target registers may be used. The following |
171 | * mmio_config_* accessors enforce this. See "BIOS and Kernel Developer's |
172 | * Guide (BKDG) For AMD Family 10h Processors", rev. 3.48, sec 2.11.1, |
173 | * "MMIO Configuration Coding Requirements". |
174 | */ |
175 | static inline unsigned char mmio_config_readb(void __iomem *pos) |
176 | { |
177 | u8 val; |
178 | asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos)); |
179 | return val; |
180 | } |
181 | |
182 | static inline unsigned short mmio_config_readw(void __iomem *pos) |
183 | { |
184 | u16 val; |
185 | asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos)); |
186 | return val; |
187 | } |
188 | |
189 | static inline unsigned int mmio_config_readl(void __iomem *pos) |
190 | { |
191 | u32 val; |
192 | asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos)); |
193 | return val; |
194 | } |
195 | |
196 | static inline void mmio_config_writeb(void __iomem *pos, u8 val) |
197 | { |
198 | asm volatile("movb %%al,(%1)" : : "a" (val), "r" (pos) : "memory" ); |
199 | } |
200 | |
201 | static inline void mmio_config_writew(void __iomem *pos, u16 val) |
202 | { |
203 | asm volatile("movw %%ax,(%1)" : : "a" (val), "r" (pos) : "memory" ); |
204 | } |
205 | |
206 | static inline void mmio_config_writel(void __iomem *pos, u32 val) |
207 | { |
208 | asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) : "memory" ); |
209 | } |
210 | |
211 | #ifdef CONFIG_PCI |
212 | # ifdef CONFIG_ACPI |
213 | # define x86_default_pci_init pci_acpi_init |
214 | # else |
215 | # define x86_default_pci_init pci_legacy_init |
216 | # endif |
217 | # define x86_default_pci_init_irq pcibios_irq_init |
218 | # define x86_default_pci_fixup_irqs pcibios_fixup_irqs |
219 | #else |
220 | # define x86_default_pci_init NULL |
221 | # define x86_default_pci_init_irq NULL |
222 | # define x86_default_pci_fixup_irqs NULL |
223 | #endif |
224 | |