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1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
---|---|
2 | /* |
3 | * platform_sst_audio.h: sst audio platform data header file |
4 | * |
5 | * Copyright (C) 2012-14 Intel Corporation |
6 | * Author: Jeeja KP <jeeja.kp@intel.com> |
7 | * Omair Mohammed Abdullah <omair.m.abdullah@intel.com> |
8 | * Vinod Koul ,vinod.koul@intel.com> |
9 | */ |
10 | #ifndef _PLATFORM_SST_AUDIO_H_ |
11 | #define _PLATFORM_SST_AUDIO_H_ |
12 | |
13 | #define MAX_NUM_STREAMS_MRFLD 25 |
14 | #define MAX_NUM_STREAMS MAX_NUM_STREAMS_MRFLD |
15 | |
16 | enum sst_audio_task_id_mrfld { |
17 | SST_TASK_ID_NONE = 0, |
18 | SST_TASK_ID_SBA = 1, |
19 | SST_TASK_ID_MEDIA = 3, |
20 | SST_TASK_ID_MAX = SST_TASK_ID_MEDIA, |
21 | }; |
22 | |
23 | /* Device IDs for Merrifield are Pipe IDs, |
24 | * ref: DSP spec v0.75 */ |
25 | enum sst_audio_device_id_mrfld { |
26 | /* Output pipeline IDs */ |
27 | PIPE_ID_OUT_START = 0x0, |
28 | PIPE_CODEC_OUT0 = 0x2, |
29 | PIPE_CODEC_OUT1 = 0x3, |
30 | PIPE_SPROT_LOOP_OUT = 0x4, |
31 | PIPE_MEDIA_LOOP1_OUT = 0x5, |
32 | PIPE_MEDIA_LOOP2_OUT = 0x6, |
33 | PIPE_VOIP_OUT = 0xC, |
34 | PIPE_PCM0_OUT = 0xD, |
35 | PIPE_PCM1_OUT = 0xE, |
36 | PIPE_PCM2_OUT = 0xF, |
37 | PIPE_MEDIA0_OUT = 0x12, |
38 | PIPE_MEDIA1_OUT = 0x13, |
39 | /* Input Pipeline IDs */ |
40 | PIPE_ID_IN_START = 0x80, |
41 | PIPE_CODEC_IN0 = 0x82, |
42 | PIPE_CODEC_IN1 = 0x83, |
43 | PIPE_SPROT_LOOP_IN = 0x84, |
44 | PIPE_MEDIA_LOOP1_IN = 0x85, |
45 | PIPE_MEDIA_LOOP2_IN = 0x86, |
46 | PIPE_VOIP_IN = 0x8C, |
47 | PIPE_PCM0_IN = 0x8D, |
48 | PIPE_PCM1_IN = 0x8E, |
49 | PIPE_MEDIA0_IN = 0x8F, |
50 | PIPE_MEDIA1_IN = 0x90, |
51 | PIPE_MEDIA2_IN = 0x91, |
52 | PIPE_MEDIA3_IN = 0x9C, |
53 | PIPE_RSVD = 0xFF, |
54 | }; |
55 | |
56 | /* The stream map for each platform consists of an array of the below |
57 | * stream map structure. |
58 | */ |
59 | struct sst_dev_stream_map { |
60 | u8 dev_num; /* device id */ |
61 | u8 subdev_num; /* substream */ |
62 | u8 direction; |
63 | u8 device_id; /* fw id */ |
64 | u8 task_id; /* fw task */ |
65 | u8 status; |
66 | }; |
67 | |
68 | struct sst_platform_data { |
69 | /* Intel software platform id*/ |
70 | struct sst_dev_stream_map *pdev_strm_map; |
71 | unsigned int strm_map_size; |
72 | }; |
73 | |
74 | struct sst_info { |
75 | u32 iram_start; |
76 | u32 iram_end; |
77 | bool iram_use; |
78 | u32 dram_start; |
79 | u32 dram_end; |
80 | bool dram_use; |
81 | u32 imr_start; |
82 | u32 imr_end; |
83 | bool imr_use; |
84 | u32 mailbox_start; |
85 | bool use_elf; |
86 | bool lpe_viewpt_rqd; |
87 | unsigned int max_streams; |
88 | u32 dma_max_len; |
89 | u8 num_probes; |
90 | }; |
91 | |
92 | struct sst_lib_dnld_info { |
93 | unsigned int mod_base; |
94 | unsigned int mod_end; |
95 | unsigned int mod_table_offset; |
96 | unsigned int mod_table_size; |
97 | bool mod_ddr_dnld; |
98 | }; |
99 | |
100 | struct sst_res_info { |
101 | unsigned int shim_offset; |
102 | unsigned int shim_size; |
103 | unsigned int shim_phy_addr; |
104 | unsigned int ssp0_offset; |
105 | unsigned int ssp0_size; |
106 | unsigned int dma0_offset; |
107 | unsigned int dma0_size; |
108 | unsigned int dma1_offset; |
109 | unsigned int dma1_size; |
110 | unsigned int iram_offset; |
111 | unsigned int iram_size; |
112 | unsigned int dram_offset; |
113 | unsigned int dram_size; |
114 | unsigned int mbox_offset; |
115 | unsigned int mbox_size; |
116 | unsigned int acpi_lpe_res_index; |
117 | unsigned int acpi_ddr_index; |
118 | unsigned int acpi_ipc_irq_index; |
119 | }; |
120 | |
121 | struct sst_ipc_info { |
122 | int ipc_offset; |
123 | unsigned int mbox_recv_off; |
124 | }; |
125 | |
126 | struct sst_platform_info { |
127 | const struct sst_info *probe_data; |
128 | const struct sst_ipc_info *ipc_info; |
129 | const struct sst_res_info *res_info; |
130 | const struct sst_lib_dnld_info *lib_info; |
131 | const char *platform; |
132 | bool streams_lost_on_suspend; |
133 | }; |
134 | int add_sst_platform_device(void); |
135 | #endif |
136 | |
137 |
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