1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_X86_PROCESSOR_FLAGS_H
3#define _ASM_X86_PROCESSOR_FLAGS_H
4
5#include <uapi/asm/processor-flags.h>
6#include <linux/mem_encrypt.h>
7
8#ifdef CONFIG_VM86
9#define X86_VM_MASK X86_EFLAGS_VM
10#else
11#define X86_VM_MASK 0 /* No VM86 support */
12#endif
13
14/*
15 * CR3's layout varies depending on several things.
16 *
17 * If CR4.PCIDE is set (64-bit only), then CR3[11:0] is the address space ID.
18 * If PAE is enabled, then CR3[11:5] is part of the PDPT address
19 * (i.e. it's 32-byte aligned, not page-aligned) and CR3[4:0] is ignored.
20 * Otherwise (non-PAE, non-PCID), CR3[3] is PWT, CR3[4] is PCD, and
21 * CR3[2:0] and CR3[11:5] are ignored.
22 *
23 * In all cases, Linux puts zeros in the low ignored bits and in PWT and PCD.
24 *
25 * CR3[63] is always read as zero. If CR4.PCIDE is set, then CR3[63] may be
26 * written as 1 to prevent the write to CR3 from flushing the TLB.
27 *
28 * On systems with SME, one bit (in a variable position!) is stolen to indicate
29 * that the top-level paging structure is encrypted.
30 *
31 * All of the remaining bits indicate the physical address of the top-level
32 * paging structure.
33 *
34 * CR3_ADDR_MASK is the mask used by read_cr3_pa().
35 */
36#ifdef CONFIG_X86_64
37/* Mask off the address space ID and SME encryption bits. */
38#define CR3_ADDR_MASK __sme_clr(0x7FFFFFFFFFFFF000ull)
39#define CR3_PCID_MASK 0xFFFull
40#define CR3_NOFLUSH BIT_ULL(63)
41
42#else
43/*
44 * CR3_ADDR_MASK needs at least bits 31:5 set on PAE systems, and we save
45 * a tiny bit of code size by setting all the bits.
46 */
47#define CR3_ADDR_MASK 0xFFFFFFFFull
48#define CR3_PCID_MASK 0ull
49#define CR3_NOFLUSH 0
50#endif
51
52#ifdef CONFIG_PAGE_TABLE_ISOLATION
53# define X86_CR3_PTI_PCID_USER_BIT 11
54#endif
55
56#endif /* _ASM_X86_PROCESSOR_FLAGS_H */
57