1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_X86_PROCESSOR_H
3#define _ASM_X86_PROCESSOR_H
4
5#include <asm/processor-flags.h>
6
7/* Forward declaration, a strange C thing */
8struct task_struct;
9struct mm_struct;
10struct vm86;
11
12#include <asm/math_emu.h>
13#include <asm/segment.h>
14#include <asm/types.h>
15#include <uapi/asm/sigcontext.h>
16#include <asm/current.h>
17#include <asm/cpufeatures.h>
18#include <asm/page.h>
19#include <asm/pgtable_types.h>
20#include <asm/percpu.h>
21#include <asm/msr.h>
22#include <asm/desc_defs.h>
23#include <asm/nops.h>
24#include <asm/special_insns.h>
25#include <asm/fpu/types.h>
26#include <asm/unwind_hints.h>
27
28#include <linux/personality.h>
29#include <linux/cache.h>
30#include <linux/threads.h>
31#include <linux/math64.h>
32#include <linux/err.h>
33#include <linux/irqflags.h>
34#include <linux/mem_encrypt.h>
35
36/*
37 * We handle most unaligned accesses in hardware. On the other hand
38 * unaligned DMA can be quite expensive on some Nehalem processors.
39 *
40 * Based on this we disable the IP header alignment in network drivers.
41 */
42#define NET_IP_ALIGN 0
43
44#define HBP_NUM 4
45/*
46 * Default implementation of macro that returns current
47 * instruction pointer ("program counter").
48 */
49static inline void *current_text_addr(void)
50{
51 void *pc;
52
53 asm volatile("mov $1f, %0; 1:":"=r" (pc));
54
55 return pc;
56}
57
58/*
59 * These alignment constraints are for performance in the vSMP case,
60 * but in the task_struct case we must also meet hardware imposed
61 * alignment requirements of the FPU state:
62 */
63#ifdef CONFIG_X86_VSMP
64# define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
65# define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
66#else
67# define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state)
68# define ARCH_MIN_MMSTRUCT_ALIGN 0
69#endif
70
71enum tlb_infos {
72 ENTRIES,
73 NR_INFO
74};
75
76extern u16 __read_mostly tlb_lli_4k[NR_INFO];
77extern u16 __read_mostly tlb_lli_2m[NR_INFO];
78extern u16 __read_mostly tlb_lli_4m[NR_INFO];
79extern u16 __read_mostly tlb_lld_4k[NR_INFO];
80extern u16 __read_mostly tlb_lld_2m[NR_INFO];
81extern u16 __read_mostly tlb_lld_4m[NR_INFO];
82extern u16 __read_mostly tlb_lld_1g[NR_INFO];
83
84/*
85 * CPU type and hardware bug flags. Kept separately for each CPU.
86 * Members of this structure are referenced in head_32.S, so think twice
87 * before touching them. [mj]
88 */
89
90struct cpuinfo_x86 {
91 __u8 x86; /* CPU family */
92 __u8 x86_vendor; /* CPU vendor */
93 __u8 x86_model;
94 __u8 x86_stepping;
95#ifdef CONFIG_X86_64
96 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
97 int x86_tlbsize;
98#endif
99 __u8 x86_virt_bits;
100 __u8 x86_phys_bits;
101 /* CPUID returned core id bits: */
102 __u8 x86_coreid_bits;
103 __u8 cu_id;
104 /* Max extended CPUID function supported: */
105 __u32 extended_cpuid_level;
106 /* Maximum supported CPUID level, -1=no CPUID: */
107 int cpuid_level;
108 __u32 x86_capability[NCAPINTS + NBUGINTS];
109 char x86_vendor_id[16];
110 char x86_model_id[64];
111 /* in KB - valid for CPUS which support this call: */
112 unsigned int x86_cache_size;
113 int x86_cache_alignment; /* In bytes */
114 /* Cache QoS architectural values: */
115 int x86_cache_max_rmid; /* max index */
116 int x86_cache_occ_scale; /* scale to bytes */
117 int x86_power;
118 unsigned long loops_per_jiffy;
119 /* cpuid returned max cores value: */
120 u16 x86_max_cores;
121 u16 apicid;
122 u16 initial_apicid;
123 u16 x86_clflush_size;
124 /* number of cores as seen by the OS: */
125 u16 booted_cores;
126 /* Physical processor id: */
127 u16 phys_proc_id;
128 /* Logical processor id: */
129 u16 logical_proc_id;
130 /* Core id: */
131 u16 cpu_core_id;
132 /* Index into per_cpu list: */
133 u16 cpu_index;
134 u32 microcode;
135 unsigned initialized : 1;
136} __randomize_layout;
137
138struct cpuid_regs {
139 u32 eax, ebx, ecx, edx;
140};
141
142enum cpuid_regs_idx {
143 CPUID_EAX = 0,
144 CPUID_EBX,
145 CPUID_ECX,
146 CPUID_EDX,
147};
148
149#define X86_VENDOR_INTEL 0
150#define X86_VENDOR_CYRIX 1
151#define X86_VENDOR_AMD 2
152#define X86_VENDOR_UMC 3
153#define X86_VENDOR_CENTAUR 5
154#define X86_VENDOR_TRANSMETA 7
155#define X86_VENDOR_NSC 8
156#define X86_VENDOR_NUM 9
157
158#define X86_VENDOR_UNKNOWN 0xff
159
160/*
161 * capabilities of CPUs
162 */
163extern struct cpuinfo_x86 boot_cpu_data;
164extern struct cpuinfo_x86 new_cpu_data;
165
166extern struct x86_hw_tss doublefault_tss;
167extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS];
168extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS];
169
170#ifdef CONFIG_SMP
171DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
172#define cpu_data(cpu) per_cpu(cpu_info, cpu)
173#else
174#define cpu_info boot_cpu_data
175#define cpu_data(cpu) boot_cpu_data
176#endif
177
178extern const struct seq_operations cpuinfo_op;
179
180#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
181
182extern void cpu_detect(struct cpuinfo_x86 *c);
183
184static inline unsigned long l1tf_pfn_limit(void)
185{
186 return BIT(boot_cpu_data.x86_phys_bits - 1 - PAGE_SHIFT) - 1;
187}
188
189extern void early_cpu_init(void);
190extern void identify_boot_cpu(void);
191extern void identify_secondary_cpu(struct cpuinfo_x86 *);
192extern void print_cpu_info(struct cpuinfo_x86 *);
193void print_cpu_msr(struct cpuinfo_x86 *);
194
195#ifdef CONFIG_X86_32
196extern int have_cpuid_p(void);
197#else
198static inline int have_cpuid_p(void)
199{
200 return 1;
201}
202#endif
203static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
204 unsigned int *ecx, unsigned int *edx)
205{
206 /* ecx is often an input as well as an output. */
207 asm volatile("cpuid"
208 : "=a" (*eax),
209 "=b" (*ebx),
210 "=c" (*ecx),
211 "=d" (*edx)
212 : "0" (*eax), "2" (*ecx)
213 : "memory");
214}
215
216#define native_cpuid_reg(reg) \
217static inline unsigned int native_cpuid_##reg(unsigned int op) \
218{ \
219 unsigned int eax = op, ebx, ecx = 0, edx; \
220 \
221 native_cpuid(&eax, &ebx, &ecx, &edx); \
222 \
223 return reg; \
224}
225
226/*
227 * Native CPUID functions returning a single datum.
228 */
229native_cpuid_reg(eax)
230native_cpuid_reg(ebx)
231native_cpuid_reg(ecx)
232native_cpuid_reg(edx)
233
234/*
235 * Friendlier CR3 helpers.
236 */
237static inline unsigned long read_cr3_pa(void)
238{
239 return __read_cr3() & CR3_ADDR_MASK;
240}
241
242static inline unsigned long native_read_cr3_pa(void)
243{
244 return __native_read_cr3() & CR3_ADDR_MASK;
245}
246
247static inline void load_cr3(pgd_t *pgdir)
248{
249 write_cr3(__sme_pa(pgdir));
250}
251
252/*
253 * Note that while the legacy 'TSS' name comes from 'Task State Segment',
254 * on modern x86 CPUs the TSS also holds information important to 64-bit mode,
255 * unrelated to the task-switch mechanism:
256 */
257#ifdef CONFIG_X86_32
258/* This is the TSS defined by the hardware. */
259struct x86_hw_tss {
260 unsigned short back_link, __blh;
261 unsigned long sp0;
262 unsigned short ss0, __ss0h;
263 unsigned long sp1;
264
265 /*
266 * We don't use ring 1, so ss1 is a convenient scratch space in
267 * the same cacheline as sp0. We use ss1 to cache the value in
268 * MSR_IA32_SYSENTER_CS. When we context switch
269 * MSR_IA32_SYSENTER_CS, we first check if the new value being
270 * written matches ss1, and, if it's not, then we wrmsr the new
271 * value and update ss1.
272 *
273 * The only reason we context switch MSR_IA32_SYSENTER_CS is
274 * that we set it to zero in vm86 tasks to avoid corrupting the
275 * stack if we were to go through the sysenter path from vm86
276 * mode.
277 */
278 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */
279
280 unsigned short __ss1h;
281 unsigned long sp2;
282 unsigned short ss2, __ss2h;
283 unsigned long __cr3;
284 unsigned long ip;
285 unsigned long flags;
286 unsigned long ax;
287 unsigned long cx;
288 unsigned long dx;
289 unsigned long bx;
290 unsigned long sp;
291 unsigned long bp;
292 unsigned long si;
293 unsigned long di;
294 unsigned short es, __esh;
295 unsigned short cs, __csh;
296 unsigned short ss, __ssh;
297 unsigned short ds, __dsh;
298 unsigned short fs, __fsh;
299 unsigned short gs, __gsh;
300 unsigned short ldt, __ldth;
301 unsigned short trace;
302 unsigned short io_bitmap_base;
303
304} __attribute__((packed));
305#else
306struct x86_hw_tss {
307 u32 reserved1;
308 u64 sp0;
309
310 /*
311 * We store cpu_current_top_of_stack in sp1 so it's always accessible.
312 * Linux does not use ring 1, so sp1 is not otherwise needed.
313 */
314 u64 sp1;
315
316 u64 sp2;
317 u64 reserved2;
318 u64 ist[7];
319 u32 reserved3;
320 u32 reserved4;
321 u16 reserved5;
322 u16 io_bitmap_base;
323
324} __attribute__((packed));
325#endif
326
327/*
328 * IO-bitmap sizes:
329 */
330#define IO_BITMAP_BITS 65536
331#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
332#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
333#define IO_BITMAP_OFFSET (offsetof(struct tss_struct, io_bitmap) - offsetof(struct tss_struct, x86_tss))
334#define INVALID_IO_BITMAP_OFFSET 0x8000
335
336struct entry_stack {
337 unsigned long words[64];
338};
339
340struct entry_stack_page {
341 struct entry_stack stack;
342} __aligned(PAGE_SIZE);
343
344struct tss_struct {
345 /*
346 * The fixed hardware portion. This must not cross a page boundary
347 * at risk of violating the SDM's advice and potentially triggering
348 * errata.
349 */
350 struct x86_hw_tss x86_tss;
351
352 /*
353 * The extra 1 is there because the CPU will access an
354 * additional byte beyond the end of the IO permission
355 * bitmap. The extra byte must be all 1 bits, and must
356 * be within the limit.
357 */
358 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
359} __aligned(PAGE_SIZE);
360
361DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw);
362
363/*
364 * sizeof(unsigned long) coming from an extra "long" at the end
365 * of the iobitmap.
366 *
367 * -1? seg base+limit should be pointing to the address of the
368 * last valid byte
369 */
370#define __KERNEL_TSS_LIMIT \
371 (IO_BITMAP_OFFSET + IO_BITMAP_BYTES + sizeof(unsigned long) - 1)
372
373#ifdef CONFIG_X86_32
374DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack);
375#else
376/* The RO copy can't be accessed with this_cpu_xyz(), so use the RW copy. */
377#define cpu_current_top_of_stack cpu_tss_rw.x86_tss.sp1
378#endif
379
380/*
381 * Save the original ist values for checking stack pointers during debugging
382 */
383struct orig_ist {
384 unsigned long ist[7];
385};
386
387#ifdef CONFIG_X86_64
388DECLARE_PER_CPU(struct orig_ist, orig_ist);
389
390union irq_stack_union {
391 char irq_stack[IRQ_STACK_SIZE];
392 /*
393 * GCC hardcodes the stack canary as %gs:40. Since the
394 * irq_stack is the object at %gs:0, we reserve the bottom
395 * 48 bytes of the irq stack for the canary.
396 */
397 struct {
398 char gs_base[40];
399 unsigned long stack_canary;
400 };
401};
402
403DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible;
404DECLARE_INIT_PER_CPU(irq_stack_union);
405
406static inline unsigned long cpu_kernelmode_gs_base(int cpu)
407{
408 return (unsigned long)per_cpu(irq_stack_union.gs_base, cpu);
409}
410
411DECLARE_PER_CPU(char *, irq_stack_ptr);
412DECLARE_PER_CPU(unsigned int, irq_count);
413extern asmlinkage void ignore_sysret(void);
414
415#if IS_ENABLED(CONFIG_KVM)
416/* Save actual FS/GS selectors and bases to current->thread */
417void save_fsgs_for_kvm(void);
418#endif
419#else /* X86_64 */
420#ifdef CONFIG_STACKPROTECTOR
421/*
422 * Make sure stack canary segment base is cached-aligned:
423 * "For Intel Atom processors, avoid non zero segment base address
424 * that is not aligned to cache line boundary at all cost."
425 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
426 */
427struct stack_canary {
428 char __pad[20]; /* canary at %gs:20 */
429 unsigned long canary;
430};
431DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
432#endif
433/*
434 * per-CPU IRQ handling stacks
435 */
436struct irq_stack {
437 u32 stack[THREAD_SIZE/sizeof(u32)];
438} __aligned(THREAD_SIZE);
439
440DECLARE_PER_CPU(struct irq_stack *, hardirq_stack);
441DECLARE_PER_CPU(struct irq_stack *, softirq_stack);
442#endif /* X86_64 */
443
444extern unsigned int fpu_kernel_xstate_size;
445extern unsigned int fpu_user_xstate_size;
446
447struct perf_event;
448
449typedef struct {
450 unsigned long seg;
451} mm_segment_t;
452
453struct thread_struct {
454 /* Cached TLS descriptors: */
455 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
456#ifdef CONFIG_X86_32
457 unsigned long sp0;
458#endif
459 unsigned long sp;
460#ifdef CONFIG_X86_32
461 unsigned long sysenter_cs;
462#else
463 unsigned short es;
464 unsigned short ds;
465 unsigned short fsindex;
466 unsigned short gsindex;
467#endif
468
469#ifdef CONFIG_X86_64
470 unsigned long fsbase;
471 unsigned long gsbase;
472#else
473 /*
474 * XXX: this could presumably be unsigned short. Alternatively,
475 * 32-bit kernels could be taught to use fsindex instead.
476 */
477 unsigned long fs;
478 unsigned long gs;
479#endif
480
481 /* Save middle states of ptrace breakpoints */
482 struct perf_event *ptrace_bps[HBP_NUM];
483 /* Debug status used for traps, single steps, etc... */
484 unsigned long debugreg6;
485 /* Keep track of the exact dr7 value set by the user */
486 unsigned long ptrace_dr7;
487 /* Fault info: */
488 unsigned long cr2;
489 unsigned long trap_nr;
490 unsigned long error_code;
491#ifdef CONFIG_VM86
492 /* Virtual 86 mode info */
493 struct vm86 *vm86;
494#endif
495 /* IO permissions: */
496 unsigned long *io_bitmap_ptr;
497 unsigned long iopl;
498 /* Max allowed port in the bitmap, in bytes: */
499 unsigned io_bitmap_max;
500
501 mm_segment_t addr_limit;
502
503 unsigned int sig_on_uaccess_err:1;
504 unsigned int uaccess_err:1; /* uaccess failed */
505
506 /* Floating point and extended processor state */
507 struct fpu fpu;
508 /*
509 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at
510 * the end.
511 */
512};
513
514/* Whitelist the FPU state from the task_struct for hardened usercopy. */
515static inline void arch_thread_struct_whitelist(unsigned long *offset,
516 unsigned long *size)
517{
518 *offset = offsetof(struct thread_struct, fpu.state);
519 *size = fpu_kernel_xstate_size;
520}
521
522/*
523 * Thread-synchronous status.
524 *
525 * This is different from the flags in that nobody else
526 * ever touches our thread-synchronous status, so we don't
527 * have to worry about atomic accesses.
528 */
529#define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/
530
531/*
532 * Set IOPL bits in EFLAGS from given mask
533 */
534static inline void native_set_iopl_mask(unsigned mask)
535{
536#ifdef CONFIG_X86_32
537 unsigned int reg;
538
539 asm volatile ("pushfl;"
540 "popl %0;"
541 "andl %1, %0;"
542 "orl %2, %0;"
543 "pushl %0;"
544 "popfl"
545 : "=&r" (reg)
546 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
547#endif
548}
549
550static inline void
551native_load_sp0(unsigned long sp0)
552{
553 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0);
554}
555
556static inline void native_swapgs(void)
557{
558#ifdef CONFIG_X86_64
559 asm volatile("swapgs" ::: "memory");
560#endif
561}
562
563static inline unsigned long current_top_of_stack(void)
564{
565 /*
566 * We can't read directly from tss.sp0: sp0 on x86_32 is special in
567 * and around vm86 mode and sp0 on x86_64 is special because of the
568 * entry trampoline.
569 */
570 return this_cpu_read_stable(cpu_current_top_of_stack);
571}
572
573static inline bool on_thread_stack(void)
574{
575 return (unsigned long)(current_top_of_stack() -
576 current_stack_pointer) < THREAD_SIZE;
577}
578
579#ifdef CONFIG_PARAVIRT
580#include <asm/paravirt.h>
581#else
582#define __cpuid native_cpuid
583
584static inline void load_sp0(unsigned long sp0)
585{
586 native_load_sp0(sp0);
587}
588
589#define set_iopl_mask native_set_iopl_mask
590#endif /* CONFIG_PARAVIRT */
591
592/* Free all resources held by a thread. */
593extern void release_thread(struct task_struct *);
594
595unsigned long get_wchan(struct task_struct *p);
596
597/*
598 * Generic CPUID function
599 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
600 * resulting in stale register contents being returned.
601 */
602static inline void cpuid(unsigned int op,
603 unsigned int *eax, unsigned int *ebx,
604 unsigned int *ecx, unsigned int *edx)
605{
606 *eax = op;
607 *ecx = 0;
608 __cpuid(eax, ebx, ecx, edx);
609}
610
611/* Some CPUID calls want 'count' to be placed in ecx */
612static inline void cpuid_count(unsigned int op, int count,
613 unsigned int *eax, unsigned int *ebx,
614 unsigned int *ecx, unsigned int *edx)
615{
616 *eax = op;
617 *ecx = count;
618 __cpuid(eax, ebx, ecx, edx);
619}
620
621/*
622 * CPUID functions returning a single datum
623 */
624static inline unsigned int cpuid_eax(unsigned int op)
625{
626 unsigned int eax, ebx, ecx, edx;
627
628 cpuid(op, &eax, &ebx, &ecx, &edx);
629
630 return eax;
631}
632
633static inline unsigned int cpuid_ebx(unsigned int op)
634{
635 unsigned int eax, ebx, ecx, edx;
636
637 cpuid(op, &eax, &ebx, &ecx, &edx);
638
639 return ebx;
640}
641
642static inline unsigned int cpuid_ecx(unsigned int op)
643{
644 unsigned int eax, ebx, ecx, edx;
645
646 cpuid(op, &eax, &ebx, &ecx, &edx);
647
648 return ecx;
649}
650
651static inline unsigned int cpuid_edx(unsigned int op)
652{
653 unsigned int eax, ebx, ecx, edx;
654
655 cpuid(op, &eax, &ebx, &ecx, &edx);
656
657 return edx;
658}
659
660/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
661static __always_inline void rep_nop(void)
662{
663 asm volatile("rep; nop" ::: "memory");
664}
665
666static __always_inline void cpu_relax(void)
667{
668 rep_nop();
669}
670
671/*
672 * This function forces the icache and prefetched instruction stream to
673 * catch up with reality in two very specific cases:
674 *
675 * a) Text was modified using one virtual address and is about to be executed
676 * from the same physical page at a different virtual address.
677 *
678 * b) Text was modified on a different CPU, may subsequently be
679 * executed on this CPU, and you want to make sure the new version
680 * gets executed. This generally means you're calling this in a IPI.
681 *
682 * If you're calling this for a different reason, you're probably doing
683 * it wrong.
684 */
685static inline void sync_core(void)
686{
687 /*
688 * There are quite a few ways to do this. IRET-to-self is nice
689 * because it works on every CPU, at any CPL (so it's compatible
690 * with paravirtualization), and it never exits to a hypervisor.
691 * The only down sides are that it's a bit slow (it seems to be
692 * a bit more than 2x slower than the fastest options) and that
693 * it unmasks NMIs. The "push %cs" is needed because, in
694 * paravirtual environments, __KERNEL_CS may not be a valid CS
695 * value when we do IRET directly.
696 *
697 * In case NMI unmasking or performance ever becomes a problem,
698 * the next best option appears to be MOV-to-CR2 and an
699 * unconditional jump. That sequence also works on all CPUs,
700 * but it will fault at CPL3 (i.e. Xen PV).
701 *
702 * CPUID is the conventional way, but it's nasty: it doesn't
703 * exist on some 486-like CPUs, and it usually exits to a
704 * hypervisor.
705 *
706 * Like all of Linux's memory ordering operations, this is a
707 * compiler barrier as well.
708 */
709#ifdef CONFIG_X86_32
710 asm volatile (
711 "pushfl\n\t"
712 "pushl %%cs\n\t"
713 "pushl $1f\n\t"
714 "iret\n\t"
715 "1:"
716 : ASM_CALL_CONSTRAINT : : "memory");
717#else
718 unsigned int tmp;
719
720 asm volatile (
721 UNWIND_HINT_SAVE
722 "mov %%ss, %0\n\t"
723 "pushq %q0\n\t"
724 "pushq %%rsp\n\t"
725 "addq $8, (%%rsp)\n\t"
726 "pushfq\n\t"
727 "mov %%cs, %0\n\t"
728 "pushq %q0\n\t"
729 "pushq $1f\n\t"
730 "iretq\n\t"
731 UNWIND_HINT_RESTORE
732 "1:"
733 : "=&r" (tmp), ASM_CALL_CONSTRAINT : : "cc", "memory");
734#endif
735}
736
737extern void select_idle_routine(const struct cpuinfo_x86 *c);
738extern void amd_e400_c1e_apic_setup(void);
739
740extern unsigned long boot_option_idle_override;
741
742enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
743 IDLE_POLL};
744
745extern void enable_sep_cpu(void);
746extern int sysenter_setup(void);
747
748void early_trap_pf_init(void);
749
750/* Defined in head.S */
751extern struct desc_ptr early_gdt_descr;
752
753extern void switch_to_new_gdt(int);
754extern void load_direct_gdt(int);
755extern void load_fixmap_gdt(int);
756extern void load_percpu_segment(int);
757extern void cpu_init(void);
758
759static inline unsigned long get_debugctlmsr(void)
760{
761 unsigned long debugctlmsr = 0;
762
763#ifndef CONFIG_X86_DEBUGCTLMSR
764 if (boot_cpu_data.x86 < 6)
765 return 0;
766#endif
767 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
768
769 return debugctlmsr;
770}
771
772static inline void update_debugctlmsr(unsigned long debugctlmsr)
773{
774#ifndef CONFIG_X86_DEBUGCTLMSR
775 if (boot_cpu_data.x86 < 6)
776 return;
777#endif
778 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
779}
780
781extern void set_task_blockstep(struct task_struct *task, bool on);
782
783/* Boot loader type from the setup header: */
784extern int bootloader_type;
785extern int bootloader_version;
786
787extern char ignore_fpu_irq;
788
789#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
790#define ARCH_HAS_PREFETCHW
791#define ARCH_HAS_SPINLOCK_PREFETCH
792
793#ifdef CONFIG_X86_32
794# define BASE_PREFETCH ""
795# define ARCH_HAS_PREFETCH
796#else
797# define BASE_PREFETCH "prefetcht0 %P1"
798#endif
799
800/*
801 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
802 *
803 * It's not worth to care about 3dnow prefetches for the K6
804 * because they are microcoded there and very slow.
805 */
806static inline void prefetch(const void *x)
807{
808 alternative_input(BASE_PREFETCH, "prefetchnta %P1",
809 X86_FEATURE_XMM,
810 "m" (*(const char *)x));
811}
812
813/*
814 * 3dnow prefetch to get an exclusive cache line.
815 * Useful for spinlocks to avoid one state transition in the
816 * cache coherency protocol:
817 */
818static inline void prefetchw(const void *x)
819{
820 alternative_input(BASE_PREFETCH, "prefetchw %P1",
821 X86_FEATURE_3DNOWPREFETCH,
822 "m" (*(const char *)x));
823}
824
825static inline void spin_lock_prefetch(const void *x)
826{
827 prefetchw(x);
828}
829
830#define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
831 TOP_OF_KERNEL_STACK_PADDING)
832
833#define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1))
834
835#define task_pt_regs(task) \
836({ \
837 unsigned long __ptr = (unsigned long)task_stack_page(task); \
838 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \
839 ((struct pt_regs *)__ptr) - 1; \
840})
841
842#ifdef CONFIG_X86_32
843/*
844 * User space process size: 3GB (default).
845 */
846#define IA32_PAGE_OFFSET PAGE_OFFSET
847#define TASK_SIZE PAGE_OFFSET
848#define TASK_SIZE_LOW TASK_SIZE
849#define TASK_SIZE_MAX TASK_SIZE
850#define DEFAULT_MAP_WINDOW TASK_SIZE
851#define STACK_TOP TASK_SIZE
852#define STACK_TOP_MAX STACK_TOP
853
854#define INIT_THREAD { \
855 .sp0 = TOP_OF_INIT_STACK, \
856 .sysenter_cs = __KERNEL_CS, \
857 .io_bitmap_ptr = NULL, \
858 .addr_limit = KERNEL_DS, \
859}
860
861#define KSTK_ESP(task) (task_pt_regs(task)->sp)
862
863#else
864/*
865 * User space process size. This is the first address outside the user range.
866 * There are a few constraints that determine this:
867 *
868 * On Intel CPUs, if a SYSCALL instruction is at the highest canonical
869 * address, then that syscall will enter the kernel with a
870 * non-canonical return address, and SYSRET will explode dangerously.
871 * We avoid this particular problem by preventing anything executable
872 * from being mapped at the maximum canonical address.
873 *
874 * On AMD CPUs in the Ryzen family, there's a nasty bug in which the
875 * CPUs malfunction if they execute code from the highest canonical page.
876 * They'll speculate right off the end of the canonical space, and
877 * bad things happen. This is worked around in the same way as the
878 * Intel problem.
879 *
880 * With page table isolation enabled, we map the LDT in ... [stay tuned]
881 */
882#define TASK_SIZE_MAX ((1UL << __VIRTUAL_MASK_SHIFT) - PAGE_SIZE)
883
884#define DEFAULT_MAP_WINDOW ((1UL << 47) - PAGE_SIZE)
885
886/* This decides where the kernel will search for a free chunk of vm
887 * space during mmap's.
888 */
889#define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
890 0xc0000000 : 0xFFFFe000)
891
892#define TASK_SIZE_LOW (test_thread_flag(TIF_ADDR32) ? \
893 IA32_PAGE_OFFSET : DEFAULT_MAP_WINDOW)
894#define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
895 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
896#define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
897 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
898
899#define STACK_TOP TASK_SIZE_LOW
900#define STACK_TOP_MAX TASK_SIZE_MAX
901
902#define INIT_THREAD { \
903 .addr_limit = KERNEL_DS, \
904}
905
906extern unsigned long KSTK_ESP(struct task_struct *task);
907
908#endif /* CONFIG_X86_64 */
909
910extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
911 unsigned long new_sp);
912
913/*
914 * This decides where the kernel will search for a free chunk of vm
915 * space during mmap's.
916 */
917#define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3))
918#define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE_LOW)
919
920#define KSTK_EIP(task) (task_pt_regs(task)->ip)
921
922/* Get/set a process' ability to use the timestamp counter instruction */
923#define GET_TSC_CTL(adr) get_tsc_mode((adr))
924#define SET_TSC_CTL(val) set_tsc_mode((val))
925
926extern int get_tsc_mode(unsigned long adr);
927extern int set_tsc_mode(unsigned int val);
928
929DECLARE_PER_CPU(u64, msr_misc_features_shadow);
930
931/* Register/unregister a process' MPX related resource */
932#define MPX_ENABLE_MANAGEMENT() mpx_enable_management()
933#define MPX_DISABLE_MANAGEMENT() mpx_disable_management()
934
935#ifdef CONFIG_X86_INTEL_MPX
936extern int mpx_enable_management(void);
937extern int mpx_disable_management(void);
938#else
939static inline int mpx_enable_management(void)
940{
941 return -EINVAL;
942}
943static inline int mpx_disable_management(void)
944{
945 return -EINVAL;
946}
947#endif /* CONFIG_X86_INTEL_MPX */
948
949#ifdef CONFIG_CPU_SUP_AMD
950extern u16 amd_get_nb_id(int cpu);
951extern u32 amd_get_nodes_per_socket(void);
952#else
953static inline u16 amd_get_nb_id(int cpu) { return 0; }
954static inline u32 amd_get_nodes_per_socket(void) { return 0; }
955#endif
956
957static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
958{
959 uint32_t base, eax, signature[3];
960
961 for (base = 0x40000000; base < 0x40010000; base += 0x100) {
962 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);
963
964 if (!memcmp(sig, signature, 12) &&
965 (leaves == 0 || ((eax - base) >= leaves)))
966 return base;
967 }
968
969 return 0;
970}
971
972extern unsigned long arch_align_stack(unsigned long sp);
973extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
974extern void free_kernel_image_pages(void *begin, void *end);
975
976void default_idle(void);
977#ifdef CONFIG_XEN
978bool xen_set_default_idle(void);
979#else
980#define xen_set_default_idle 0
981#endif
982
983void stop_this_cpu(void *dummy);
984void df_debug(struct pt_regs *regs, long error_code);
985void microcode_check(void);
986
987enum l1tf_mitigations {
988 L1TF_MITIGATION_OFF,
989 L1TF_MITIGATION_FLUSH_NOWARN,
990 L1TF_MITIGATION_FLUSH,
991 L1TF_MITIGATION_FLUSH_NOSMT,
992 L1TF_MITIGATION_FULL,
993 L1TF_MITIGATION_FULL_FORCE
994};
995
996extern enum l1tf_mitigations l1tf_mitigation;
997
998#endif /* _ASM_X86_PROCESSOR_H */
999