1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_X86_TLBFLUSH_H
3#define _ASM_X86_TLBFLUSH_H
4
5#include <linux/mm.h>
6#include <linux/sched.h>
7
8#include <asm/processor.h>
9#include <asm/cpufeature.h>
10#include <asm/special_insns.h>
11#include <asm/smp.h>
12#include <asm/invpcid.h>
13#include <asm/pti.h>
14#include <asm/processor-flags.h>
15
16/*
17 * The x86 feature is called PCID (Process Context IDentifier). It is similar
18 * to what is traditionally called ASID on the RISC processors.
19 *
20 * We don't use the traditional ASID implementation, where each process/mm gets
21 * its own ASID and flush/restart when we run out of ASID space.
22 *
23 * Instead we have a small per-cpu array of ASIDs and cache the last few mm's
24 * that came by on this CPU, allowing cheaper switch_mm between processes on
25 * this CPU.
26 *
27 * We end up with different spaces for different things. To avoid confusion we
28 * use different names for each of them:
29 *
30 * ASID - [0, TLB_NR_DYN_ASIDS-1]
31 * the canonical identifier for an mm
32 *
33 * kPCID - [1, TLB_NR_DYN_ASIDS]
34 * the value we write into the PCID part of CR3; corresponds to the
35 * ASID+1, because PCID 0 is special.
36 *
37 * uPCID - [2048 + 1, 2048 + TLB_NR_DYN_ASIDS]
38 * for KPTI each mm has two address spaces and thus needs two
39 * PCID values, but we can still do with a single ASID denomination
40 * for each mm. Corresponds to kPCID + 2048.
41 *
42 */
43
44/* There are 12 bits of space for ASIDS in CR3 */
45#define CR3_HW_ASID_BITS 12
46
47/*
48 * When enabled, PAGE_TABLE_ISOLATION consumes a single bit for
49 * user/kernel switches
50 */
51#ifdef CONFIG_PAGE_TABLE_ISOLATION
52# define PTI_CONSUMED_PCID_BITS 1
53#else
54# define PTI_CONSUMED_PCID_BITS 0
55#endif
56
57#define CR3_AVAIL_PCID_BITS (X86_CR3_PCID_BITS - PTI_CONSUMED_PCID_BITS)
58
59/*
60 * ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid. -1 below to account
61 * for them being zero-based. Another -1 is because PCID 0 is reserved for
62 * use by non-PCID-aware users.
63 */
64#define MAX_ASID_AVAILABLE ((1 << CR3_AVAIL_PCID_BITS) - 2)
65
66/*
67 * 6 because 6 should be plenty and struct tlb_state will fit in two cache
68 * lines.
69 */
70#define TLB_NR_DYN_ASIDS 6
71
72/*
73 * Given @asid, compute kPCID
74 */
75static inline u16 kern_pcid(u16 asid)
76{
77 VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
78
79#ifdef CONFIG_PAGE_TABLE_ISOLATION
80 /*
81 * Make sure that the dynamic ASID space does not confict with the
82 * bit we are using to switch between user and kernel ASIDs.
83 */
84 BUILD_BUG_ON(TLB_NR_DYN_ASIDS >= (1 << X86_CR3_PTI_PCID_USER_BIT));
85
86 /*
87 * The ASID being passed in here should have respected the
88 * MAX_ASID_AVAILABLE and thus never have the switch bit set.
89 */
90 VM_WARN_ON_ONCE(asid & (1 << X86_CR3_PTI_PCID_USER_BIT));
91#endif
92 /*
93 * The dynamically-assigned ASIDs that get passed in are small
94 * (<TLB_NR_DYN_ASIDS). They never have the high switch bit set,
95 * so do not bother to clear it.
96 *
97 * If PCID is on, ASID-aware code paths put the ASID+1 into the
98 * PCID bits. This serves two purposes. It prevents a nasty
99 * situation in which PCID-unaware code saves CR3, loads some other
100 * value (with PCID == 0), and then restores CR3, thus corrupting
101 * the TLB for ASID 0 if the saved ASID was nonzero. It also means
102 * that any bugs involving loading a PCID-enabled CR3 with
103 * CR4.PCIDE off will trigger deterministically.
104 */
105 return asid + 1;
106}
107
108/*
109 * Given @asid, compute uPCID
110 */
111static inline u16 user_pcid(u16 asid)
112{
113 u16 ret = kern_pcid(asid);
114#ifdef CONFIG_PAGE_TABLE_ISOLATION
115 ret |= 1 << X86_CR3_PTI_PCID_USER_BIT;
116#endif
117 return ret;
118}
119
120struct pgd_t;
121static inline unsigned long build_cr3(pgd_t *pgd, u16 asid)
122{
123 if (static_cpu_has(X86_FEATURE_PCID)) {
124 return __sme_pa(pgd) | kern_pcid(asid);
125 } else {
126 VM_WARN_ON_ONCE(asid != 0);
127 return __sme_pa(pgd);
128 }
129}
130
131static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid)
132{
133 VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
134 /*
135 * Use boot_cpu_has() instead of this_cpu_has() as this function
136 * might be called during early boot. This should work even after
137 * boot because all CPU's the have same capabilities:
138 */
139 VM_WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_PCID));
140 return __sme_pa(pgd) | kern_pcid(asid) | CR3_NOFLUSH;
141}
142
143#ifdef CONFIG_PARAVIRT
144#include <asm/paravirt.h>
145#else
146#define __flush_tlb() __native_flush_tlb()
147#define __flush_tlb_global() __native_flush_tlb_global()
148#define __flush_tlb_one_user(addr) __native_flush_tlb_one_user(addr)
149#endif
150
151struct tlb_context {
152 u64 ctx_id;
153 u64 tlb_gen;
154};
155
156struct tlb_state {
157 /*
158 * cpu_tlbstate.loaded_mm should match CR3 whenever interrupts
159 * are on. This means that it may not match current->active_mm,
160 * which will contain the previous user mm when we're in lazy TLB
161 * mode even if we've already switched back to swapper_pg_dir.
162 */
163 struct mm_struct *loaded_mm;
164 u16 loaded_mm_asid;
165 u16 next_asid;
166 /* last user mm's ctx id */
167 u64 last_ctx_id;
168
169 /*
170 * We can be in one of several states:
171 *
172 * - Actively using an mm. Our CPU's bit will be set in
173 * mm_cpumask(loaded_mm) and is_lazy == false;
174 *
175 * - Not using a real mm. loaded_mm == &init_mm. Our CPU's bit
176 * will not be set in mm_cpumask(&init_mm) and is_lazy == false.
177 *
178 * - Lazily using a real mm. loaded_mm != &init_mm, our bit
179 * is set in mm_cpumask(loaded_mm), but is_lazy == true.
180 * We're heuristically guessing that the CR3 load we
181 * skipped more than makes up for the overhead added by
182 * lazy mode.
183 */
184 bool is_lazy;
185
186 /*
187 * If set we changed the page tables in such a way that we
188 * needed an invalidation of all contexts (aka. PCIDs / ASIDs).
189 * This tells us to go invalidate all the non-loaded ctxs[]
190 * on the next context switch.
191 *
192 * The current ctx was kept up-to-date as it ran and does not
193 * need to be invalidated.
194 */
195 bool invalidate_other;
196
197 /*
198 * Mask that contains TLB_NR_DYN_ASIDS+1 bits to indicate
199 * the corresponding user PCID needs a flush next time we
200 * switch to it; see SWITCH_TO_USER_CR3.
201 */
202 unsigned short user_pcid_flush_mask;
203
204 /*
205 * Access to this CR4 shadow and to H/W CR4 is protected by
206 * disabling interrupts when modifying either one.
207 */
208 unsigned long cr4;
209
210 /*
211 * This is a list of all contexts that might exist in the TLB.
212 * There is one per ASID that we use, and the ASID (what the
213 * CPU calls PCID) is the index into ctxts.
214 *
215 * For each context, ctx_id indicates which mm the TLB's user
216 * entries came from. As an invariant, the TLB will never
217 * contain entries that are out-of-date as when that mm reached
218 * the tlb_gen in the list.
219 *
220 * To be clear, this means that it's legal for the TLB code to
221 * flush the TLB without updating tlb_gen. This can happen
222 * (for now, at least) due to paravirt remote flushes.
223 *
224 * NB: context 0 is a bit special, since it's also used by
225 * various bits of init code. This is fine -- code that
226 * isn't aware of PCID will end up harmlessly flushing
227 * context 0.
228 */
229 struct tlb_context ctxs[TLB_NR_DYN_ASIDS];
230};
231DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate);
232
233/* Initialize cr4 shadow for this CPU. */
234static inline void cr4_init_shadow(void)
235{
236 this_cpu_write(cpu_tlbstate.cr4, __read_cr4());
237}
238
239static inline void __cr4_set(unsigned long cr4)
240{
241 lockdep_assert_irqs_disabled();
242 this_cpu_write(cpu_tlbstate.cr4, cr4);
243 __write_cr4(cr4);
244}
245
246/* Set in this cpu's CR4. */
247static inline void cr4_set_bits(unsigned long mask)
248{
249 unsigned long cr4, flags;
250
251 local_irq_save(flags);
252 cr4 = this_cpu_read(cpu_tlbstate.cr4);
253 if ((cr4 | mask) != cr4)
254 __cr4_set(cr4 | mask);
255 local_irq_restore(flags);
256}
257
258/* Clear in this cpu's CR4. */
259static inline void cr4_clear_bits(unsigned long mask)
260{
261 unsigned long cr4, flags;
262
263 local_irq_save(flags);
264 cr4 = this_cpu_read(cpu_tlbstate.cr4);
265 if ((cr4 & ~mask) != cr4)
266 __cr4_set(cr4 & ~mask);
267 local_irq_restore(flags);
268}
269
270static inline void cr4_toggle_bits_irqsoff(unsigned long mask)
271{
272 unsigned long cr4;
273
274 cr4 = this_cpu_read(cpu_tlbstate.cr4);
275 __cr4_set(cr4 ^ mask);
276}
277
278/* Read the CR4 shadow. */
279static inline unsigned long cr4_read_shadow(void)
280{
281 return this_cpu_read(cpu_tlbstate.cr4);
282}
283
284/*
285 * Mark all other ASIDs as invalid, preserves the current.
286 */
287static inline void invalidate_other_asid(void)
288{
289 this_cpu_write(cpu_tlbstate.invalidate_other, true);
290}
291
292/*
293 * Save some of cr4 feature set we're using (e.g. Pentium 4MB
294 * enable and PPro Global page enable), so that any CPU's that boot
295 * up after us can get the correct flags. This should only be used
296 * during boot on the boot cpu.
297 */
298extern unsigned long mmu_cr4_features;
299extern u32 *trampoline_cr4_features;
300
301static inline void cr4_set_bits_and_update_boot(unsigned long mask)
302{
303 mmu_cr4_features |= mask;
304 if (trampoline_cr4_features)
305 *trampoline_cr4_features = mmu_cr4_features;
306 cr4_set_bits(mask);
307}
308
309extern void initialize_tlbstate_and_flush(void);
310
311/*
312 * Given an ASID, flush the corresponding user ASID. We can delay this
313 * until the next time we switch to it.
314 *
315 * See SWITCH_TO_USER_CR3.
316 */
317static inline void invalidate_user_asid(u16 asid)
318{
319 /* There is no user ASID if address space separation is off */
320 if (!IS_ENABLED(CONFIG_PAGE_TABLE_ISOLATION))
321 return;
322
323 /*
324 * We only have a single ASID if PCID is off and the CR3
325 * write will have flushed it.
326 */
327 if (!cpu_feature_enabled(X86_FEATURE_PCID))
328 return;
329
330 if (!static_cpu_has(X86_FEATURE_PTI))
331 return;
332
333 __set_bit(kern_pcid(asid),
334 (unsigned long *)this_cpu_ptr(&cpu_tlbstate.user_pcid_flush_mask));
335}
336
337/*
338 * flush the entire current user mapping
339 */
340static inline void __native_flush_tlb(void)
341{
342 /*
343 * Preemption or interrupts must be disabled to protect the access
344 * to the per CPU variable and to prevent being preempted between
345 * read_cr3() and write_cr3().
346 */
347 WARN_ON_ONCE(preemptible());
348
349 invalidate_user_asid(this_cpu_read(cpu_tlbstate.loaded_mm_asid));
350
351 /* If current->mm == NULL then the read_cr3() "borrows" an mm */
352 native_write_cr3(__native_read_cr3());
353}
354
355/*
356 * flush everything
357 */
358static inline void __native_flush_tlb_global(void)
359{
360 unsigned long cr4, flags;
361
362 if (static_cpu_has(X86_FEATURE_INVPCID)) {
363 /*
364 * Using INVPCID is considerably faster than a pair of writes
365 * to CR4 sandwiched inside an IRQ flag save/restore.
366 *
367 * Note, this works with CR4.PCIDE=0 or 1.
368 */
369 invpcid_flush_all();
370 return;
371 }
372
373 /*
374 * Read-modify-write to CR4 - protect it from preemption and
375 * from interrupts. (Use the raw variant because this code can
376 * be called from deep inside debugging code.)
377 */
378 raw_local_irq_save(flags);
379
380 cr4 = this_cpu_read(cpu_tlbstate.cr4);
381 /* toggle PGE */
382 native_write_cr4(cr4 ^ X86_CR4_PGE);
383 /* write old PGE again and flush TLBs */
384 native_write_cr4(cr4);
385
386 raw_local_irq_restore(flags);
387}
388
389/*
390 * flush one page in the user mapping
391 */
392static inline void __native_flush_tlb_one_user(unsigned long addr)
393{
394 u32 loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);
395
396 asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
397
398 if (!static_cpu_has(X86_FEATURE_PTI))
399 return;
400
401 /*
402 * Some platforms #GP if we call invpcid(type=1/2) before CR4.PCIDE=1.
403 * Just use invalidate_user_asid() in case we are called early.
404 */
405 if (!this_cpu_has(X86_FEATURE_INVPCID_SINGLE))
406 invalidate_user_asid(loaded_mm_asid);
407 else
408 invpcid_flush_one(user_pcid(loaded_mm_asid), addr);
409}
410
411/*
412 * flush everything
413 */
414static inline void __flush_tlb_all(void)
415{
416 if (boot_cpu_has(X86_FEATURE_PGE)) {
417 __flush_tlb_global();
418 } else {
419 /*
420 * !PGE -> !PCID (setup_pcid()), thus every flush is total.
421 */
422 __flush_tlb();
423 }
424}
425
426/*
427 * flush one page in the kernel mapping
428 */
429static inline void __flush_tlb_one_kernel(unsigned long addr)
430{
431 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
432
433 /*
434 * If PTI is off, then __flush_tlb_one_user() is just INVLPG or its
435 * paravirt equivalent. Even with PCID, this is sufficient: we only
436 * use PCID if we also use global PTEs for the kernel mapping, and
437 * INVLPG flushes global translations across all address spaces.
438 *
439 * If PTI is on, then the kernel is mapped with non-global PTEs, and
440 * __flush_tlb_one_user() will flush the given address for the current
441 * kernel address space and for its usermode counterpart, but it does
442 * not flush it for other address spaces.
443 */
444 __flush_tlb_one_user(addr);
445
446 if (!static_cpu_has(X86_FEATURE_PTI))
447 return;
448
449 /*
450 * See above. We need to propagate the flush to all other address
451 * spaces. In principle, we only need to propagate it to kernelmode
452 * address spaces, but the extra bookkeeping we would need is not
453 * worth it.
454 */
455 invalidate_other_asid();
456}
457
458#define TLB_FLUSH_ALL -1UL
459
460/*
461 * TLB flushing:
462 *
463 * - flush_tlb_all() flushes all processes TLBs
464 * - flush_tlb_mm(mm) flushes the specified mm context TLB's
465 * - flush_tlb_page(vma, vmaddr) flushes one page
466 * - flush_tlb_range(vma, start, end) flushes a range of pages
467 * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
468 * - flush_tlb_others(cpumask, info) flushes TLBs on other cpus
469 *
470 * ..but the i386 has somewhat limited tlb flushing capabilities,
471 * and page-granular flushes are available only on i486 and up.
472 */
473struct flush_tlb_info {
474 /*
475 * We support several kinds of flushes.
476 *
477 * - Fully flush a single mm. .mm will be set, .end will be
478 * TLB_FLUSH_ALL, and .new_tlb_gen will be the tlb_gen to
479 * which the IPI sender is trying to catch us up.
480 *
481 * - Partially flush a single mm. .mm will be set, .start and
482 * .end will indicate the range, and .new_tlb_gen will be set
483 * such that the changes between generation .new_tlb_gen-1 and
484 * .new_tlb_gen are entirely contained in the indicated range.
485 *
486 * - Fully flush all mms whose tlb_gens have been updated. .mm
487 * will be NULL, .end will be TLB_FLUSH_ALL, and .new_tlb_gen
488 * will be zero.
489 */
490 struct mm_struct *mm;
491 unsigned long start;
492 unsigned long end;
493 u64 new_tlb_gen;
494};
495
496#define local_flush_tlb() __flush_tlb()
497
498#define flush_tlb_mm(mm) flush_tlb_mm_range(mm, 0UL, TLB_FLUSH_ALL, 0UL)
499
500#define flush_tlb_range(vma, start, end) \
501 flush_tlb_mm_range(vma->vm_mm, start, end, vma->vm_flags)
502
503extern void flush_tlb_all(void);
504extern void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
505 unsigned long end, unsigned long vmflag);
506extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
507
508static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long a)
509{
510 flush_tlb_mm_range(vma->vm_mm, a, a + PAGE_SIZE, VM_NONE);
511}
512
513void native_flush_tlb_others(const struct cpumask *cpumask,
514 const struct flush_tlb_info *info);
515
516static inline u64 inc_mm_tlb_gen(struct mm_struct *mm)
517{
518 /*
519 * Bump the generation count. This also serves as a full barrier
520 * that synchronizes with switch_mm(): callers are required to order
521 * their read of mm_cpumask after their writes to the paging
522 * structures.
523 */
524 return atomic64_inc_return(&mm->context.tlb_gen);
525}
526
527static inline void arch_tlbbatch_add_mm(struct arch_tlbflush_unmap_batch *batch,
528 struct mm_struct *mm)
529{
530 inc_mm_tlb_gen(mm);
531 cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm));
532}
533
534extern void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch);
535
536#ifndef CONFIG_PARAVIRT
537#define flush_tlb_others(mask, info) \
538 native_flush_tlb_others(mask, info)
539#endif
540
541extern void tlb_flush_remove_tables(struct mm_struct *mm);
542extern void tlb_flush_remove_tables_local(void *arg);
543
544#define HAVE_TLB_FLUSH_REMOVE_TABLES
545
546#endif /* _ASM_X86_TLBFLUSH_H */
547