1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * x86 TSC related functions
4 */
5#ifndef _ASM_X86_TSC_H
6#define _ASM_X86_TSC_H
7
8#include <asm/processor.h>
9#include <asm/cpufeature.h>
10
11/*
12 * Standard way to access the cycle counter.
13 */
14typedef unsigned long long cycles_t;
15
16extern unsigned int cpu_khz;
17extern unsigned int tsc_khz;
18
19extern void disable_TSC(void);
20
21static inline cycles_t get_cycles(void)
22{
23 if (!IS_ENABLED(CONFIG_X86_TSC) &&
24 !cpu_feature_enabled(X86_FEATURE_TSC))
25 return 0;
26 return rdtsc();
27}
28#define get_cycles get_cycles
29
30extern struct system_counterval_t convert_art_to_tsc(u64 art);
31extern struct system_counterval_t convert_art_ns_to_tsc(u64 art_ns);
32
33extern void tsc_early_init(void);
34extern void tsc_init(void);
35extern void mark_tsc_unstable(char *reason);
36extern int unsynchronized_tsc(void);
37extern int check_tsc_unstable(void);
38extern void mark_tsc_async_resets(char *reason);
39extern unsigned long native_calibrate_cpu_early(void);
40extern unsigned long native_calibrate_tsc(void);
41extern unsigned long long native_sched_clock_from_tsc(u64 tsc);
42
43extern int tsc_clocksource_reliable;
44#ifdef CONFIG_X86_TSC
45extern bool tsc_async_resets;
46#else
47# define tsc_async_resets false
48#endif
49
50/*
51 * Boot-time check whether the TSCs are synchronized across
52 * all CPUs/cores:
53 */
54#ifdef CONFIG_X86_TSC
55extern bool tsc_store_and_check_tsc_adjust(bool bootcpu);
56extern void tsc_verify_tsc_adjust(bool resume);
57extern void check_tsc_sync_target(void);
58#else
59static inline bool tsc_store_and_check_tsc_adjust(bool bootcpu) { return false; }
60static inline void tsc_verify_tsc_adjust(bool resume) { }
61static inline void check_tsc_sync_target(void) { }
62#endif
63
64extern int notsc_setup(char *);
65extern void tsc_save_sched_clock_state(void);
66extern void tsc_restore_sched_clock_state(void);
67
68unsigned long cpu_khz_from_msr(void);
69
70#endif /* _ASM_X86_TSC_H */
71

source code of linux/arch/x86/include/asm/tsc.h