1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
2 | #ifndef _ASM_X86_KVM_H |
3 | #define _ASM_X86_KVM_H |
4 | |
5 | /* |
6 | * KVM x86 specific structures and definitions |
7 | * |
8 | */ |
9 | |
10 | #include <linux/types.h> |
11 | #include <linux/ioctl.h> |
12 | |
13 | #define KVM_PIO_PAGE_OFFSET 1 |
14 | #define KVM_COALESCED_MMIO_PAGE_OFFSET 2 |
15 | |
16 | #define DE_VECTOR 0 |
17 | #define DB_VECTOR 1 |
18 | #define BP_VECTOR 3 |
19 | #define OF_VECTOR 4 |
20 | #define BR_VECTOR 5 |
21 | #define UD_VECTOR 6 |
22 | #define NM_VECTOR 7 |
23 | #define DF_VECTOR 8 |
24 | #define TS_VECTOR 10 |
25 | #define NP_VECTOR 11 |
26 | #define SS_VECTOR 12 |
27 | #define GP_VECTOR 13 |
28 | #define PF_VECTOR 14 |
29 | #define MF_VECTOR 16 |
30 | #define AC_VECTOR 17 |
31 | #define MC_VECTOR 18 |
32 | #define XM_VECTOR 19 |
33 | #define VE_VECTOR 20 |
34 | |
35 | /* Select x86 specific features in <linux/kvm.h> */ |
36 | #define __KVM_HAVE_PIT |
37 | #define __KVM_HAVE_IOAPIC |
38 | #define __KVM_HAVE_IRQ_LINE |
39 | #define __KVM_HAVE_MSI |
40 | #define __KVM_HAVE_USER_NMI |
41 | #define __KVM_HAVE_GUEST_DEBUG |
42 | #define __KVM_HAVE_MSIX |
43 | #define __KVM_HAVE_MCE |
44 | #define __KVM_HAVE_PIT_STATE2 |
45 | #define __KVM_HAVE_XEN_HVM |
46 | #define __KVM_HAVE_VCPU_EVENTS |
47 | #define __KVM_HAVE_DEBUGREGS |
48 | #define __KVM_HAVE_XSAVE |
49 | #define __KVM_HAVE_XCRS |
50 | #define __KVM_HAVE_READONLY_MEM |
51 | |
52 | /* Architectural interrupt line count. */ |
53 | #define KVM_NR_INTERRUPTS 256 |
54 | |
55 | struct kvm_memory_alias { |
56 | __u32 slot; /* this has a different namespace than memory slots */ |
57 | __u32 flags; |
58 | __u64 guest_phys_addr; |
59 | __u64 memory_size; |
60 | __u64 target_phys_addr; |
61 | }; |
62 | |
63 | /* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */ |
64 | struct kvm_pic_state { |
65 | __u8 last_irr; /* edge detection */ |
66 | __u8 irr; /* interrupt request register */ |
67 | __u8 imr; /* interrupt mask register */ |
68 | __u8 isr; /* interrupt service register */ |
69 | __u8 priority_add; /* highest irq priority */ |
70 | __u8 irq_base; |
71 | __u8 read_reg_select; |
72 | __u8 poll; |
73 | __u8 special_mask; |
74 | __u8 init_state; |
75 | __u8 auto_eoi; |
76 | __u8 rotate_on_auto_eoi; |
77 | __u8 special_fully_nested_mode; |
78 | __u8 init4; /* true if 4 byte init */ |
79 | __u8 elcr; /* PIIX edge/trigger selection */ |
80 | __u8 elcr_mask; |
81 | }; |
82 | |
83 | #define KVM_IOAPIC_NUM_PINS 24 |
84 | struct kvm_ioapic_state { |
85 | __u64 base_address; |
86 | __u32 ioregsel; |
87 | __u32 id; |
88 | __u32 irr; |
89 | __u32 pad; |
90 | union { |
91 | __u64 bits; |
92 | struct { |
93 | __u8 vector; |
94 | __u8 delivery_mode:3; |
95 | __u8 dest_mode:1; |
96 | __u8 delivery_status:1; |
97 | __u8 polarity:1; |
98 | __u8 remote_irr:1; |
99 | __u8 trig_mode:1; |
100 | __u8 mask:1; |
101 | __u8 reserve:7; |
102 | __u8 reserved[4]; |
103 | __u8 dest_id; |
104 | } fields; |
105 | } redirtbl[KVM_IOAPIC_NUM_PINS]; |
106 | }; |
107 | |
108 | #define KVM_IRQCHIP_PIC_MASTER 0 |
109 | #define KVM_IRQCHIP_PIC_SLAVE 1 |
110 | #define KVM_IRQCHIP_IOAPIC 2 |
111 | #define KVM_NR_IRQCHIPS 3 |
112 | |
113 | #define KVM_RUN_X86_SMM (1 << 0) |
114 | |
115 | /* for KVM_GET_REGS and KVM_SET_REGS */ |
116 | struct kvm_regs { |
117 | /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */ |
118 | __u64 rax, rbx, rcx, rdx; |
119 | __u64 rsi, rdi, rsp, rbp; |
120 | __u64 r8, r9, r10, r11; |
121 | __u64 r12, r13, r14, r15; |
122 | __u64 rip, rflags; |
123 | }; |
124 | |
125 | /* for KVM_GET_LAPIC and KVM_SET_LAPIC */ |
126 | #define KVM_APIC_REG_SIZE 0x400 |
127 | struct kvm_lapic_state { |
128 | char regs[KVM_APIC_REG_SIZE]; |
129 | }; |
130 | |
131 | struct kvm_segment { |
132 | __u64 base; |
133 | __u32 limit; |
134 | __u16 selector; |
135 | __u8 type; |
136 | __u8 present, dpl, db, s, l, g, avl; |
137 | __u8 unusable; |
138 | __u8 padding; |
139 | }; |
140 | |
141 | struct kvm_dtable { |
142 | __u64 base; |
143 | __u16 limit; |
144 | __u16 padding[3]; |
145 | }; |
146 | |
147 | |
148 | /* for KVM_GET_SREGS and KVM_SET_SREGS */ |
149 | struct kvm_sregs { |
150 | /* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */ |
151 | struct kvm_segment cs, ds, es, fs, gs, ss; |
152 | struct kvm_segment tr, ldt; |
153 | struct kvm_dtable gdt, idt; |
154 | __u64 cr0, cr2, cr3, cr4, cr8; |
155 | __u64 efer; |
156 | __u64 apic_base; |
157 | __u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64]; |
158 | }; |
159 | |
160 | /* for KVM_GET_FPU and KVM_SET_FPU */ |
161 | struct kvm_fpu { |
162 | __u8 fpr[8][16]; |
163 | __u16 fcw; |
164 | __u16 fsw; |
165 | __u8 ftwx; /* in fxsave format */ |
166 | __u8 pad1; |
167 | __u16 last_opcode; |
168 | __u64 last_ip; |
169 | __u64 last_dp; |
170 | __u8 xmm[16][16]; |
171 | __u32 mxcsr; |
172 | __u32 pad2; |
173 | }; |
174 | |
175 | struct kvm_msr_entry { |
176 | __u32 index; |
177 | __u32 reserved; |
178 | __u64 data; |
179 | }; |
180 | |
181 | /* for KVM_GET_MSRS and KVM_SET_MSRS */ |
182 | struct kvm_msrs { |
183 | __u32 nmsrs; /* number of msrs in entries */ |
184 | __u32 pad; |
185 | |
186 | struct kvm_msr_entry entries[0]; |
187 | }; |
188 | |
189 | /* for KVM_GET_MSR_INDEX_LIST */ |
190 | struct kvm_msr_list { |
191 | __u32 nmsrs; /* number of msrs in entries */ |
192 | __u32 indices[0]; |
193 | }; |
194 | |
195 | |
196 | struct kvm_cpuid_entry { |
197 | __u32 function; |
198 | __u32 eax; |
199 | __u32 ebx; |
200 | __u32 ecx; |
201 | __u32 edx; |
202 | __u32 padding; |
203 | }; |
204 | |
205 | /* for KVM_SET_CPUID */ |
206 | struct kvm_cpuid { |
207 | __u32 nent; |
208 | __u32 padding; |
209 | struct kvm_cpuid_entry entries[0]; |
210 | }; |
211 | |
212 | struct kvm_cpuid_entry2 { |
213 | __u32 function; |
214 | __u32 index; |
215 | __u32 flags; |
216 | __u32 eax; |
217 | __u32 ebx; |
218 | __u32 ecx; |
219 | __u32 edx; |
220 | __u32 padding[3]; |
221 | }; |
222 | |
223 | #define KVM_CPUID_FLAG_SIGNIFCANT_INDEX (1 << 0) |
224 | #define KVM_CPUID_FLAG_STATEFUL_FUNC (1 << 1) |
225 | #define KVM_CPUID_FLAG_STATE_READ_NEXT (1 << 2) |
226 | |
227 | /* for KVM_SET_CPUID2 */ |
228 | struct kvm_cpuid2 { |
229 | __u32 nent; |
230 | __u32 padding; |
231 | struct kvm_cpuid_entry2 entries[0]; |
232 | }; |
233 | |
234 | /* for KVM_GET_PIT and KVM_SET_PIT */ |
235 | struct kvm_pit_channel_state { |
236 | __u32 count; /* can be 65536 */ |
237 | __u16 latched_count; |
238 | __u8 count_latched; |
239 | __u8 status_latched; |
240 | __u8 status; |
241 | __u8 read_state; |
242 | __u8 write_state; |
243 | __u8 write_latch; |
244 | __u8 rw_mode; |
245 | __u8 mode; |
246 | __u8 bcd; |
247 | __u8 gate; |
248 | __s64 count_load_time; |
249 | }; |
250 | |
251 | struct kvm_debug_exit_arch { |
252 | __u32 exception; |
253 | __u32 pad; |
254 | __u64 pc; |
255 | __u64 dr6; |
256 | __u64 dr7; |
257 | }; |
258 | |
259 | #define KVM_GUESTDBG_USE_SW_BP 0x00010000 |
260 | #define KVM_GUESTDBG_USE_HW_BP 0x00020000 |
261 | #define KVM_GUESTDBG_INJECT_DB 0x00040000 |
262 | #define KVM_GUESTDBG_INJECT_BP 0x00080000 |
263 | |
264 | /* for KVM_SET_GUEST_DEBUG */ |
265 | struct kvm_guest_debug_arch { |
266 | __u64 debugreg[8]; |
267 | }; |
268 | |
269 | struct kvm_pit_state { |
270 | struct kvm_pit_channel_state channels[3]; |
271 | }; |
272 | |
273 | #define KVM_PIT_FLAGS_HPET_LEGACY 0x00000001 |
274 | |
275 | struct kvm_pit_state2 { |
276 | struct kvm_pit_channel_state channels[3]; |
277 | __u32 flags; |
278 | __u32 reserved[9]; |
279 | }; |
280 | |
281 | struct kvm_reinject_control { |
282 | __u8 pit_reinject; |
283 | __u8 reserved[31]; |
284 | }; |
285 | |
286 | /* When set in flags, include corresponding fields on KVM_SET_VCPU_EVENTS */ |
287 | #define KVM_VCPUEVENT_VALID_NMI_PENDING 0x00000001 |
288 | #define KVM_VCPUEVENT_VALID_SIPI_VECTOR 0x00000002 |
289 | #define KVM_VCPUEVENT_VALID_SHADOW 0x00000004 |
290 | #define KVM_VCPUEVENT_VALID_SMM 0x00000008 |
291 | #define KVM_VCPUEVENT_VALID_PAYLOAD 0x00000010 |
292 | |
293 | /* Interrupt shadow states */ |
294 | #define KVM_X86_SHADOW_INT_MOV_SS 0x01 |
295 | #define KVM_X86_SHADOW_INT_STI 0x02 |
296 | |
297 | /* for KVM_GET/SET_VCPU_EVENTS */ |
298 | struct kvm_vcpu_events { |
299 | struct { |
300 | __u8 injected; |
301 | __u8 nr; |
302 | __u8 has_error_code; |
303 | __u8 pending; |
304 | __u32 error_code; |
305 | } exception; |
306 | struct { |
307 | __u8 injected; |
308 | __u8 nr; |
309 | __u8 soft; |
310 | __u8 shadow; |
311 | } interrupt; |
312 | struct { |
313 | __u8 injected; |
314 | __u8 pending; |
315 | __u8 masked; |
316 | __u8 pad; |
317 | } nmi; |
318 | __u32 sipi_vector; |
319 | __u32 flags; |
320 | struct { |
321 | __u8 smm; |
322 | __u8 pending; |
323 | __u8 smm_inside_nmi; |
324 | __u8 latched_init; |
325 | } smi; |
326 | __u8 reserved[27]; |
327 | __u8 exception_has_payload; |
328 | __u64 exception_payload; |
329 | }; |
330 | |
331 | /* for KVM_GET/SET_DEBUGREGS */ |
332 | struct kvm_debugregs { |
333 | __u64 db[4]; |
334 | __u64 dr6; |
335 | __u64 dr7; |
336 | __u64 flags; |
337 | __u64 reserved[9]; |
338 | }; |
339 | |
340 | /* for KVM_CAP_XSAVE */ |
341 | struct kvm_xsave { |
342 | __u32 region[1024]; |
343 | }; |
344 | |
345 | #define KVM_MAX_XCRS 16 |
346 | |
347 | struct kvm_xcr { |
348 | __u32 xcr; |
349 | __u32 reserved; |
350 | __u64 value; |
351 | }; |
352 | |
353 | struct kvm_xcrs { |
354 | __u32 nr_xcrs; |
355 | __u32 flags; |
356 | struct kvm_xcr xcrs[KVM_MAX_XCRS]; |
357 | __u64 padding[16]; |
358 | }; |
359 | |
360 | #define KVM_SYNC_X86_REGS (1UL << 0) |
361 | #define KVM_SYNC_X86_SREGS (1UL << 1) |
362 | #define KVM_SYNC_X86_EVENTS (1UL << 2) |
363 | |
364 | #define KVM_SYNC_X86_VALID_FIELDS \ |
365 | (KVM_SYNC_X86_REGS| \ |
366 | KVM_SYNC_X86_SREGS| \ |
367 | KVM_SYNC_X86_EVENTS) |
368 | |
369 | /* kvm_sync_regs struct included by kvm_run struct */ |
370 | struct kvm_sync_regs { |
371 | /* Members of this structure are potentially malicious. |
372 | * Care must be taken by code reading, esp. interpreting, |
373 | * data fields from them inside KVM to prevent TOCTOU and |
374 | * double-fetch types of vulnerabilities. |
375 | */ |
376 | struct kvm_regs regs; |
377 | struct kvm_sregs sregs; |
378 | struct kvm_vcpu_events events; |
379 | }; |
380 | |
381 | #define KVM_X86_QUIRK_LINT0_REENABLED (1 << 0) |
382 | #define KVM_X86_QUIRK_CD_NW_CLEARED (1 << 1) |
383 | #define KVM_X86_QUIRK_LAPIC_MMIO_HOLE (1 << 2) |
384 | |
385 | #define KVM_STATE_NESTED_GUEST_MODE 0x00000001 |
386 | #define KVM_STATE_NESTED_RUN_PENDING 0x00000002 |
387 | #define KVM_STATE_NESTED_EVMCS 0x00000004 |
388 | |
389 | #define KVM_STATE_NESTED_SMM_GUEST_MODE 0x00000001 |
390 | #define KVM_STATE_NESTED_SMM_VMXON 0x00000002 |
391 | |
392 | struct kvm_vmx_nested_state { |
393 | __u64 vmxon_pa; |
394 | __u64 vmcs_pa; |
395 | |
396 | struct { |
397 | __u16 flags; |
398 | } smm; |
399 | }; |
400 | |
401 | /* for KVM_CAP_NESTED_STATE */ |
402 | struct kvm_nested_state { |
403 | /* KVM_STATE_* flags */ |
404 | __u16 flags; |
405 | |
406 | /* 0 for VMX, 1 for SVM. */ |
407 | __u16 format; |
408 | |
409 | /* 128 for SVM, 128 + VMCS size for VMX. */ |
410 | __u32 size; |
411 | |
412 | union { |
413 | /* VMXON, VMCS */ |
414 | struct kvm_vmx_nested_state vmx; |
415 | |
416 | /* Pad the header to 128 bytes. */ |
417 | __u8 pad[120]; |
418 | }; |
419 | |
420 | __u8 data[0]; |
421 | }; |
422 | |
423 | #endif /* _ASM_X86_KVM_H */ |
424 | |