1/* cpu_feature_enabled() cannot be used this early */
2#define USE_EARLY_PGTABLE_L5
3
4#include <linux/memblock.h>
5#include <linux/linkage.h>
6#include <linux/bitops.h>
7#include <linux/kernel.h>
8#include <linux/export.h>
9#include <linux/percpu.h>
10#include <linux/string.h>
11#include <linux/ctype.h>
12#include <linux/delay.h>
13#include <linux/sched/mm.h>
14#include <linux/sched/clock.h>
15#include <linux/sched/task.h>
16#include <linux/init.h>
17#include <linux/kprobes.h>
18#include <linux/kgdb.h>
19#include <linux/smp.h>
20#include <linux/io.h>
21#include <linux/syscore_ops.h>
22
23#include <asm/stackprotector.h>
24#include <asm/perf_event.h>
25#include <asm/mmu_context.h>
26#include <asm/archrandom.h>
27#include <asm/hypervisor.h>
28#include <asm/processor.h>
29#include <asm/tlbflush.h>
30#include <asm/debugreg.h>
31#include <asm/sections.h>
32#include <asm/vsyscall.h>
33#include <linux/topology.h>
34#include <linux/cpumask.h>
35#include <asm/pgtable.h>
36#include <linux/atomic.h>
37#include <asm/proto.h>
38#include <asm/setup.h>
39#include <asm/apic.h>
40#include <asm/desc.h>
41#include <asm/fpu/internal.h>
42#include <asm/mtrr.h>
43#include <asm/hwcap2.h>
44#include <linux/numa.h>
45#include <asm/asm.h>
46#include <asm/bugs.h>
47#include <asm/cpu.h>
48#include <asm/mce.h>
49#include <asm/msr.h>
50#include <asm/pat.h>
51#include <asm/microcode.h>
52#include <asm/microcode_intel.h>
53#include <asm/intel-family.h>
54#include <asm/cpu_device_id.h>
55
56#ifdef CONFIG_X86_LOCAL_APIC
57#include <asm/uv/uv.h>
58#endif
59
60#include "cpu.h"
61
62u32 elf_hwcap2 __read_mostly;
63
64/* all of these masks are initialized in setup_cpu_local_masks() */
65cpumask_var_t cpu_initialized_mask;
66cpumask_var_t cpu_callout_mask;
67cpumask_var_t cpu_callin_mask;
68
69/* representing cpus for which sibling maps can be computed */
70cpumask_var_t cpu_sibling_setup_mask;
71
72/* Number of siblings per CPU package */
73int smp_num_siblings = 1;
74EXPORT_SYMBOL(smp_num_siblings);
75
76/* Last level cache ID of each logical CPU */
77DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
78
79/* correctly size the local cpu masks */
80void __init setup_cpu_local_masks(void)
81{
82 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
83 alloc_bootmem_cpumask_var(&cpu_callin_mask);
84 alloc_bootmem_cpumask_var(&cpu_callout_mask);
85 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
86}
87
88static void default_init(struct cpuinfo_x86 *c)
89{
90#ifdef CONFIG_X86_64
91 cpu_detect_cache_sizes(c);
92#else
93 /* Not much we can do here... */
94 /* Check if at least it has cpuid */
95 if (c->cpuid_level == -1) {
96 /* No cpuid. It must be an ancient CPU */
97 if (c->x86 == 4)
98 strcpy(c->x86_model_id, "486");
99 else if (c->x86 == 3)
100 strcpy(c->x86_model_id, "386");
101 }
102#endif
103}
104
105static const struct cpu_dev default_cpu = {
106 .c_init = default_init,
107 .c_vendor = "Unknown",
108 .c_x86_vendor = X86_VENDOR_UNKNOWN,
109};
110
111static const struct cpu_dev *this_cpu = &default_cpu;
112
113DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
114#ifdef CONFIG_X86_64
115 /*
116 * We need valid kernel segments for data and code in long mode too
117 * IRET will check the segment types kkeil 2000/10/28
118 * Also sysret mandates a special GDT layout
119 *
120 * TLS descriptors are currently at a different place compared to i386.
121 * Hopefully nobody expects them at a fixed place (Wine?)
122 */
123 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
124 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
125 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
126 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
127 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
128 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
129#else
130 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
131 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
132 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
133 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
134 /*
135 * Segments used for calling PnP BIOS have byte granularity.
136 * They code segments and data segments have fixed 64k limits,
137 * the transfer segment sizes are set at run time.
138 */
139 /* 32-bit code */
140 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
141 /* 16-bit code */
142 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
143 /* 16-bit data */
144 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
145 /* 16-bit data */
146 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
147 /* 16-bit data */
148 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
149 /*
150 * The APM segments have byte granularity and their bases
151 * are set at run time. All have 64k limits.
152 */
153 /* 32-bit code */
154 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
155 /* 16-bit code */
156 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
157 /* data */
158 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
159
160 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
161 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
162 GDT_STACK_CANARY_INIT
163#endif
164} };
165EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
166
167static int __init x86_mpx_setup(char *s)
168{
169 /* require an exact match without trailing characters */
170 if (strlen(s))
171 return 0;
172
173 /* do not emit a message if the feature is not present */
174 if (!boot_cpu_has(X86_FEATURE_MPX))
175 return 1;
176
177 setup_clear_cpu_cap(X86_FEATURE_MPX);
178 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
179 return 1;
180}
181__setup("nompx", x86_mpx_setup);
182
183#ifdef CONFIG_X86_64
184static int __init x86_nopcid_setup(char *s)
185{
186 /* nopcid doesn't accept parameters */
187 if (s)
188 return -EINVAL;
189
190 /* do not emit a message if the feature is not present */
191 if (!boot_cpu_has(X86_FEATURE_PCID))
192 return 0;
193
194 setup_clear_cpu_cap(X86_FEATURE_PCID);
195 pr_info("nopcid: PCID feature disabled\n");
196 return 0;
197}
198early_param("nopcid", x86_nopcid_setup);
199#endif
200
201static int __init x86_noinvpcid_setup(char *s)
202{
203 /* noinvpcid doesn't accept parameters */
204 if (s)
205 return -EINVAL;
206
207 /* do not emit a message if the feature is not present */
208 if (!boot_cpu_has(X86_FEATURE_INVPCID))
209 return 0;
210
211 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
212 pr_info("noinvpcid: INVPCID feature disabled\n");
213 return 0;
214}
215early_param("noinvpcid", x86_noinvpcid_setup);
216
217#ifdef CONFIG_X86_32
218static int cachesize_override = -1;
219static int disable_x86_serial_nr = 1;
220
221static int __init cachesize_setup(char *str)
222{
223 get_option(&str, &cachesize_override);
224 return 1;
225}
226__setup("cachesize=", cachesize_setup);
227
228static int __init x86_sep_setup(char *s)
229{
230 setup_clear_cpu_cap(X86_FEATURE_SEP);
231 return 1;
232}
233__setup("nosep", x86_sep_setup);
234
235/* Standard macro to see if a specific flag is changeable */
236static inline int flag_is_changeable_p(u32 flag)
237{
238 u32 f1, f2;
239
240 /*
241 * Cyrix and IDT cpus allow disabling of CPUID
242 * so the code below may return different results
243 * when it is executed before and after enabling
244 * the CPUID. Add "volatile" to not allow gcc to
245 * optimize the subsequent calls to this function.
246 */
247 asm volatile ("pushfl \n\t"
248 "pushfl \n\t"
249 "popl %0 \n\t"
250 "movl %0, %1 \n\t"
251 "xorl %2, %0 \n\t"
252 "pushl %0 \n\t"
253 "popfl \n\t"
254 "pushfl \n\t"
255 "popl %0 \n\t"
256 "popfl \n\t"
257
258 : "=&r" (f1), "=&r" (f2)
259 : "ir" (flag));
260
261 return ((f1^f2) & flag) != 0;
262}
263
264/* Probe for the CPUID instruction */
265int have_cpuid_p(void)
266{
267 return flag_is_changeable_p(X86_EFLAGS_ID);
268}
269
270static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
271{
272 unsigned long lo, hi;
273
274 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
275 return;
276
277 /* Disable processor serial number: */
278
279 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
280 lo |= 0x200000;
281 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
282
283 pr_notice("CPU serial number disabled.\n");
284 clear_cpu_cap(c, X86_FEATURE_PN);
285
286 /* Disabling the serial number may affect the cpuid level */
287 c->cpuid_level = cpuid_eax(0);
288}
289
290static int __init x86_serial_nr_setup(char *s)
291{
292 disable_x86_serial_nr = 0;
293 return 1;
294}
295__setup("serialnumber", x86_serial_nr_setup);
296#else
297static inline int flag_is_changeable_p(u32 flag)
298{
299 return 1;
300}
301static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
302{
303}
304#endif
305
306static __init int setup_disable_smep(char *arg)
307{
308 setup_clear_cpu_cap(X86_FEATURE_SMEP);
309 /* Check for things that depend on SMEP being enabled: */
310 check_mpx_erratum(&boot_cpu_data);
311 return 1;
312}
313__setup("nosmep", setup_disable_smep);
314
315static __always_inline void setup_smep(struct cpuinfo_x86 *c)
316{
317 if (cpu_has(c, X86_FEATURE_SMEP))
318 cr4_set_bits(X86_CR4_SMEP);
319}
320
321static __init int setup_disable_smap(char *arg)
322{
323 setup_clear_cpu_cap(X86_FEATURE_SMAP);
324 return 1;
325}
326__setup("nosmap", setup_disable_smap);
327
328static __always_inline void setup_smap(struct cpuinfo_x86 *c)
329{
330 unsigned long eflags = native_save_fl();
331
332 /* This should have been cleared long ago */
333 BUG_ON(eflags & X86_EFLAGS_AC);
334
335 if (cpu_has(c, X86_FEATURE_SMAP)) {
336#ifdef CONFIG_X86_SMAP
337 cr4_set_bits(X86_CR4_SMAP);
338#else
339 cr4_clear_bits(X86_CR4_SMAP);
340#endif
341 }
342}
343
344static __always_inline void setup_umip(struct cpuinfo_x86 *c)
345{
346 /* Check the boot processor, plus build option for UMIP. */
347 if (!cpu_feature_enabled(X86_FEATURE_UMIP))
348 goto out;
349
350 /* Check the current processor's cpuid bits. */
351 if (!cpu_has(c, X86_FEATURE_UMIP))
352 goto out;
353
354 cr4_set_bits(X86_CR4_UMIP);
355
356 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n");
357
358 return;
359
360out:
361 /*
362 * Make sure UMIP is disabled in case it was enabled in a
363 * previous boot (e.g., via kexec).
364 */
365 cr4_clear_bits(X86_CR4_UMIP);
366}
367
368/*
369 * Protection Keys are not available in 32-bit mode.
370 */
371static bool pku_disabled;
372
373static __always_inline void setup_pku(struct cpuinfo_x86 *c)
374{
375 /* check the boot processor, plus compile options for PKU: */
376 if (!cpu_feature_enabled(X86_FEATURE_PKU))
377 return;
378 /* checks the actual processor's cpuid bits: */
379 if (!cpu_has(c, X86_FEATURE_PKU))
380 return;
381 if (pku_disabled)
382 return;
383
384 cr4_set_bits(X86_CR4_PKE);
385 /*
386 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
387 * cpuid bit to be set. We need to ensure that we
388 * update that bit in this CPU's "cpu_info".
389 */
390 get_cpu_cap(c);
391}
392
393#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
394static __init int setup_disable_pku(char *arg)
395{
396 /*
397 * Do not clear the X86_FEATURE_PKU bit. All of the
398 * runtime checks are against OSPKE so clearing the
399 * bit does nothing.
400 *
401 * This way, we will see "pku" in cpuinfo, but not
402 * "ospke", which is exactly what we want. It shows
403 * that the CPU has PKU, but the OS has not enabled it.
404 * This happens to be exactly how a system would look
405 * if we disabled the config option.
406 */
407 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
408 pku_disabled = true;
409 return 1;
410}
411__setup("nopku", setup_disable_pku);
412#endif /* CONFIG_X86_64 */
413
414/*
415 * Some CPU features depend on higher CPUID levels, which may not always
416 * be available due to CPUID level capping or broken virtualization
417 * software. Add those features to this table to auto-disable them.
418 */
419struct cpuid_dependent_feature {
420 u32 feature;
421 u32 level;
422};
423
424static const struct cpuid_dependent_feature
425cpuid_dependent_features[] = {
426 { X86_FEATURE_MWAIT, 0x00000005 },
427 { X86_FEATURE_DCA, 0x00000009 },
428 { X86_FEATURE_XSAVE, 0x0000000d },
429 { 0, 0 }
430};
431
432static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
433{
434 const struct cpuid_dependent_feature *df;
435
436 for (df = cpuid_dependent_features; df->feature; df++) {
437
438 if (!cpu_has(c, df->feature))
439 continue;
440 /*
441 * Note: cpuid_level is set to -1 if unavailable, but
442 * extended_extended_level is set to 0 if unavailable
443 * and the legitimate extended levels are all negative
444 * when signed; hence the weird messing around with
445 * signs here...
446 */
447 if (!((s32)df->level < 0 ?
448 (u32)df->level > (u32)c->extended_cpuid_level :
449 (s32)df->level > (s32)c->cpuid_level))
450 continue;
451
452 clear_cpu_cap(c, df->feature);
453 if (!warn)
454 continue;
455
456 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
457 x86_cap_flag(df->feature), df->level);
458 }
459}
460
461/*
462 * Naming convention should be: <Name> [(<Codename>)]
463 * This table only is used unless init_<vendor>() below doesn't set it;
464 * in particular, if CPUID levels 0x80000002..4 are supported, this
465 * isn't used
466 */
467
468/* Look up CPU names by table lookup. */
469static const char *table_lookup_model(struct cpuinfo_x86 *c)
470{
471#ifdef CONFIG_X86_32
472 const struct legacy_cpu_model_info *info;
473
474 if (c->x86_model >= 16)
475 return NULL; /* Range check */
476
477 if (!this_cpu)
478 return NULL;
479
480 info = this_cpu->legacy_models;
481
482 while (info->family) {
483 if (info->family == c->x86)
484 return info->model_names[c->x86_model];
485 info++;
486 }
487#endif
488 return NULL; /* Not found */
489}
490
491__u32 cpu_caps_cleared[NCAPINTS + NBUGINTS];
492__u32 cpu_caps_set[NCAPINTS + NBUGINTS];
493
494void load_percpu_segment(int cpu)
495{
496#ifdef CONFIG_X86_32
497 loadsegment(fs, __KERNEL_PERCPU);
498#else
499 __loadsegment_simple(gs, 0);
500 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu));
501#endif
502 load_stack_canary_segment();
503}
504
505#ifdef CONFIG_X86_32
506/* The 32-bit entry code needs to find cpu_entry_area. */
507DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area);
508#endif
509
510#ifdef CONFIG_X86_64
511/*
512 * Special IST stacks which the CPU switches to when it calls
513 * an IST-marked descriptor entry. Up to 7 stacks (hardware
514 * limit), all of them are 4K, except the debug stack which
515 * is 8K.
516 */
517static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
518 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
519 [DEBUG_STACK - 1] = DEBUG_STKSZ
520};
521#endif
522
523/* Load the original GDT from the per-cpu structure */
524void load_direct_gdt(int cpu)
525{
526 struct desc_ptr gdt_descr;
527
528 gdt_descr.address = (long)get_cpu_gdt_rw(cpu);
529 gdt_descr.size = GDT_SIZE - 1;
530 load_gdt(&gdt_descr);
531}
532EXPORT_SYMBOL_GPL(load_direct_gdt);
533
534/* Load a fixmap remapping of the per-cpu GDT */
535void load_fixmap_gdt(int cpu)
536{
537 struct desc_ptr gdt_descr;
538
539 gdt_descr.address = (long)get_cpu_gdt_ro(cpu);
540 gdt_descr.size = GDT_SIZE - 1;
541 load_gdt(&gdt_descr);
542}
543EXPORT_SYMBOL_GPL(load_fixmap_gdt);
544
545/*
546 * Current gdt points %fs at the "master" per-cpu area: after this,
547 * it's on the real one.
548 */
549void switch_to_new_gdt(int cpu)
550{
551 /* Load the original GDT */
552 load_direct_gdt(cpu);
553 /* Reload the per-cpu base */
554 load_percpu_segment(cpu);
555}
556
557static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
558
559static void get_model_name(struct cpuinfo_x86 *c)
560{
561 unsigned int *v;
562 char *p, *q, *s;
563
564 if (c->extended_cpuid_level < 0x80000004)
565 return;
566
567 v = (unsigned int *)c->x86_model_id;
568 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
569 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
570 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
571 c->x86_model_id[48] = 0;
572
573 /* Trim whitespace */
574 p = q = s = &c->x86_model_id[0];
575
576 while (*p == ' ')
577 p++;
578
579 while (*p) {
580 /* Note the last non-whitespace index */
581 if (!isspace(*p))
582 s = q;
583
584 *q++ = *p++;
585 }
586
587 *(s + 1) = '\0';
588}
589
590void detect_num_cpu_cores(struct cpuinfo_x86 *c)
591{
592 unsigned int eax, ebx, ecx, edx;
593
594 c->x86_max_cores = 1;
595 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4)
596 return;
597
598 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
599 if (eax & 0x1f)
600 c->x86_max_cores = (eax >> 26) + 1;
601}
602
603void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
604{
605 unsigned int n, dummy, ebx, ecx, edx, l2size;
606
607 n = c->extended_cpuid_level;
608
609 if (n >= 0x80000005) {
610 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
611 c->x86_cache_size = (ecx>>24) + (edx>>24);
612#ifdef CONFIG_X86_64
613 /* On K8 L1 TLB is inclusive, so don't count it */
614 c->x86_tlbsize = 0;
615#endif
616 }
617
618 if (n < 0x80000006) /* Some chips just has a large L1. */
619 return;
620
621 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
622 l2size = ecx >> 16;
623
624#ifdef CONFIG_X86_64
625 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
626#else
627 /* do processor-specific cache resizing */
628 if (this_cpu->legacy_cache_size)
629 l2size = this_cpu->legacy_cache_size(c, l2size);
630
631 /* Allow user to override all this if necessary. */
632 if (cachesize_override != -1)
633 l2size = cachesize_override;
634
635 if (l2size == 0)
636 return; /* Again, no L2 cache is possible */
637#endif
638
639 c->x86_cache_size = l2size;
640}
641
642u16 __read_mostly tlb_lli_4k[NR_INFO];
643u16 __read_mostly tlb_lli_2m[NR_INFO];
644u16 __read_mostly tlb_lli_4m[NR_INFO];
645u16 __read_mostly tlb_lld_4k[NR_INFO];
646u16 __read_mostly tlb_lld_2m[NR_INFO];
647u16 __read_mostly tlb_lld_4m[NR_INFO];
648u16 __read_mostly tlb_lld_1g[NR_INFO];
649
650static void cpu_detect_tlb(struct cpuinfo_x86 *c)
651{
652 if (this_cpu->c_detect_tlb)
653 this_cpu->c_detect_tlb(c);
654
655 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
656 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
657 tlb_lli_4m[ENTRIES]);
658
659 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
660 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
661 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
662}
663
664int detect_ht_early(struct cpuinfo_x86 *c)
665{
666#ifdef CONFIG_SMP
667 u32 eax, ebx, ecx, edx;
668
669 if (!cpu_has(c, X86_FEATURE_HT))
670 return -1;
671
672 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
673 return -1;
674
675 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
676 return -1;
677
678 cpuid(1, &eax, &ebx, &ecx, &edx);
679
680 smp_num_siblings = (ebx & 0xff0000) >> 16;
681 if (smp_num_siblings == 1)
682 pr_info_once("CPU0: Hyper-Threading is disabled\n");
683#endif
684 return 0;
685}
686
687void detect_ht(struct cpuinfo_x86 *c)
688{
689#ifdef CONFIG_SMP
690 int index_msb, core_bits;
691
692 if (detect_ht_early(c) < 0)
693 return;
694
695 index_msb = get_count_order(smp_num_siblings);
696 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
697
698 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
699
700 index_msb = get_count_order(smp_num_siblings);
701
702 core_bits = get_count_order(c->x86_max_cores);
703
704 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
705 ((1 << core_bits) - 1);
706#endif
707}
708
709static void get_cpu_vendor(struct cpuinfo_x86 *c)
710{
711 char *v = c->x86_vendor_id;
712 int i;
713
714 for (i = 0; i < X86_VENDOR_NUM; i++) {
715 if (!cpu_devs[i])
716 break;
717
718 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
719 (cpu_devs[i]->c_ident[1] &&
720 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
721
722 this_cpu = cpu_devs[i];
723 c->x86_vendor = this_cpu->c_x86_vendor;
724 return;
725 }
726 }
727
728 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
729 "CPU: Your system may be unstable.\n", v);
730
731 c->x86_vendor = X86_VENDOR_UNKNOWN;
732 this_cpu = &default_cpu;
733}
734
735void cpu_detect(struct cpuinfo_x86 *c)
736{
737 /* Get vendor name */
738 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
739 (unsigned int *)&c->x86_vendor_id[0],
740 (unsigned int *)&c->x86_vendor_id[8],
741 (unsigned int *)&c->x86_vendor_id[4]);
742
743 c->x86 = 4;
744 /* Intel-defined flags: level 0x00000001 */
745 if (c->cpuid_level >= 0x00000001) {
746 u32 junk, tfms, cap0, misc;
747
748 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
749 c->x86 = x86_family(tfms);
750 c->x86_model = x86_model(tfms);
751 c->x86_stepping = x86_stepping(tfms);
752
753 if (cap0 & (1<<19)) {
754 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
755 c->x86_cache_alignment = c->x86_clflush_size;
756 }
757 }
758}
759
760static void apply_forced_caps(struct cpuinfo_x86 *c)
761{
762 int i;
763
764 for (i = 0; i < NCAPINTS + NBUGINTS; i++) {
765 c->x86_capability[i] &= ~cpu_caps_cleared[i];
766 c->x86_capability[i] |= cpu_caps_set[i];
767 }
768}
769
770static void init_speculation_control(struct cpuinfo_x86 *c)
771{
772 /*
773 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
774 * and they also have a different bit for STIBP support. Also,
775 * a hypervisor might have set the individual AMD bits even on
776 * Intel CPUs, for finer-grained selection of what's available.
777 */
778 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
779 set_cpu_cap(c, X86_FEATURE_IBRS);
780 set_cpu_cap(c, X86_FEATURE_IBPB);
781 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
782 }
783
784 if (cpu_has(c, X86_FEATURE_INTEL_STIBP))
785 set_cpu_cap(c, X86_FEATURE_STIBP);
786
787 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) ||
788 cpu_has(c, X86_FEATURE_VIRT_SSBD))
789 set_cpu_cap(c, X86_FEATURE_SSBD);
790
791 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) {
792 set_cpu_cap(c, X86_FEATURE_IBRS);
793 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
794 }
795
796 if (cpu_has(c, X86_FEATURE_AMD_IBPB))
797 set_cpu_cap(c, X86_FEATURE_IBPB);
798
799 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) {
800 set_cpu_cap(c, X86_FEATURE_STIBP);
801 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
802 }
803
804 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) {
805 set_cpu_cap(c, X86_FEATURE_SSBD);
806 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
807 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD);
808 }
809}
810
811void get_cpu_cap(struct cpuinfo_x86 *c)
812{
813 u32 eax, ebx, ecx, edx;
814
815 /* Intel-defined flags: level 0x00000001 */
816 if (c->cpuid_level >= 0x00000001) {
817 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
818
819 c->x86_capability[CPUID_1_ECX] = ecx;
820 c->x86_capability[CPUID_1_EDX] = edx;
821 }
822
823 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
824 if (c->cpuid_level >= 0x00000006)
825 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
826
827 /* Additional Intel-defined flags: level 0x00000007 */
828 if (c->cpuid_level >= 0x00000007) {
829 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
830 c->x86_capability[CPUID_7_0_EBX] = ebx;
831 c->x86_capability[CPUID_7_ECX] = ecx;
832 c->x86_capability[CPUID_7_EDX] = edx;
833 }
834
835 /* Extended state features: level 0x0000000d */
836 if (c->cpuid_level >= 0x0000000d) {
837 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
838
839 c->x86_capability[CPUID_D_1_EAX] = eax;
840 }
841
842 /* Additional Intel-defined flags: level 0x0000000F */
843 if (c->cpuid_level >= 0x0000000F) {
844
845 /* QoS sub-leaf, EAX=0Fh, ECX=0 */
846 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx);
847 c->x86_capability[CPUID_F_0_EDX] = edx;
848
849 if (cpu_has(c, X86_FEATURE_CQM_LLC)) {
850 /* will be overridden if occupancy monitoring exists */
851 c->x86_cache_max_rmid = ebx;
852
853 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
854 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx);
855 c->x86_capability[CPUID_F_1_EDX] = edx;
856
857 if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) ||
858 ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) ||
859 (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) {
860 c->x86_cache_max_rmid = ecx;
861 c->x86_cache_occ_scale = ebx;
862 }
863 } else {
864 c->x86_cache_max_rmid = -1;
865 c->x86_cache_occ_scale = -1;
866 }
867 }
868
869 /* AMD-defined flags: level 0x80000001 */
870 eax = cpuid_eax(0x80000000);
871 c->extended_cpuid_level = eax;
872
873 if ((eax & 0xffff0000) == 0x80000000) {
874 if (eax >= 0x80000001) {
875 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
876
877 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
878 c->x86_capability[CPUID_8000_0001_EDX] = edx;
879 }
880 }
881
882 if (c->extended_cpuid_level >= 0x80000007) {
883 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
884
885 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
886 c->x86_power = edx;
887 }
888
889 if (c->extended_cpuid_level >= 0x80000008) {
890 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
891 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
892 }
893
894 if (c->extended_cpuid_level >= 0x8000000a)
895 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
896
897 init_scattered_cpuid_features(c);
898 init_speculation_control(c);
899
900 /*
901 * Clear/Set all flags overridden by options, after probe.
902 * This needs to happen each time we re-probe, which may happen
903 * several times during CPU initialization.
904 */
905 apply_forced_caps(c);
906}
907
908void get_cpu_address_sizes(struct cpuinfo_x86 *c)
909{
910 u32 eax, ebx, ecx, edx;
911
912 if (c->extended_cpuid_level >= 0x80000008) {
913 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
914
915 c->x86_virt_bits = (eax >> 8) & 0xff;
916 c->x86_phys_bits = eax & 0xff;
917 }
918#ifdef CONFIG_X86_32
919 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
920 c->x86_phys_bits = 36;
921#endif
922 c->x86_cache_bits = c->x86_phys_bits;
923}
924
925static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
926{
927#ifdef CONFIG_X86_32
928 int i;
929
930 /*
931 * First of all, decide if this is a 486 or higher
932 * It's a 486 if we can modify the AC flag
933 */
934 if (flag_is_changeable_p(X86_EFLAGS_AC))
935 c->x86 = 4;
936 else
937 c->x86 = 3;
938
939 for (i = 0; i < X86_VENDOR_NUM; i++)
940 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
941 c->x86_vendor_id[0] = 0;
942 cpu_devs[i]->c_identify(c);
943 if (c->x86_vendor_id[0]) {
944 get_cpu_vendor(c);
945 break;
946 }
947 }
948#endif
949}
950
951static const __initconst struct x86_cpu_id cpu_no_speculation[] = {
952 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SALTWELL, X86_FEATURE_ANY },
953 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SALTWELL_TABLET, X86_FEATURE_ANY },
954 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_BONNELL_MID, X86_FEATURE_ANY },
955 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SALTWELL_MID, X86_FEATURE_ANY },
956 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_BONNELL, X86_FEATURE_ANY },
957 { X86_VENDOR_CENTAUR, 5 },
958 { X86_VENDOR_INTEL, 5 },
959 { X86_VENDOR_NSC, 5 },
960 { X86_VENDOR_ANY, 4 },
961 {}
962};
963
964static const __initconst struct x86_cpu_id cpu_no_meltdown[] = {
965 { X86_VENDOR_AMD },
966 { X86_VENDOR_HYGON },
967 {}
968};
969
970/* Only list CPUs which speculate but are non susceptible to SSB */
971static const __initconst struct x86_cpu_id cpu_no_spec_store_bypass[] = {
972 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT },
973 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_AIRMONT },
974 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT_X },
975 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT_MID },
976 { X86_VENDOR_INTEL, 6, INTEL_FAM6_CORE_YONAH },
977 { X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNL },
978 { X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNM },
979 { X86_VENDOR_AMD, 0x12, },
980 { X86_VENDOR_AMD, 0x11, },
981 { X86_VENDOR_AMD, 0x10, },
982 { X86_VENDOR_AMD, 0xf, },
983 {}
984};
985
986static const __initconst struct x86_cpu_id cpu_no_l1tf[] = {
987 /* in addition to cpu_no_speculation */
988 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT },
989 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT_X },
990 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_AIRMONT },
991 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT_MID },
992 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_AIRMONT_MID },
993 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_GOLDMONT },
994 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_GOLDMONT_X },
995 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_GOLDMONT_PLUS },
996 { X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNL },
997 { X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNM },
998 {}
999};
1000
1001static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
1002{
1003 u64 ia32_cap = 0;
1004
1005 if (x86_match_cpu(cpu_no_speculation))
1006 return;
1007
1008 setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
1009 setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
1010
1011 if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES))
1012 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
1013
1014 if (!x86_match_cpu(cpu_no_spec_store_bypass) &&
1015 !(ia32_cap & ARCH_CAP_SSB_NO) &&
1016 !cpu_has(c, X86_FEATURE_AMD_SSB_NO))
1017 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
1018
1019 if (ia32_cap & ARCH_CAP_IBRS_ALL)
1020 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED);
1021
1022 if (x86_match_cpu(cpu_no_meltdown))
1023 return;
1024
1025 /* Rogue Data Cache Load? No! */
1026 if (ia32_cap & ARCH_CAP_RDCL_NO)
1027 return;
1028
1029 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
1030
1031 if (x86_match_cpu(cpu_no_l1tf))
1032 return;
1033
1034 setup_force_cpu_bug(X86_BUG_L1TF);
1035}
1036
1037/*
1038 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1039 * unfortunately, that's not true in practice because of early VIA
1040 * chips and (more importantly) broken virtualizers that are not easy
1041 * to detect. In the latter case it doesn't even *fail* reliably, so
1042 * probing for it doesn't even work. Disable it completely on 32-bit
1043 * unless we can find a reliable way to detect all the broken cases.
1044 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1045 */
1046static void detect_nopl(void)
1047{
1048#ifdef CONFIG_X86_32
1049 setup_clear_cpu_cap(X86_FEATURE_NOPL);
1050#else
1051 setup_force_cpu_cap(X86_FEATURE_NOPL);
1052#endif
1053}
1054
1055/*
1056 * Do minimum CPU detection early.
1057 * Fields really needed: vendor, cpuid_level, family, model, mask,
1058 * cache alignment.
1059 * The others are not touched to avoid unwanted side effects.
1060 *
1061 * WARNING: this function is only called on the boot CPU. Don't add code
1062 * here that is supposed to run on all CPUs.
1063 */
1064static void __init early_identify_cpu(struct cpuinfo_x86 *c)
1065{
1066#ifdef CONFIG_X86_64
1067 c->x86_clflush_size = 64;
1068 c->x86_phys_bits = 36;
1069 c->x86_virt_bits = 48;
1070#else
1071 c->x86_clflush_size = 32;
1072 c->x86_phys_bits = 32;
1073 c->x86_virt_bits = 32;
1074#endif
1075 c->x86_cache_alignment = c->x86_clflush_size;
1076
1077 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1078 c->extended_cpuid_level = 0;
1079
1080 if (!have_cpuid_p())
1081 identify_cpu_without_cpuid(c);
1082
1083 /* cyrix could have cpuid enabled via c_identify()*/
1084 if (have_cpuid_p()) {
1085 cpu_detect(c);
1086 get_cpu_vendor(c);
1087 get_cpu_cap(c);
1088 get_cpu_address_sizes(c);
1089 setup_force_cpu_cap(X86_FEATURE_CPUID);
1090
1091 if (this_cpu->c_early_init)
1092 this_cpu->c_early_init(c);
1093
1094 c->cpu_index = 0;
1095 filter_cpuid_features(c, false);
1096
1097 if (this_cpu->c_bsp_init)
1098 this_cpu->c_bsp_init(c);
1099 } else {
1100 setup_clear_cpu_cap(X86_FEATURE_CPUID);
1101 }
1102
1103 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
1104
1105 cpu_set_bug_bits(c);
1106
1107 fpu__init_system(c);
1108
1109#ifdef CONFIG_X86_32
1110 /*
1111 * Regardless of whether PCID is enumerated, the SDM says
1112 * that it can't be enabled in 32-bit mode.
1113 */
1114 setup_clear_cpu_cap(X86_FEATURE_PCID);
1115#endif
1116
1117 /*
1118 * Later in the boot process pgtable_l5_enabled() relies on
1119 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not
1120 * enabled by this point we need to clear the feature bit to avoid
1121 * false-positives at the later stage.
1122 *
1123 * pgtable_l5_enabled() can be false here for several reasons:
1124 * - 5-level paging is disabled compile-time;
1125 * - it's 32-bit kernel;
1126 * - machine doesn't support 5-level paging;
1127 * - user specified 'no5lvl' in kernel command line.
1128 */
1129 if (!pgtable_l5_enabled())
1130 setup_clear_cpu_cap(X86_FEATURE_LA57);
1131
1132 detect_nopl();
1133}
1134
1135void __init early_cpu_init(void)
1136{
1137 const struct cpu_dev *const *cdev;
1138 int count = 0;
1139
1140#ifdef CONFIG_PROCESSOR_SELECT
1141 pr_info("KERNEL supported cpus:\n");
1142#endif
1143
1144 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
1145 const struct cpu_dev *cpudev = *cdev;
1146
1147 if (count >= X86_VENDOR_NUM)
1148 break;
1149 cpu_devs[count] = cpudev;
1150 count++;
1151
1152#ifdef CONFIG_PROCESSOR_SELECT
1153 {
1154 unsigned int j;
1155
1156 for (j = 0; j < 2; j++) {
1157 if (!cpudev->c_ident[j])
1158 continue;
1159 pr_info(" %s %s\n", cpudev->c_vendor,
1160 cpudev->c_ident[j]);
1161 }
1162 }
1163#endif
1164 }
1165 early_identify_cpu(&boot_cpu_data);
1166}
1167
1168static void detect_null_seg_behavior(struct cpuinfo_x86 *c)
1169{
1170#ifdef CONFIG_X86_64
1171 /*
1172 * Empirically, writing zero to a segment selector on AMD does
1173 * not clear the base, whereas writing zero to a segment
1174 * selector on Intel does clear the base. Intel's behavior
1175 * allows slightly faster context switches in the common case
1176 * where GS is unused by the prev and next threads.
1177 *
1178 * Since neither vendor documents this anywhere that I can see,
1179 * detect it directly instead of hardcoding the choice by
1180 * vendor.
1181 *
1182 * I've designated AMD's behavior as the "bug" because it's
1183 * counterintuitive and less friendly.
1184 */
1185
1186 unsigned long old_base, tmp;
1187 rdmsrl(MSR_FS_BASE, old_base);
1188 wrmsrl(MSR_FS_BASE, 1);
1189 loadsegment(fs, 0);
1190 rdmsrl(MSR_FS_BASE, tmp);
1191 if (tmp != 0)
1192 set_cpu_bug(c, X86_BUG_NULL_SEG);
1193 wrmsrl(MSR_FS_BASE, old_base);
1194#endif
1195}
1196
1197static void generic_identify(struct cpuinfo_x86 *c)
1198{
1199 c->extended_cpuid_level = 0;
1200
1201 if (!have_cpuid_p())
1202 identify_cpu_without_cpuid(c);
1203
1204 /* cyrix could have cpuid enabled via c_identify()*/
1205 if (!have_cpuid_p())
1206 return;
1207
1208 cpu_detect(c);
1209
1210 get_cpu_vendor(c);
1211
1212 get_cpu_cap(c);
1213
1214 get_cpu_address_sizes(c);
1215
1216 if (c->cpuid_level >= 0x00000001) {
1217 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
1218#ifdef CONFIG_X86_32
1219# ifdef CONFIG_SMP
1220 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1221# else
1222 c->apicid = c->initial_apicid;
1223# endif
1224#endif
1225 c->phys_proc_id = c->initial_apicid;
1226 }
1227
1228 get_model_name(c); /* Default name */
1229
1230 detect_null_seg_behavior(c);
1231
1232 /*
1233 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1234 * systems that run Linux at CPL > 0 may or may not have the
1235 * issue, but, even if they have the issue, there's absolutely
1236 * nothing we can do about it because we can't use the real IRET
1237 * instruction.
1238 *
1239 * NB: For the time being, only 32-bit kernels support
1240 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1241 * whether to apply espfix using paravirt hooks. If any
1242 * non-paravirt system ever shows up that does *not* have the
1243 * ESPFIX issue, we can change this.
1244 */
1245#ifdef CONFIG_X86_32
1246# ifdef CONFIG_PARAVIRT_XXL
1247 do {
1248 extern void native_iret(void);
1249 if (pv_ops.cpu.iret == native_iret)
1250 set_cpu_bug(c, X86_BUG_ESPFIX);
1251 } while (0);
1252# else
1253 set_cpu_bug(c, X86_BUG_ESPFIX);
1254# endif
1255#endif
1256}
1257
1258static void x86_init_cache_qos(struct cpuinfo_x86 *c)
1259{
1260 /*
1261 * The heavy lifting of max_rmid and cache_occ_scale are handled
1262 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu
1263 * in case CQM bits really aren't there in this CPU.
1264 */
1265 if (c != &boot_cpu_data) {
1266 boot_cpu_data.x86_cache_max_rmid =
1267 min(boot_cpu_data.x86_cache_max_rmid,
1268 c->x86_cache_max_rmid);
1269 }
1270}
1271
1272/*
1273 * Validate that ACPI/mptables have the same information about the
1274 * effective APIC id and update the package map.
1275 */
1276static void validate_apic_and_package_id(struct cpuinfo_x86 *c)
1277{
1278#ifdef CONFIG_SMP
1279 unsigned int apicid, cpu = smp_processor_id();
1280
1281 apicid = apic->cpu_present_to_apicid(cpu);
1282
1283 if (apicid != c->apicid) {
1284 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1285 cpu, apicid, c->initial_apicid);
1286 }
1287 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu));
1288#else
1289 c->logical_proc_id = 0;
1290#endif
1291}
1292
1293/*
1294 * This does the hard work of actually picking apart the CPU stuff...
1295 */
1296static void identify_cpu(struct cpuinfo_x86 *c)
1297{
1298 int i;
1299
1300 c->loops_per_jiffy = loops_per_jiffy;
1301 c->x86_cache_size = 0;
1302 c->x86_vendor = X86_VENDOR_UNKNOWN;
1303 c->x86_model = c->x86_stepping = 0; /* So far unknown... */
1304 c->x86_vendor_id[0] = '\0'; /* Unset */
1305 c->x86_model_id[0] = '\0'; /* Unset */
1306 c->x86_max_cores = 1;
1307 c->x86_coreid_bits = 0;
1308 c->cu_id = 0xff;
1309#ifdef CONFIG_X86_64
1310 c->x86_clflush_size = 64;
1311 c->x86_phys_bits = 36;
1312 c->x86_virt_bits = 48;
1313#else
1314 c->cpuid_level = -1; /* CPUID not detected */
1315 c->x86_clflush_size = 32;
1316 c->x86_phys_bits = 32;
1317 c->x86_virt_bits = 32;
1318#endif
1319 c->x86_cache_alignment = c->x86_clflush_size;
1320 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1321
1322 generic_identify(c);
1323
1324 if (this_cpu->c_identify)
1325 this_cpu->c_identify(c);
1326
1327 /* Clear/Set all flags overridden by options, after probe */
1328 apply_forced_caps(c);
1329
1330#ifdef CONFIG_X86_64
1331 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1332#endif
1333
1334 /*
1335 * Vendor-specific initialization. In this section we
1336 * canonicalize the feature flags, meaning if there are
1337 * features a certain CPU supports which CPUID doesn't
1338 * tell us, CPUID claiming incorrect flags, or other bugs,
1339 * we handle them here.
1340 *
1341 * At the end of this section, c->x86_capability better
1342 * indicate the features this CPU genuinely supports!
1343 */
1344 if (this_cpu->c_init)
1345 this_cpu->c_init(c);
1346
1347 /* Disable the PN if appropriate */
1348 squash_the_stupid_serial_number(c);
1349
1350 /* Set up SMEP/SMAP/UMIP */
1351 setup_smep(c);
1352 setup_smap(c);
1353 setup_umip(c);
1354
1355 /*
1356 * The vendor-specific functions might have changed features.
1357 * Now we do "generic changes."
1358 */
1359
1360 /* Filter out anything that depends on CPUID levels we don't have */
1361 filter_cpuid_features(c, true);
1362
1363 /* If the model name is still unset, do table lookup. */
1364 if (!c->x86_model_id[0]) {
1365 const char *p;
1366 p = table_lookup_model(c);
1367 if (p)
1368 strcpy(c->x86_model_id, p);
1369 else
1370 /* Last resort... */
1371 sprintf(c->x86_model_id, "%02x/%02x",
1372 c->x86, c->x86_model);
1373 }
1374
1375#ifdef CONFIG_X86_64
1376 detect_ht(c);
1377#endif
1378
1379 x86_init_rdrand(c);
1380 x86_init_cache_qos(c);
1381 setup_pku(c);
1382
1383 /*
1384 * Clear/Set all flags overridden by options, need do it
1385 * before following smp all cpus cap AND.
1386 */
1387 apply_forced_caps(c);
1388
1389 /*
1390 * On SMP, boot_cpu_data holds the common feature set between
1391 * all CPUs; so make sure that we indicate which features are
1392 * common between the CPUs. The first time this routine gets
1393 * executed, c == &boot_cpu_data.
1394 */
1395 if (c != &boot_cpu_data) {
1396 /* AND the already accumulated flags with these */
1397 for (i = 0; i < NCAPINTS; i++)
1398 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1399
1400 /* OR, i.e. replicate the bug flags */
1401 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1402 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1403 }
1404
1405 /* Init Machine Check Exception if available. */
1406 mcheck_cpu_init(c);
1407
1408 select_idle_routine(c);
1409
1410#ifdef CONFIG_NUMA
1411 numa_add_cpu(smp_processor_id());
1412#endif
1413}
1414
1415/*
1416 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1417 * on 32-bit kernels:
1418 */
1419#ifdef CONFIG_X86_32
1420void enable_sep_cpu(void)
1421{
1422 struct tss_struct *tss;
1423 int cpu;
1424
1425 if (!boot_cpu_has(X86_FEATURE_SEP))
1426 return;
1427
1428 cpu = get_cpu();
1429 tss = &per_cpu(cpu_tss_rw, cpu);
1430
1431 /*
1432 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1433 * see the big comment in struct x86_hw_tss's definition.
1434 */
1435
1436 tss->x86_tss.ss1 = __KERNEL_CS;
1437 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1438 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0);
1439 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1440
1441 put_cpu();
1442}
1443#endif
1444
1445void __init identify_boot_cpu(void)
1446{
1447 identify_cpu(&boot_cpu_data);
1448#ifdef CONFIG_X86_32
1449 sysenter_setup();
1450 enable_sep_cpu();
1451#endif
1452 cpu_detect_tlb(&boot_cpu_data);
1453}
1454
1455void identify_secondary_cpu(struct cpuinfo_x86 *c)
1456{
1457 BUG_ON(c == &boot_cpu_data);
1458 identify_cpu(c);
1459#ifdef CONFIG_X86_32
1460 enable_sep_cpu();
1461#endif
1462 mtrr_ap_init();
1463 validate_apic_and_package_id(c);
1464 x86_spec_ctrl_setup_ap();
1465}
1466
1467static __init int setup_noclflush(char *arg)
1468{
1469 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1470 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1471 return 1;
1472}
1473__setup("noclflush", setup_noclflush);
1474
1475void print_cpu_info(struct cpuinfo_x86 *c)
1476{
1477 const char *vendor = NULL;
1478
1479 if (c->x86_vendor < X86_VENDOR_NUM) {
1480 vendor = this_cpu->c_vendor;
1481 } else {
1482 if (c->cpuid_level >= 0)
1483 vendor = c->x86_vendor_id;
1484 }
1485
1486 if (vendor && !strstr(c->x86_model_id, vendor))
1487 pr_cont("%s ", vendor);
1488
1489 if (c->x86_model_id[0])
1490 pr_cont("%s", c->x86_model_id);
1491 else
1492 pr_cont("%d86", c->x86);
1493
1494 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1495
1496 if (c->x86_stepping || c->cpuid_level >= 0)
1497 pr_cont(", stepping: 0x%x)\n", c->x86_stepping);
1498 else
1499 pr_cont(")\n");
1500}
1501
1502/*
1503 * clearcpuid= was already parsed in fpu__init_parse_early_param.
1504 * But we need to keep a dummy __setup around otherwise it would
1505 * show up as an environment variable for init.
1506 */
1507static __init int setup_clearcpuid(char *arg)
1508{
1509 return 1;
1510}
1511__setup("clearcpuid=", setup_clearcpuid);
1512
1513#ifdef CONFIG_X86_64
1514DEFINE_PER_CPU_FIRST(union irq_stack_union,
1515 irq_stack_union) __aligned(PAGE_SIZE) __visible;
1516EXPORT_PER_CPU_SYMBOL_GPL(irq_stack_union);
1517
1518/*
1519 * The following percpu variables are hot. Align current_task to
1520 * cacheline size such that they fall in the same cacheline.
1521 */
1522DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1523 &init_task;
1524EXPORT_PER_CPU_SYMBOL(current_task);
1525
1526DEFINE_PER_CPU(char *, irq_stack_ptr) =
1527 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE;
1528
1529DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1530
1531DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1532EXPORT_PER_CPU_SYMBOL(__preempt_count);
1533
1534/* May not be marked __init: used by software suspend */
1535void syscall_init(void)
1536{
1537 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
1538 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
1539
1540#ifdef CONFIG_IA32_EMULATION
1541 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
1542 /*
1543 * This only works on Intel CPUs.
1544 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1545 * This does not cause SYSENTER to jump to the wrong location, because
1546 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1547 */
1548 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1549 wrmsrl_safe(MSR_IA32_SYSENTER_ESP,
1550 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1));
1551 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1552#else
1553 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret);
1554 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1555 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1556 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1557#endif
1558
1559 /* Flags to clear on syscall */
1560 wrmsrl(MSR_SYSCALL_MASK,
1561 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1562 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
1563}
1564
1565/*
1566 * Copies of the original ist values from the tss are only accessed during
1567 * debugging, no special alignment required.
1568 */
1569DEFINE_PER_CPU(struct orig_ist, orig_ist);
1570
1571static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
1572DEFINE_PER_CPU(int, debug_stack_usage);
1573
1574int is_debug_stack(unsigned long addr)
1575{
1576 return __this_cpu_read(debug_stack_usage) ||
1577 (addr <= __this_cpu_read(debug_stack_addr) &&
1578 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ));
1579}
1580NOKPROBE_SYMBOL(is_debug_stack);
1581
1582DEFINE_PER_CPU(u32, debug_idt_ctr);
1583
1584void debug_stack_set_zero(void)
1585{
1586 this_cpu_inc(debug_idt_ctr);
1587 load_current_idt();
1588}
1589NOKPROBE_SYMBOL(debug_stack_set_zero);
1590
1591void debug_stack_reset(void)
1592{
1593 if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
1594 return;
1595 if (this_cpu_dec_return(debug_idt_ctr) == 0)
1596 load_current_idt();
1597}
1598NOKPROBE_SYMBOL(debug_stack_reset);
1599
1600#else /* CONFIG_X86_64 */
1601
1602DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1603EXPORT_PER_CPU_SYMBOL(current_task);
1604DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1605EXPORT_PER_CPU_SYMBOL(__preempt_count);
1606
1607/*
1608 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1609 * the top of the kernel stack. Use an extra percpu variable to track the
1610 * top of the kernel stack directly.
1611 */
1612DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
1613 (unsigned long)&init_thread_union + THREAD_SIZE;
1614EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
1615
1616#ifdef CONFIG_STACKPROTECTOR
1617DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1618#endif
1619
1620#endif /* CONFIG_X86_64 */
1621
1622/*
1623 * Clear all 6 debug registers:
1624 */
1625static void clear_all_debug_regs(void)
1626{
1627 int i;
1628
1629 for (i = 0; i < 8; i++) {
1630 /* Ignore db4, db5 */
1631 if ((i == 4) || (i == 5))
1632 continue;
1633
1634 set_debugreg(0, i);
1635 }
1636}
1637
1638#ifdef CONFIG_KGDB
1639/*
1640 * Restore debug regs if using kgdbwait and you have a kernel debugger
1641 * connection established.
1642 */
1643static void dbg_restore_debug_regs(void)
1644{
1645 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1646 arch_kgdb_ops.correct_hw_break();
1647}
1648#else /* ! CONFIG_KGDB */
1649#define dbg_restore_debug_regs()
1650#endif /* ! CONFIG_KGDB */
1651
1652static void wait_for_master_cpu(int cpu)
1653{
1654#ifdef CONFIG_SMP
1655 /*
1656 * wait for ACK from master CPU before continuing
1657 * with AP initialization
1658 */
1659 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
1660 while (!cpumask_test_cpu(cpu, cpu_callout_mask))
1661 cpu_relax();
1662#endif
1663}
1664
1665#ifdef CONFIG_X86_64
1666static void setup_getcpu(int cpu)
1667{
1668 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu));
1669 struct desc_struct d = { };
1670
1671 if (static_cpu_has(X86_FEATURE_RDTSCP))
1672 write_rdtscp_aux(cpudata);
1673
1674 /* Store CPU and node number in limit. */
1675 d.limit0 = cpudata;
1676 d.limit1 = cpudata >> 16;
1677
1678 d.type = 5; /* RO data, expand down, accessed */
1679 d.dpl = 3; /* Visible to user code */
1680 d.s = 1; /* Not a system segment */
1681 d.p = 1; /* Present */
1682 d.d = 1; /* 32-bit */
1683
1684 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S);
1685}
1686#endif
1687
1688/*
1689 * cpu_init() initializes state that is per-CPU. Some data is already
1690 * initialized (naturally) in the bootstrap process, such as the GDT
1691 * and IDT. We reload them nevertheless, this function acts as a
1692 * 'CPU state barrier', nothing should get across.
1693 * A lot of state is already set up in PDA init for 64 bit
1694 */
1695#ifdef CONFIG_X86_64
1696
1697void cpu_init(void)
1698{
1699 struct orig_ist *oist;
1700 struct task_struct *me;
1701 struct tss_struct *t;
1702 unsigned long v;
1703 int cpu = raw_smp_processor_id();
1704 int i;
1705
1706 wait_for_master_cpu(cpu);
1707
1708 /*
1709 * Initialize the CR4 shadow before doing anything that could
1710 * try to read it.
1711 */
1712 cr4_init_shadow();
1713
1714 if (cpu)
1715 load_ucode_ap();
1716
1717 t = &per_cpu(cpu_tss_rw, cpu);
1718 oist = &per_cpu(orig_ist, cpu);
1719
1720#ifdef CONFIG_NUMA
1721 if (this_cpu_read(numa_node) == 0 &&
1722 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1723 set_numa_node(early_cpu_to_node(cpu));
1724#endif
1725 setup_getcpu(cpu);
1726
1727 me = current;
1728
1729 pr_debug("Initializing CPU#%d\n", cpu);
1730
1731 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1732
1733 /*
1734 * Initialize the per-CPU GDT with the boot GDT,
1735 * and set up the GDT descriptor:
1736 */
1737
1738 switch_to_new_gdt(cpu);
1739 loadsegment(fs, 0);
1740
1741 load_current_idt();
1742
1743 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1744 syscall_init();
1745
1746 wrmsrl(MSR_FS_BASE, 0);
1747 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1748 barrier();
1749
1750 x86_configure_nx();
1751 x2apic_setup();
1752
1753 /*
1754 * set up and load the per-CPU TSS
1755 */
1756 if (!oist->ist[0]) {
1757 char *estacks = get_cpu_entry_area(cpu)->exception_stacks;
1758
1759 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1760 estacks += exception_stack_sizes[v];
1761 oist->ist[v] = t->x86_tss.ist[v] =
1762 (unsigned long)estacks;
1763 if (v == DEBUG_STACK-1)
1764 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
1765 }
1766 }
1767
1768 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET;
1769
1770 /*
1771 * <= is required because the CPU will access up to
1772 * 8 bits beyond the end of the IO permission bitmap.
1773 */
1774 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1775 t->io_bitmap[i] = ~0UL;
1776
1777 mmgrab(&init_mm);
1778 me->active_mm = &init_mm;
1779 BUG_ON(me->mm);
1780 initialize_tlbstate_and_flush();
1781 enter_lazy_tlb(&init_mm, me);
1782
1783 /*
1784 * Initialize the TSS. sp0 points to the entry trampoline stack
1785 * regardless of what task is running.
1786 */
1787 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
1788 load_TR_desc();
1789 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1));
1790
1791 load_mm_ldt(&init_mm);
1792
1793 clear_all_debug_regs();
1794 dbg_restore_debug_regs();
1795
1796 fpu__init_cpu();
1797
1798 if (is_uv_system())
1799 uv_cpu_init();
1800
1801 load_fixmap_gdt(cpu);
1802}
1803
1804#else
1805
1806void cpu_init(void)
1807{
1808 int cpu = smp_processor_id();
1809 struct task_struct *curr = current;
1810 struct tss_struct *t = &per_cpu(cpu_tss_rw, cpu);
1811
1812 wait_for_master_cpu(cpu);
1813
1814 /*
1815 * Initialize the CR4 shadow before doing anything that could
1816 * try to read it.
1817 */
1818 cr4_init_shadow();
1819
1820 show_ucode_info_early();
1821
1822 pr_info("Initializing CPU#%d\n", cpu);
1823
1824 if (cpu_feature_enabled(X86_FEATURE_VME) ||
1825 boot_cpu_has(X86_FEATURE_TSC) ||
1826 boot_cpu_has(X86_FEATURE_DE))
1827 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1828
1829 load_current_idt();
1830 switch_to_new_gdt(cpu);
1831
1832 /*
1833 * Set up and load the per-CPU TSS and LDT
1834 */
1835 mmgrab(&init_mm);
1836 curr->active_mm = &init_mm;
1837 BUG_ON(curr->mm);
1838 initialize_tlbstate_and_flush();
1839 enter_lazy_tlb(&init_mm, curr);
1840
1841 /*
1842 * Initialize the TSS. sp0 points to the entry trampoline stack
1843 * regardless of what task is running.
1844 */
1845 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
1846 load_TR_desc();
1847 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1));
1848
1849 load_mm_ldt(&init_mm);
1850
1851 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET;
1852
1853#ifdef CONFIG_DOUBLEFAULT
1854 /* Set up doublefault TSS pointer in the GDT */
1855 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1856#endif
1857
1858 clear_all_debug_regs();
1859 dbg_restore_debug_regs();
1860
1861 fpu__init_cpu();
1862
1863 load_fixmap_gdt(cpu);
1864}
1865#endif
1866
1867static void bsp_resume(void)
1868{
1869 if (this_cpu->c_bsp_resume)
1870 this_cpu->c_bsp_resume(&boot_cpu_data);
1871}
1872
1873static struct syscore_ops cpu_syscore_ops = {
1874 .resume = bsp_resume,
1875};
1876
1877static int __init init_cpu_syscore(void)
1878{
1879 register_syscore_ops(&cpu_syscore_ops);
1880 return 0;
1881}
1882core_initcall(init_cpu_syscore);
1883
1884/*
1885 * The microcode loader calls this upon late microcode load to recheck features,
1886 * only when microcode has been updated. Caller holds microcode_mutex and CPU
1887 * hotplug lock.
1888 */
1889void microcode_check(void)
1890{
1891 struct cpuinfo_x86 info;
1892
1893 perf_check_microcode();
1894
1895 /* Reload CPUID max function as it might've changed. */
1896 info.cpuid_level = cpuid_eax(0);
1897
1898 /*
1899 * Copy all capability leafs to pick up the synthetic ones so that
1900 * memcmp() below doesn't fail on that. The ones coming from CPUID will
1901 * get overwritten in get_cpu_cap().
1902 */
1903 memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability));
1904
1905 get_cpu_cap(&info);
1906
1907 if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)))
1908 return;
1909
1910 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");
1911 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
1912}
1913