1/*
2 * Machine check handler.
3 *
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
8 * Author: Andi Kleen
9 */
10
11#include <linux/thread_info.h>
12#include <linux/capability.h>
13#include <linux/miscdevice.h>
14#include <linux/ratelimit.h>
15#include <linux/rcupdate.h>
16#include <linux/kobject.h>
17#include <linux/uaccess.h>
18#include <linux/kdebug.h>
19#include <linux/kernel.h>
20#include <linux/percpu.h>
21#include <linux/string.h>
22#include <linux/device.h>
23#include <linux/syscore_ops.h>
24#include <linux/delay.h>
25#include <linux/ctype.h>
26#include <linux/sched.h>
27#include <linux/sysfs.h>
28#include <linux/types.h>
29#include <linux/slab.h>
30#include <linux/init.h>
31#include <linux/kmod.h>
32#include <linux/poll.h>
33#include <linux/nmi.h>
34#include <linux/cpu.h>
35#include <linux/ras.h>
36#include <linux/smp.h>
37#include <linux/fs.h>
38#include <linux/mm.h>
39#include <linux/debugfs.h>
40#include <linux/irq_work.h>
41#include <linux/export.h>
42#include <linux/jump_label.h>
43#include <linux/set_memory.h>
44
45#include <asm/intel-family.h>
46#include <asm/processor.h>
47#include <asm/traps.h>
48#include <asm/tlbflush.h>
49#include <asm/mce.h>
50#include <asm/msr.h>
51#include <asm/reboot.h>
52
53#include "internal.h"
54
55static DEFINE_MUTEX(mce_log_mutex);
56
57/* sysfs synchronization */
58static DEFINE_MUTEX(mce_sysfs_mutex);
59
60#define CREATE_TRACE_POINTS
61#include <trace/events/mce.h>
62
63#define SPINUNIT 100 /* 100ns */
64
65DEFINE_PER_CPU(unsigned, mce_exception_count);
66
67struct mce_bank *mce_banks __read_mostly;
68struct mce_vendor_flags mce_flags __read_mostly;
69
70struct mca_config mca_cfg __read_mostly = {
71 .bootlog = -1,
72 /*
73 * Tolerant levels:
74 * 0: always panic on uncorrected errors, log corrected errors
75 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
76 * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors
77 * 3: never panic or SIGBUS, log all errors (for testing only)
78 */
79 .tolerant = 1,
80 .monarch_timeout = -1
81};
82
83static DEFINE_PER_CPU(struct mce, mces_seen);
84static unsigned long mce_need_notify;
85static int cpu_missing;
86
87/*
88 * MCA banks polled by the period polling timer for corrected events.
89 * With Intel CMCI, this only has MCA banks which do not support CMCI (if any).
90 */
91DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
92 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
93};
94
95/*
96 * MCA banks controlled through firmware first for corrected errors.
97 * This is a global list of banks for which we won't enable CMCI and we
98 * won't poll. Firmware controls these banks and is responsible for
99 * reporting corrected errors through GHES. Uncorrected/recoverable
100 * errors are still notified through a machine check.
101 */
102mce_banks_t mce_banks_ce_disabled;
103
104static struct work_struct mce_work;
105static struct irq_work mce_irq_work;
106
107static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs);
108
109/*
110 * CPU/chipset specific EDAC code can register a notifier call here to print
111 * MCE errors in a human-readable form.
112 */
113BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain);
114
115/* Do initial initialization of a struct mce */
116void mce_setup(struct mce *m)
117{
118 memset(m, 0, sizeof(struct mce));
119 m->cpu = m->extcpu = smp_processor_id();
120 /* need the internal __ version to avoid deadlocks */
121 m->time = __ktime_get_real_seconds();
122 m->cpuvendor = boot_cpu_data.x86_vendor;
123 m->cpuid = cpuid_eax(1);
124 m->socketid = cpu_data(m->extcpu).phys_proc_id;
125 m->apicid = cpu_data(m->extcpu).initial_apicid;
126 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
127
128 if (this_cpu_has(X86_FEATURE_INTEL_PPIN))
129 rdmsrl(MSR_PPIN, m->ppin);
130
131 m->microcode = boot_cpu_data.microcode;
132}
133
134DEFINE_PER_CPU(struct mce, injectm);
135EXPORT_PER_CPU_SYMBOL_GPL(injectm);
136
137void mce_log(struct mce *m)
138{
139 if (!mce_gen_pool_add(m))
140 irq_work_queue(&mce_irq_work);
141}
142
143void mce_inject_log(struct mce *m)
144{
145 mutex_lock(&mce_log_mutex);
146 mce_log(m);
147 mutex_unlock(&mce_log_mutex);
148}
149EXPORT_SYMBOL_GPL(mce_inject_log);
150
151static struct notifier_block mce_srao_nb;
152
153/*
154 * We run the default notifier if we have only the SRAO, the first and the
155 * default notifier registered. I.e., the mandatory NUM_DEFAULT_NOTIFIERS
156 * notifiers registered on the chain.
157 */
158#define NUM_DEFAULT_NOTIFIERS 3
159static atomic_t num_notifiers;
160
161void mce_register_decode_chain(struct notifier_block *nb)
162{
163 if (WARN_ON(nb->priority > MCE_PRIO_MCELOG && nb->priority < MCE_PRIO_EDAC))
164 return;
165
166 atomic_inc(&num_notifiers);
167
168 blocking_notifier_chain_register(&x86_mce_decoder_chain, nb);
169}
170EXPORT_SYMBOL_GPL(mce_register_decode_chain);
171
172void mce_unregister_decode_chain(struct notifier_block *nb)
173{
174 atomic_dec(&num_notifiers);
175
176 blocking_notifier_chain_unregister(&x86_mce_decoder_chain, nb);
177}
178EXPORT_SYMBOL_GPL(mce_unregister_decode_chain);
179
180static inline u32 ctl_reg(int bank)
181{
182 return MSR_IA32_MCx_CTL(bank);
183}
184
185static inline u32 status_reg(int bank)
186{
187 return MSR_IA32_MCx_STATUS(bank);
188}
189
190static inline u32 addr_reg(int bank)
191{
192 return MSR_IA32_MCx_ADDR(bank);
193}
194
195static inline u32 misc_reg(int bank)
196{
197 return MSR_IA32_MCx_MISC(bank);
198}
199
200static inline u32 smca_ctl_reg(int bank)
201{
202 return MSR_AMD64_SMCA_MCx_CTL(bank);
203}
204
205static inline u32 smca_status_reg(int bank)
206{
207 return MSR_AMD64_SMCA_MCx_STATUS(bank);
208}
209
210static inline u32 smca_addr_reg(int bank)
211{
212 return MSR_AMD64_SMCA_MCx_ADDR(bank);
213}
214
215static inline u32 smca_misc_reg(int bank)
216{
217 return MSR_AMD64_SMCA_MCx_MISC(bank);
218}
219
220struct mca_msr_regs msr_ops = {
221 .ctl = ctl_reg,
222 .status = status_reg,
223 .addr = addr_reg,
224 .misc = misc_reg
225};
226
227static void __print_mce(struct mce *m)
228{
229 pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n",
230 m->extcpu,
231 (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""),
232 m->mcgstatus, m->bank, m->status);
233
234 if (m->ip) {
235 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
236 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
237 m->cs, m->ip);
238
239 if (m->cs == __KERNEL_CS)
240 pr_cont("{%pS}", (void *)(unsigned long)m->ip);
241 pr_cont("\n");
242 }
243
244 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
245 if (m->addr)
246 pr_cont("ADDR %llx ", m->addr);
247 if (m->misc)
248 pr_cont("MISC %llx ", m->misc);
249
250 if (mce_flags.smca) {
251 if (m->synd)
252 pr_cont("SYND %llx ", m->synd);
253 if (m->ipid)
254 pr_cont("IPID %llx ", m->ipid);
255 }
256
257 pr_cont("\n");
258 /*
259 * Note this output is parsed by external tools and old fields
260 * should not be changed.
261 */
262 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
263 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
264 m->microcode);
265}
266
267static void print_mce(struct mce *m)
268{
269 __print_mce(m);
270
271 if (m->cpuvendor != X86_VENDOR_AMD && m->cpuvendor != X86_VENDOR_HYGON)
272 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
273}
274
275#define PANIC_TIMEOUT 5 /* 5 seconds */
276
277static atomic_t mce_panicked;
278
279static int fake_panic;
280static atomic_t mce_fake_panicked;
281
282/* Panic in progress. Enable interrupts and wait for final IPI */
283static void wait_for_panic(void)
284{
285 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
286
287 preempt_disable();
288 local_irq_enable();
289 while (timeout-- > 0)
290 udelay(1);
291 if (panic_timeout == 0)
292 panic_timeout = mca_cfg.panic_timeout;
293 panic("Panicing machine check CPU died");
294}
295
296static void mce_panic(const char *msg, struct mce *final, char *exp)
297{
298 int apei_err = 0;
299 struct llist_node *pending;
300 struct mce_evt_llist *l;
301
302 if (!fake_panic) {
303 /*
304 * Make sure only one CPU runs in machine check panic
305 */
306 if (atomic_inc_return(&mce_panicked) > 1)
307 wait_for_panic();
308 barrier();
309
310 bust_spinlocks(1);
311 console_verbose();
312 } else {
313 /* Don't log too much for fake panic */
314 if (atomic_inc_return(&mce_fake_panicked) > 1)
315 return;
316 }
317 pending = mce_gen_pool_prepare_records();
318 /* First print corrected ones that are still unlogged */
319 llist_for_each_entry(l, pending, llnode) {
320 struct mce *m = &l->mce;
321 if (!(m->status & MCI_STATUS_UC)) {
322 print_mce(m);
323 if (!apei_err)
324 apei_err = apei_write_mce(m);
325 }
326 }
327 /* Now print uncorrected but with the final one last */
328 llist_for_each_entry(l, pending, llnode) {
329 struct mce *m = &l->mce;
330 if (!(m->status & MCI_STATUS_UC))
331 continue;
332 if (!final || mce_cmp(m, final)) {
333 print_mce(m);
334 if (!apei_err)
335 apei_err = apei_write_mce(m);
336 }
337 }
338 if (final) {
339 print_mce(final);
340 if (!apei_err)
341 apei_err = apei_write_mce(final);
342 }
343 if (cpu_missing)
344 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
345 if (exp)
346 pr_emerg(HW_ERR "Machine check: %s\n", exp);
347 if (!fake_panic) {
348 if (panic_timeout == 0)
349 panic_timeout = mca_cfg.panic_timeout;
350 panic(msg);
351 } else
352 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
353}
354
355/* Support code for software error injection */
356
357static int msr_to_offset(u32 msr)
358{
359 unsigned bank = __this_cpu_read(injectm.bank);
360
361 if (msr == mca_cfg.rip_msr)
362 return offsetof(struct mce, ip);
363 if (msr == msr_ops.status(bank))
364 return offsetof(struct mce, status);
365 if (msr == msr_ops.addr(bank))
366 return offsetof(struct mce, addr);
367 if (msr == msr_ops.misc(bank))
368 return offsetof(struct mce, misc);
369 if (msr == MSR_IA32_MCG_STATUS)
370 return offsetof(struct mce, mcgstatus);
371 return -1;
372}
373
374/* MSR access wrappers used for error injection */
375static u64 mce_rdmsrl(u32 msr)
376{
377 u64 v;
378
379 if (__this_cpu_read(injectm.finished)) {
380 int offset = msr_to_offset(msr);
381
382 if (offset < 0)
383 return 0;
384 return *(u64 *)((char *)this_cpu_ptr(&injectm) + offset);
385 }
386
387 if (rdmsrl_safe(msr, &v)) {
388 WARN_ONCE(1, "mce: Unable to read MSR 0x%x!\n", msr);
389 /*
390 * Return zero in case the access faulted. This should
391 * not happen normally but can happen if the CPU does
392 * something weird, or if the code is buggy.
393 */
394 v = 0;
395 }
396
397 return v;
398}
399
400static void mce_wrmsrl(u32 msr, u64 v)
401{
402 if (__this_cpu_read(injectm.finished)) {
403 int offset = msr_to_offset(msr);
404
405 if (offset >= 0)
406 *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v;
407 return;
408 }
409 wrmsrl(msr, v);
410}
411
412/*
413 * Collect all global (w.r.t. this processor) status about this machine
414 * check into our "mce" struct so that we can use it later to assess
415 * the severity of the problem as we read per-bank specific details.
416 */
417static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
418{
419 mce_setup(m);
420
421 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
422 if (regs) {
423 /*
424 * Get the address of the instruction at the time of
425 * the machine check error.
426 */
427 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
428 m->ip = regs->ip;
429 m->cs = regs->cs;
430
431 /*
432 * When in VM86 mode make the cs look like ring 3
433 * always. This is a lie, but it's better than passing
434 * the additional vm86 bit around everywhere.
435 */
436 if (v8086_mode(regs))
437 m->cs |= 3;
438 }
439 /* Use accurate RIP reporting if available. */
440 if (mca_cfg.rip_msr)
441 m->ip = mce_rdmsrl(mca_cfg.rip_msr);
442 }
443}
444
445int mce_available(struct cpuinfo_x86 *c)
446{
447 if (mca_cfg.disabled)
448 return 0;
449 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
450}
451
452static void mce_schedule_work(void)
453{
454 if (!mce_gen_pool_empty())
455 schedule_work(&mce_work);
456}
457
458static void mce_irq_work_cb(struct irq_work *entry)
459{
460 mce_schedule_work();
461}
462
463static void mce_report_event(struct pt_regs *regs)
464{
465 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
466 mce_notify_irq();
467 /*
468 * Triggering the work queue here is just an insurance
469 * policy in case the syscall exit notify handler
470 * doesn't run soon enough or ends up running on the
471 * wrong CPU (can happen when audit sleeps)
472 */
473 mce_schedule_work();
474 return;
475 }
476
477 irq_work_queue(&mce_irq_work);
478}
479
480/*
481 * Check if the address reported by the CPU is in a format we can parse.
482 * It would be possible to add code for most other cases, but all would
483 * be somewhat complicated (e.g. segment offset would require an instruction
484 * parser). So only support physical addresses up to page granuality for now.
485 */
486int mce_usable_address(struct mce *m)
487{
488 if (!(m->status & MCI_STATUS_ADDRV))
489 return 0;
490
491 /* Checks after this one are Intel-specific: */
492 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
493 return 1;
494
495 if (!(m->status & MCI_STATUS_MISCV))
496 return 0;
497
498 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
499 return 0;
500
501 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
502 return 0;
503
504 return 1;
505}
506EXPORT_SYMBOL_GPL(mce_usable_address);
507
508bool mce_is_memory_error(struct mce *m)
509{
510 if (m->cpuvendor == X86_VENDOR_AMD ||
511 m->cpuvendor == X86_VENDOR_HYGON) {
512 return amd_mce_is_memory_error(m);
513 } else if (m->cpuvendor == X86_VENDOR_INTEL) {
514 /*
515 * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
516 *
517 * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for
518 * indicating a memory error. Bit 8 is used for indicating a
519 * cache hierarchy error. The combination of bit 2 and bit 3
520 * is used for indicating a `generic' cache hierarchy error
521 * But we can't just blindly check the above bits, because if
522 * bit 11 is set, then it is a bus/interconnect error - and
523 * either way the above bits just gives more detail on what
524 * bus/interconnect error happened. Note that bit 12 can be
525 * ignored, as it's the "filter" bit.
526 */
527 return (m->status & 0xef80) == BIT(7) ||
528 (m->status & 0xef00) == BIT(8) ||
529 (m->status & 0xeffc) == 0xc;
530 }
531
532 return false;
533}
534EXPORT_SYMBOL_GPL(mce_is_memory_error);
535
536bool mce_is_correctable(struct mce *m)
537{
538 if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED)
539 return false;
540
541 if (m->cpuvendor == X86_VENDOR_HYGON && m->status & MCI_STATUS_DEFERRED)
542 return false;
543
544 if (m->status & MCI_STATUS_UC)
545 return false;
546
547 return true;
548}
549EXPORT_SYMBOL_GPL(mce_is_correctable);
550
551static bool cec_add_mce(struct mce *m)
552{
553 if (!m)
554 return false;
555
556 /* We eat only correctable DRAM errors with usable addresses. */
557 if (mce_is_memory_error(m) &&
558 mce_is_correctable(m) &&
559 mce_usable_address(m))
560 if (!cec_add_elem(m->addr >> PAGE_SHIFT))
561 return true;
562
563 return false;
564}
565
566static int mce_first_notifier(struct notifier_block *nb, unsigned long val,
567 void *data)
568{
569 struct mce *m = (struct mce *)data;
570
571 if (!m)
572 return NOTIFY_DONE;
573
574 if (cec_add_mce(m))
575 return NOTIFY_STOP;
576
577 /* Emit the trace record: */
578 trace_mce_record(m);
579
580 set_bit(0, &mce_need_notify);
581
582 mce_notify_irq();
583
584 return NOTIFY_DONE;
585}
586
587static struct notifier_block first_nb = {
588 .notifier_call = mce_first_notifier,
589 .priority = MCE_PRIO_FIRST,
590};
591
592static int srao_decode_notifier(struct notifier_block *nb, unsigned long val,
593 void *data)
594{
595 struct mce *mce = (struct mce *)data;
596 unsigned long pfn;
597
598 if (!mce)
599 return NOTIFY_DONE;
600
601 if (mce_usable_address(mce) && (mce->severity == MCE_AO_SEVERITY)) {
602 pfn = mce->addr >> PAGE_SHIFT;
603 if (!memory_failure(pfn, 0))
604 set_mce_nospec(pfn);
605 }
606
607 return NOTIFY_OK;
608}
609static struct notifier_block mce_srao_nb = {
610 .notifier_call = srao_decode_notifier,
611 .priority = MCE_PRIO_SRAO,
612};
613
614static int mce_default_notifier(struct notifier_block *nb, unsigned long val,
615 void *data)
616{
617 struct mce *m = (struct mce *)data;
618
619 if (!m)
620 return NOTIFY_DONE;
621
622 if (atomic_read(&num_notifiers) > NUM_DEFAULT_NOTIFIERS)
623 return NOTIFY_DONE;
624
625 __print_mce(m);
626
627 return NOTIFY_DONE;
628}
629
630static struct notifier_block mce_default_nb = {
631 .notifier_call = mce_default_notifier,
632 /* lowest prio, we want it to run last. */
633 .priority = MCE_PRIO_LOWEST,
634};
635
636/*
637 * Read ADDR and MISC registers.
638 */
639static void mce_read_aux(struct mce *m, int i)
640{
641 if (m->status & MCI_STATUS_MISCV)
642 m->misc = mce_rdmsrl(msr_ops.misc(i));
643
644 if (m->status & MCI_STATUS_ADDRV) {
645 m->addr = mce_rdmsrl(msr_ops.addr(i));
646
647 /*
648 * Mask the reported address by the reported granularity.
649 */
650 if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) {
651 u8 shift = MCI_MISC_ADDR_LSB(m->misc);
652 m->addr >>= shift;
653 m->addr <<= shift;
654 }
655
656 /*
657 * Extract [55:<lsb>] where lsb is the least significant
658 * *valid* bit of the address bits.
659 */
660 if (mce_flags.smca) {
661 u8 lsb = (m->addr >> 56) & 0x3f;
662
663 m->addr &= GENMASK_ULL(55, lsb);
664 }
665 }
666
667 if (mce_flags.smca) {
668 m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i));
669
670 if (m->status & MCI_STATUS_SYNDV)
671 m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i));
672 }
673}
674
675DEFINE_PER_CPU(unsigned, mce_poll_count);
676
677/*
678 * Poll for corrected events or events that happened before reset.
679 * Those are just logged through /dev/mcelog.
680 *
681 * This is executed in standard interrupt context.
682 *
683 * Note: spec recommends to panic for fatal unsignalled
684 * errors here. However this would be quite problematic --
685 * we would need to reimplement the Monarch handling and
686 * it would mess up the exclusion between exception handler
687 * and poll handler -- * so we skip this for now.
688 * These cases should not happen anyways, or only when the CPU
689 * is already totally * confused. In this case it's likely it will
690 * not fully execute the machine check handler either.
691 */
692bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
693{
694 bool error_seen = false;
695 struct mce m;
696 int i;
697
698 this_cpu_inc(mce_poll_count);
699
700 mce_gather_info(&m, NULL);
701
702 if (flags & MCP_TIMESTAMP)
703 m.tsc = rdtsc();
704
705 for (i = 0; i < mca_cfg.banks; i++) {
706 if (!mce_banks[i].ctl || !test_bit(i, *b))
707 continue;
708
709 m.misc = 0;
710 m.addr = 0;
711 m.bank = i;
712
713 barrier();
714 m.status = mce_rdmsrl(msr_ops.status(i));
715 if (!(m.status & MCI_STATUS_VAL))
716 continue;
717
718 /*
719 * Uncorrected or signalled events are handled by the exception
720 * handler when it is enabled, so don't process those here.
721 *
722 * TBD do the same check for MCI_STATUS_EN here?
723 */
724 if (!(flags & MCP_UC) &&
725 (m.status & (mca_cfg.ser ? MCI_STATUS_S : MCI_STATUS_UC)))
726 continue;
727
728 error_seen = true;
729
730 mce_read_aux(&m, i);
731
732 m.severity = mce_severity(&m, mca_cfg.tolerant, NULL, false);
733
734 /*
735 * Don't get the IP here because it's unlikely to
736 * have anything to do with the actual error location.
737 */
738 if (!(flags & MCP_DONTLOG) && !mca_cfg.dont_log_ce)
739 mce_log(&m);
740 else if (mce_usable_address(&m)) {
741 /*
742 * Although we skipped logging this, we still want
743 * to take action. Add to the pool so the registered
744 * notifiers will see it.
745 */
746 if (!mce_gen_pool_add(&m))
747 mce_schedule_work();
748 }
749
750 /*
751 * Clear state for this bank.
752 */
753 mce_wrmsrl(msr_ops.status(i), 0);
754 }
755
756 /*
757 * Don't clear MCG_STATUS here because it's only defined for
758 * exceptions.
759 */
760
761 sync_core();
762
763 return error_seen;
764}
765EXPORT_SYMBOL_GPL(machine_check_poll);
766
767/*
768 * Do a quick check if any of the events requires a panic.
769 * This decides if we keep the events around or clear them.
770 */
771static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
772 struct pt_regs *regs)
773{
774 char *tmp;
775 int i;
776
777 for (i = 0; i < mca_cfg.banks; i++) {
778 m->status = mce_rdmsrl(msr_ops.status(i));
779 if (!(m->status & MCI_STATUS_VAL))
780 continue;
781
782 __set_bit(i, validp);
783 if (quirk_no_way_out)
784 quirk_no_way_out(i, m, regs);
785
786 if (mce_severity(m, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) {
787 m->bank = i;
788 mce_read_aux(m, i);
789 *msg = tmp;
790 return 1;
791 }
792 }
793 return 0;
794}
795
796/*
797 * Variable to establish order between CPUs while scanning.
798 * Each CPU spins initially until executing is equal its number.
799 */
800static atomic_t mce_executing;
801
802/*
803 * Defines order of CPUs on entry. First CPU becomes Monarch.
804 */
805static atomic_t mce_callin;
806
807/*
808 * Check if a timeout waiting for other CPUs happened.
809 */
810static int mce_timed_out(u64 *t, const char *msg)
811{
812 /*
813 * The others already did panic for some reason.
814 * Bail out like in a timeout.
815 * rmb() to tell the compiler that system_state
816 * might have been modified by someone else.
817 */
818 rmb();
819 if (atomic_read(&mce_panicked))
820 wait_for_panic();
821 if (!mca_cfg.monarch_timeout)
822 goto out;
823 if ((s64)*t < SPINUNIT) {
824 if (mca_cfg.tolerant <= 1)
825 mce_panic(msg, NULL, NULL);
826 cpu_missing = 1;
827 return 1;
828 }
829 *t -= SPINUNIT;
830out:
831 touch_nmi_watchdog();
832 return 0;
833}
834
835/*
836 * The Monarch's reign. The Monarch is the CPU who entered
837 * the machine check handler first. It waits for the others to
838 * raise the exception too and then grades them. When any
839 * error is fatal panic. Only then let the others continue.
840 *
841 * The other CPUs entering the MCE handler will be controlled by the
842 * Monarch. They are called Subjects.
843 *
844 * This way we prevent any potential data corruption in a unrecoverable case
845 * and also makes sure always all CPU's errors are examined.
846 *
847 * Also this detects the case of a machine check event coming from outer
848 * space (not detected by any CPUs) In this case some external agent wants
849 * us to shut down, so panic too.
850 *
851 * The other CPUs might still decide to panic if the handler happens
852 * in a unrecoverable place, but in this case the system is in a semi-stable
853 * state and won't corrupt anything by itself. It's ok to let the others
854 * continue for a bit first.
855 *
856 * All the spin loops have timeouts; when a timeout happens a CPU
857 * typically elects itself to be Monarch.
858 */
859static void mce_reign(void)
860{
861 int cpu;
862 struct mce *m = NULL;
863 int global_worst = 0;
864 char *msg = NULL;
865 char *nmsg = NULL;
866
867 /*
868 * This CPU is the Monarch and the other CPUs have run
869 * through their handlers.
870 * Grade the severity of the errors of all the CPUs.
871 */
872 for_each_possible_cpu(cpu) {
873 int severity = mce_severity(&per_cpu(mces_seen, cpu),
874 mca_cfg.tolerant,
875 &nmsg, true);
876 if (severity > global_worst) {
877 msg = nmsg;
878 global_worst = severity;
879 m = &per_cpu(mces_seen, cpu);
880 }
881 }
882
883 /*
884 * Cannot recover? Panic here then.
885 * This dumps all the mces in the log buffer and stops the
886 * other CPUs.
887 */
888 if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3)
889 mce_panic("Fatal machine check", m, msg);
890
891 /*
892 * For UC somewhere we let the CPU who detects it handle it.
893 * Also must let continue the others, otherwise the handling
894 * CPU could deadlock on a lock.
895 */
896
897 /*
898 * No machine check event found. Must be some external
899 * source or one CPU is hung. Panic.
900 */
901 if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3)
902 mce_panic("Fatal machine check from unknown source", NULL, NULL);
903
904 /*
905 * Now clear all the mces_seen so that they don't reappear on
906 * the next mce.
907 */
908 for_each_possible_cpu(cpu)
909 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
910}
911
912static atomic_t global_nwo;
913
914/*
915 * Start of Monarch synchronization. This waits until all CPUs have
916 * entered the exception handler and then determines if any of them
917 * saw a fatal event that requires panic. Then it executes them
918 * in the entry order.
919 * TBD double check parallel CPU hotunplug
920 */
921static int mce_start(int *no_way_out)
922{
923 int order;
924 int cpus = num_online_cpus();
925 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
926
927 if (!timeout)
928 return -1;
929
930 atomic_add(*no_way_out, &global_nwo);
931 /*
932 * Rely on the implied barrier below, such that global_nwo
933 * is updated before mce_callin.
934 */
935 order = atomic_inc_return(&mce_callin);
936
937 /*
938 * Wait for everyone.
939 */
940 while (atomic_read(&mce_callin) != cpus) {
941 if (mce_timed_out(&timeout,
942 "Timeout: Not all CPUs entered broadcast exception handler")) {
943 atomic_set(&global_nwo, 0);
944 return -1;
945 }
946 ndelay(SPINUNIT);
947 }
948
949 /*
950 * mce_callin should be read before global_nwo
951 */
952 smp_rmb();
953
954 if (order == 1) {
955 /*
956 * Monarch: Starts executing now, the others wait.
957 */
958 atomic_set(&mce_executing, 1);
959 } else {
960 /*
961 * Subject: Now start the scanning loop one by one in
962 * the original callin order.
963 * This way when there are any shared banks it will be
964 * only seen by one CPU before cleared, avoiding duplicates.
965 */
966 while (atomic_read(&mce_executing) < order) {
967 if (mce_timed_out(&timeout,
968 "Timeout: Subject CPUs unable to finish machine check processing")) {
969 atomic_set(&global_nwo, 0);
970 return -1;
971 }
972 ndelay(SPINUNIT);
973 }
974 }
975
976 /*
977 * Cache the global no_way_out state.
978 */
979 *no_way_out = atomic_read(&global_nwo);
980
981 return order;
982}
983
984/*
985 * Synchronize between CPUs after main scanning loop.
986 * This invokes the bulk of the Monarch processing.
987 */
988static int mce_end(int order)
989{
990 int ret = -1;
991 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
992
993 if (!timeout)
994 goto reset;
995 if (order < 0)
996 goto reset;
997
998 /*
999 * Allow others to run.
1000 */
1001 atomic_inc(&mce_executing);
1002
1003 if (order == 1) {
1004 /* CHECKME: Can this race with a parallel hotplug? */
1005 int cpus = num_online_cpus();
1006
1007 /*
1008 * Monarch: Wait for everyone to go through their scanning
1009 * loops.
1010 */
1011 while (atomic_read(&mce_executing) <= cpus) {
1012 if (mce_timed_out(&timeout,
1013 "Timeout: Monarch CPU unable to finish machine check processing"))
1014 goto reset;
1015 ndelay(SPINUNIT);
1016 }
1017
1018 mce_reign();
1019 barrier();
1020 ret = 0;
1021 } else {
1022 /*
1023 * Subject: Wait for Monarch to finish.
1024 */
1025 while (atomic_read(&mce_executing) != 0) {
1026 if (mce_timed_out(&timeout,
1027 "Timeout: Monarch CPU did not finish machine check processing"))
1028 goto reset;
1029 ndelay(SPINUNIT);
1030 }
1031
1032 /*
1033 * Don't reset anything. That's done by the Monarch.
1034 */
1035 return 0;
1036 }
1037
1038 /*
1039 * Reset all global state.
1040 */
1041reset:
1042 atomic_set(&global_nwo, 0);
1043 atomic_set(&mce_callin, 0);
1044 barrier();
1045
1046 /*
1047 * Let others run again.
1048 */
1049 atomic_set(&mce_executing, 0);
1050 return ret;
1051}
1052
1053static void mce_clear_state(unsigned long *toclear)
1054{
1055 int i;
1056
1057 for (i = 0; i < mca_cfg.banks; i++) {
1058 if (test_bit(i, toclear))
1059 mce_wrmsrl(msr_ops.status(i), 0);
1060 }
1061}
1062
1063static int do_memory_failure(struct mce *m)
1064{
1065 int flags = MF_ACTION_REQUIRED;
1066 int ret;
1067
1068 pr_err("Uncorrected hardware memory error in user-access at %llx", m->addr);
1069 if (!(m->mcgstatus & MCG_STATUS_RIPV))
1070 flags |= MF_MUST_KILL;
1071 ret = memory_failure(m->addr >> PAGE_SHIFT, flags);
1072 if (ret)
1073 pr_err("Memory error not recovered");
1074 else
1075 set_mce_nospec(m->addr >> PAGE_SHIFT);
1076 return ret;
1077}
1078
1079
1080/*
1081 * Cases where we avoid rendezvous handler timeout:
1082 * 1) If this CPU is offline.
1083 *
1084 * 2) If crashing_cpu was set, e.g. we're entering kdump and we need to
1085 * skip those CPUs which remain looping in the 1st kernel - see
1086 * crash_nmi_callback().
1087 *
1088 * Note: there still is a small window between kexec-ing and the new,
1089 * kdump kernel establishing a new #MC handler where a broadcasted MCE
1090 * might not get handled properly.
1091 */
1092static bool __mc_check_crashing_cpu(int cpu)
1093{
1094 if (cpu_is_offline(cpu) ||
1095 (crashing_cpu != -1 && crashing_cpu != cpu)) {
1096 u64 mcgstatus;
1097
1098 mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
1099 if (mcgstatus & MCG_STATUS_RIPV) {
1100 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1101 return true;
1102 }
1103 }
1104 return false;
1105}
1106
1107static void __mc_scan_banks(struct mce *m, struct mce *final,
1108 unsigned long *toclear, unsigned long *valid_banks,
1109 int no_way_out, int *worst)
1110{
1111 struct mca_config *cfg = &mca_cfg;
1112 int severity, i;
1113
1114 for (i = 0; i < cfg->banks; i++) {
1115 __clear_bit(i, toclear);
1116 if (!test_bit(i, valid_banks))
1117 continue;
1118
1119 if (!mce_banks[i].ctl)
1120 continue;
1121
1122 m->misc = 0;
1123 m->addr = 0;
1124 m->bank = i;
1125
1126 m->status = mce_rdmsrl(msr_ops.status(i));
1127 if (!(m->status & MCI_STATUS_VAL))
1128 continue;
1129
1130 /*
1131 * Corrected or non-signaled errors are handled by
1132 * machine_check_poll(). Leave them alone, unless this panics.
1133 */
1134 if (!(m->status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1135 !no_way_out)
1136 continue;
1137
1138 /* Set taint even when machine check was not enabled. */
1139 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
1140
1141 severity = mce_severity(m, cfg->tolerant, NULL, true);
1142
1143 /*
1144 * When machine check was for corrected/deferred handler don't
1145 * touch, unless we're panicking.
1146 */
1147 if ((severity == MCE_KEEP_SEVERITY ||
1148 severity == MCE_UCNA_SEVERITY) && !no_way_out)
1149 continue;
1150
1151 __set_bit(i, toclear);
1152
1153 /* Machine check event was not enabled. Clear, but ignore. */
1154 if (severity == MCE_NO_SEVERITY)
1155 continue;
1156
1157 mce_read_aux(m, i);
1158
1159 /* assuming valid severity level != 0 */
1160 m->severity = severity;
1161
1162 mce_log(m);
1163
1164 if (severity > *worst) {
1165 *final = *m;
1166 *worst = severity;
1167 }
1168 }
1169
1170 /* mce_clear_state will clear *final, save locally for use later */
1171 *m = *final;
1172}
1173
1174/*
1175 * The actual machine check handler. This only handles real
1176 * exceptions when something got corrupted coming in through int 18.
1177 *
1178 * This is executed in NMI context not subject to normal locking rules. This
1179 * implies that most kernel services cannot be safely used. Don't even
1180 * think about putting a printk in there!
1181 *
1182 * On Intel systems this is entered on all CPUs in parallel through
1183 * MCE broadcast. However some CPUs might be broken beyond repair,
1184 * so be always careful when synchronizing with others.
1185 */
1186void do_machine_check(struct pt_regs *regs, long error_code)
1187{
1188 DECLARE_BITMAP(valid_banks, MAX_NR_BANKS);
1189 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
1190 struct mca_config *cfg = &mca_cfg;
1191 int cpu = smp_processor_id();
1192 char *msg = "Unknown";
1193 struct mce m, *final;
1194 int worst = 0;
1195
1196 /*
1197 * Establish sequential order between the CPUs entering the machine
1198 * check handler.
1199 */
1200 int order = -1;
1201
1202 /*
1203 * If no_way_out gets set, there is no safe way to recover from this
1204 * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway.
1205 */
1206 int no_way_out = 0;
1207
1208 /*
1209 * If kill_it gets set, there might be a way to recover from this
1210 * error.
1211 */
1212 int kill_it = 0;
1213
1214 /*
1215 * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES
1216 * on Intel.
1217 */
1218 int lmce = 1;
1219
1220 if (__mc_check_crashing_cpu(cpu))
1221 return;
1222
1223 ist_enter(regs);
1224
1225 this_cpu_inc(mce_exception_count);
1226
1227 mce_gather_info(&m, regs);
1228 m.tsc = rdtsc();
1229
1230 final = this_cpu_ptr(&mces_seen);
1231 *final = m;
1232
1233 memset(valid_banks, 0, sizeof(valid_banks));
1234 no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs);
1235
1236 barrier();
1237
1238 /*
1239 * When no restart IP might need to kill or panic.
1240 * Assume the worst for now, but if we find the
1241 * severity is MCE_AR_SEVERITY we have other options.
1242 */
1243 if (!(m.mcgstatus & MCG_STATUS_RIPV))
1244 kill_it = 1;
1245
1246 /*
1247 * Check if this MCE is signaled to only this logical processor,
1248 * on Intel only.
1249 */
1250 if (m.cpuvendor == X86_VENDOR_INTEL)
1251 lmce = m.mcgstatus & MCG_STATUS_LMCES;
1252
1253 /*
1254 * Local machine check may already know that we have to panic.
1255 * Broadcast machine check begins rendezvous in mce_start()
1256 * Go through all banks in exclusion of the other CPUs. This way we
1257 * don't report duplicated events on shared banks because the first one
1258 * to see it will clear it.
1259 */
1260 if (lmce) {
1261 if (no_way_out)
1262 mce_panic("Fatal local machine check", &m, msg);
1263 } else {
1264 order = mce_start(&no_way_out);
1265 }
1266
1267 __mc_scan_banks(&m, final, toclear, valid_banks, no_way_out, &worst);
1268
1269 if (!no_way_out)
1270 mce_clear_state(toclear);
1271
1272 /*
1273 * Do most of the synchronization with other CPUs.
1274 * When there's any problem use only local no_way_out state.
1275 */
1276 if (!lmce) {
1277 if (mce_end(order) < 0)
1278 no_way_out = worst >= MCE_PANIC_SEVERITY;
1279 } else {
1280 /*
1281 * If there was a fatal machine check we should have
1282 * already called mce_panic earlier in this function.
1283 * Since we re-read the banks, we might have found
1284 * something new. Check again to see if we found a
1285 * fatal error. We call "mce_severity()" again to
1286 * make sure we have the right "msg".
1287 */
1288 if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) {
1289 mce_severity(&m, cfg->tolerant, &msg, true);
1290 mce_panic("Local fatal machine check!", &m, msg);
1291 }
1292 }
1293
1294 /*
1295 * If tolerant is at an insane level we drop requests to kill
1296 * processes and continue even when there is no way out.
1297 */
1298 if (cfg->tolerant == 3)
1299 kill_it = 0;
1300 else if (no_way_out)
1301 mce_panic("Fatal machine check on current CPU", &m, msg);
1302
1303 if (worst > 0)
1304 mce_report_event(regs);
1305 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1306
1307 sync_core();
1308
1309 if (worst != MCE_AR_SEVERITY && !kill_it)
1310 goto out_ist;
1311
1312 /* Fault was in user mode and we need to take some action */
1313 if ((m.cs & 3) == 3) {
1314 ist_begin_non_atomic(regs);
1315 local_irq_enable();
1316
1317 if (kill_it || do_memory_failure(&m))
1318 force_sig(SIGBUS, current);
1319 local_irq_disable();
1320 ist_end_non_atomic();
1321 } else {
1322 if (!fixup_exception(regs, X86_TRAP_MC, error_code, 0))
1323 mce_panic("Failed kernel mode recovery", &m, NULL);
1324 }
1325
1326out_ist:
1327 ist_exit(regs);
1328}
1329EXPORT_SYMBOL_GPL(do_machine_check);
1330
1331#ifndef CONFIG_MEMORY_FAILURE
1332int memory_failure(unsigned long pfn, int flags)
1333{
1334 /* mce_severity() should not hand us an ACTION_REQUIRED error */
1335 BUG_ON(flags & MF_ACTION_REQUIRED);
1336 pr_err("Uncorrected memory error in page 0x%lx ignored\n"
1337 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n",
1338 pfn);
1339
1340 return 0;
1341}
1342#endif
1343
1344/*
1345 * Periodic polling timer for "silent" machine check errors. If the
1346 * poller finds an MCE, poll 2x faster. When the poller finds no more
1347 * errors, poll 2x slower (up to check_interval seconds).
1348 */
1349static unsigned long check_interval = INITIAL_CHECK_INTERVAL;
1350
1351static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */
1352static DEFINE_PER_CPU(struct timer_list, mce_timer);
1353
1354static unsigned long mce_adjust_timer_default(unsigned long interval)
1355{
1356 return interval;
1357}
1358
1359static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default;
1360
1361static void __start_timer(struct timer_list *t, unsigned long interval)
1362{
1363 unsigned long when = jiffies + interval;
1364 unsigned long flags;
1365
1366 local_irq_save(flags);
1367
1368 if (!timer_pending(t) || time_before(when, t->expires))
1369 mod_timer(t, round_jiffies(when));
1370
1371 local_irq_restore(flags);
1372}
1373
1374static void mce_timer_fn(struct timer_list *t)
1375{
1376 struct timer_list *cpu_t = this_cpu_ptr(&mce_timer);
1377 unsigned long iv;
1378
1379 WARN_ON(cpu_t != t);
1380
1381 iv = __this_cpu_read(mce_next_interval);
1382
1383 if (mce_available(this_cpu_ptr(&cpu_info))) {
1384 machine_check_poll(0, this_cpu_ptr(&mce_poll_banks));
1385
1386 if (mce_intel_cmci_poll()) {
1387 iv = mce_adjust_timer(iv);
1388 goto done;
1389 }
1390 }
1391
1392 /*
1393 * Alert userspace if needed. If we logged an MCE, reduce the polling
1394 * interval, otherwise increase the polling interval.
1395 */
1396 if (mce_notify_irq())
1397 iv = max(iv / 2, (unsigned long) HZ/100);
1398 else
1399 iv = min(iv * 2, round_jiffies_relative(check_interval * HZ));
1400
1401done:
1402 __this_cpu_write(mce_next_interval, iv);
1403 __start_timer(t, iv);
1404}
1405
1406/*
1407 * Ensure that the timer is firing in @interval from now.
1408 */
1409void mce_timer_kick(unsigned long interval)
1410{
1411 struct timer_list *t = this_cpu_ptr(&mce_timer);
1412 unsigned long iv = __this_cpu_read(mce_next_interval);
1413
1414 __start_timer(t, interval);
1415
1416 if (interval < iv)
1417 __this_cpu_write(mce_next_interval, interval);
1418}
1419
1420/* Must not be called in IRQ context where del_timer_sync() can deadlock */
1421static void mce_timer_delete_all(void)
1422{
1423 int cpu;
1424
1425 for_each_online_cpu(cpu)
1426 del_timer_sync(&per_cpu(mce_timer, cpu));
1427}
1428
1429/*
1430 * Notify the user(s) about new machine check events.
1431 * Can be called from interrupt context, but not from machine check/NMI
1432 * context.
1433 */
1434int mce_notify_irq(void)
1435{
1436 /* Not more than two messages every minute */
1437 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1438
1439 if (test_and_clear_bit(0, &mce_need_notify)) {
1440 mce_work_trigger();
1441
1442 if (__ratelimit(&ratelimit))
1443 pr_info(HW_ERR "Machine check events logged\n");
1444
1445 return 1;
1446 }
1447 return 0;
1448}
1449EXPORT_SYMBOL_GPL(mce_notify_irq);
1450
1451static int __mcheck_cpu_mce_banks_init(void)
1452{
1453 int i;
1454 u8 num_banks = mca_cfg.banks;
1455
1456 mce_banks = kcalloc(num_banks, sizeof(struct mce_bank), GFP_KERNEL);
1457 if (!mce_banks)
1458 return -ENOMEM;
1459
1460 for (i = 0; i < num_banks; i++) {
1461 struct mce_bank *b = &mce_banks[i];
1462
1463 b->ctl = -1ULL;
1464 b->init = 1;
1465 }
1466 return 0;
1467}
1468
1469/*
1470 * Initialize Machine Checks for a CPU.
1471 */
1472static int __mcheck_cpu_cap_init(void)
1473{
1474 unsigned b;
1475 u64 cap;
1476
1477 rdmsrl(MSR_IA32_MCG_CAP, cap);
1478
1479 b = cap & MCG_BANKCNT_MASK;
1480 if (!mca_cfg.banks)
1481 pr_info("CPU supports %d MCE banks\n", b);
1482
1483 if (b > MAX_NR_BANKS) {
1484 pr_warn("Using only %u machine check banks out of %u\n",
1485 MAX_NR_BANKS, b);
1486 b = MAX_NR_BANKS;
1487 }
1488
1489 /* Don't support asymmetric configurations today */
1490 WARN_ON(mca_cfg.banks != 0 && b != mca_cfg.banks);
1491 mca_cfg.banks = b;
1492
1493 if (!mce_banks) {
1494 int err = __mcheck_cpu_mce_banks_init();
1495
1496 if (err)
1497 return err;
1498 }
1499
1500 /* Use accurate RIP reporting if available. */
1501 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1502 mca_cfg.rip_msr = MSR_IA32_MCG_EIP;
1503
1504 if (cap & MCG_SER_P)
1505 mca_cfg.ser = 1;
1506
1507 return 0;
1508}
1509
1510static void __mcheck_cpu_init_generic(void)
1511{
1512 enum mcp_flags m_fl = 0;
1513 mce_banks_t all_banks;
1514 u64 cap;
1515
1516 if (!mca_cfg.bootlog)
1517 m_fl = MCP_DONTLOG;
1518
1519 /*
1520 * Log the machine checks left over from the previous reset.
1521 */
1522 bitmap_fill(all_banks, MAX_NR_BANKS);
1523 machine_check_poll(MCP_UC | m_fl, &all_banks);
1524
1525 cr4_set_bits(X86_CR4_MCE);
1526
1527 rdmsrl(MSR_IA32_MCG_CAP, cap);
1528 if (cap & MCG_CTL_P)
1529 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1530}
1531
1532static void __mcheck_cpu_init_clear_banks(void)
1533{
1534 int i;
1535
1536 for (i = 0; i < mca_cfg.banks; i++) {
1537 struct mce_bank *b = &mce_banks[i];
1538
1539 if (!b->init)
1540 continue;
1541 wrmsrl(msr_ops.ctl(i), b->ctl);
1542 wrmsrl(msr_ops.status(i), 0);
1543 }
1544}
1545
1546/*
1547 * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and
1548 * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM
1549 * Vol 3B Table 15-20). But this confuses both the code that determines
1550 * whether the machine check occurred in kernel or user mode, and also
1551 * the severity assessment code. Pretend that EIPV was set, and take the
1552 * ip/cs values from the pt_regs that mce_gather_info() ignored earlier.
1553 */
1554static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs)
1555{
1556 if (bank != 0)
1557 return;
1558 if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0)
1559 return;
1560 if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC|
1561 MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV|
1562 MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR|
1563 MCACOD)) !=
1564 (MCI_STATUS_UC|MCI_STATUS_EN|
1565 MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S|
1566 MCI_STATUS_AR|MCACOD_INSTR))
1567 return;
1568
1569 m->mcgstatus |= MCG_STATUS_EIPV;
1570 m->ip = regs->ip;
1571 m->cs = regs->cs;
1572}
1573
1574/* Add per CPU specific workarounds here */
1575static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1576{
1577 struct mca_config *cfg = &mca_cfg;
1578
1579 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1580 pr_info("unknown CPU type - not enabling MCE support\n");
1581 return -EOPNOTSUPP;
1582 }
1583
1584 /* This should be disabled by the BIOS, but isn't always */
1585 if (c->x86_vendor == X86_VENDOR_AMD) {
1586 if (c->x86 == 15 && cfg->banks > 4) {
1587 /*
1588 * disable GART TBL walk error reporting, which
1589 * trips off incorrectly with the IOMMU & 3ware
1590 * & Cerberus:
1591 */
1592 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1593 }
1594 if (c->x86 < 0x11 && cfg->bootlog < 0) {
1595 /*
1596 * Lots of broken BIOS around that don't clear them
1597 * by default and leave crap in there. Don't log:
1598 */
1599 cfg->bootlog = 0;
1600 }
1601 /*
1602 * Various K7s with broken bank 0 around. Always disable
1603 * by default.
1604 */
1605 if (c->x86 == 6 && cfg->banks > 0)
1606 mce_banks[0].ctl = 0;
1607
1608 /*
1609 * overflow_recov is supported for F15h Models 00h-0fh
1610 * even though we don't have a CPUID bit for it.
1611 */
1612 if (c->x86 == 0x15 && c->x86_model <= 0xf)
1613 mce_flags.overflow_recov = 1;
1614
1615 }
1616
1617 if (c->x86_vendor == X86_VENDOR_INTEL) {
1618 /*
1619 * SDM documents that on family 6 bank 0 should not be written
1620 * because it aliases to another special BIOS controlled
1621 * register.
1622 * But it's not aliased anymore on model 0x1a+
1623 * Don't ignore bank 0 completely because there could be a
1624 * valid event later, merely don't write CTL0.
1625 */
1626
1627 if (c->x86 == 6 && c->x86_model < 0x1A && cfg->banks > 0)
1628 mce_banks[0].init = 0;
1629
1630 /*
1631 * All newer Intel systems support MCE broadcasting. Enable
1632 * synchronization with a one second timeout.
1633 */
1634 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1635 cfg->monarch_timeout < 0)
1636 cfg->monarch_timeout = USEC_PER_SEC;
1637
1638 /*
1639 * There are also broken BIOSes on some Pentium M and
1640 * earlier systems:
1641 */
1642 if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0)
1643 cfg->bootlog = 0;
1644
1645 if (c->x86 == 6 && c->x86_model == 45)
1646 quirk_no_way_out = quirk_sandybridge_ifu;
1647 }
1648 if (cfg->monarch_timeout < 0)
1649 cfg->monarch_timeout = 0;
1650 if (cfg->bootlog != 0)
1651 cfg->panic_timeout = 30;
1652
1653 return 0;
1654}
1655
1656static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1657{
1658 if (c->x86 != 5)
1659 return 0;
1660
1661 switch (c->x86_vendor) {
1662 case X86_VENDOR_INTEL:
1663 intel_p5_mcheck_init(c);
1664 return 1;
1665 break;
1666 case X86_VENDOR_CENTAUR:
1667 winchip_mcheck_init(c);
1668 return 1;
1669 break;
1670 default:
1671 return 0;
1672 }
1673
1674 return 0;
1675}
1676
1677/*
1678 * Init basic CPU features needed for early decoding of MCEs.
1679 */
1680static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c)
1681{
1682 if (c->x86_vendor == X86_VENDOR_AMD || c->x86_vendor == X86_VENDOR_HYGON) {
1683 mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV);
1684 mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR);
1685 mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA);
1686
1687 if (mce_flags.smca) {
1688 msr_ops.ctl = smca_ctl_reg;
1689 msr_ops.status = smca_status_reg;
1690 msr_ops.addr = smca_addr_reg;
1691 msr_ops.misc = smca_misc_reg;
1692 }
1693 }
1694}
1695
1696static void mce_centaur_feature_init(struct cpuinfo_x86 *c)
1697{
1698 struct mca_config *cfg = &mca_cfg;
1699
1700 /*
1701 * All newer Centaur CPUs support MCE broadcasting. Enable
1702 * synchronization with a one second timeout.
1703 */
1704 if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) ||
1705 c->x86 > 6) {
1706 if (cfg->monarch_timeout < 0)
1707 cfg->monarch_timeout = USEC_PER_SEC;
1708 }
1709}
1710
1711static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1712{
1713 switch (c->x86_vendor) {
1714 case X86_VENDOR_INTEL:
1715 mce_intel_feature_init(c);
1716 mce_adjust_timer = cmci_intel_adjust_timer;
1717 break;
1718
1719 case X86_VENDOR_AMD: {
1720 mce_amd_feature_init(c);
1721 break;
1722 }
1723
1724 case X86_VENDOR_HYGON:
1725 mce_hygon_feature_init(c);
1726 break;
1727
1728 case X86_VENDOR_CENTAUR:
1729 mce_centaur_feature_init(c);
1730 break;
1731
1732 default:
1733 break;
1734 }
1735}
1736
1737static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c)
1738{
1739 switch (c->x86_vendor) {
1740 case X86_VENDOR_INTEL:
1741 mce_intel_feature_clear(c);
1742 break;
1743 default:
1744 break;
1745 }
1746}
1747
1748static void mce_start_timer(struct timer_list *t)
1749{
1750 unsigned long iv = check_interval * HZ;
1751
1752 if (mca_cfg.ignore_ce || !iv)
1753 return;
1754
1755 this_cpu_write(mce_next_interval, iv);
1756 __start_timer(t, iv);
1757}
1758
1759static void __mcheck_cpu_setup_timer(void)
1760{
1761 struct timer_list *t = this_cpu_ptr(&mce_timer);
1762
1763 timer_setup(t, mce_timer_fn, TIMER_PINNED);
1764}
1765
1766static void __mcheck_cpu_init_timer(void)
1767{
1768 struct timer_list *t = this_cpu_ptr(&mce_timer);
1769
1770 timer_setup(t, mce_timer_fn, TIMER_PINNED);
1771 mce_start_timer(t);
1772}
1773
1774/* Handle unconfigured int18 (should never happen) */
1775static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1776{
1777 pr_err("CPU#%d: Unexpected int18 (Machine Check)\n",
1778 smp_processor_id());
1779}
1780
1781/* Call the installed machine check handler for this CPU setup. */
1782void (*machine_check_vector)(struct pt_regs *, long error_code) =
1783 unexpected_machine_check;
1784
1785dotraplinkage void do_mce(struct pt_regs *regs, long error_code)
1786{
1787 machine_check_vector(regs, error_code);
1788}
1789
1790/*
1791 * Called for each booted CPU to set up machine checks.
1792 * Must be called with preempt off:
1793 */
1794void mcheck_cpu_init(struct cpuinfo_x86 *c)
1795{
1796 if (mca_cfg.disabled)
1797 return;
1798
1799 if (__mcheck_cpu_ancient_init(c))
1800 return;
1801
1802 if (!mce_available(c))
1803 return;
1804
1805 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1806 mca_cfg.disabled = 1;
1807 return;
1808 }
1809
1810 if (mce_gen_pool_init()) {
1811 mca_cfg.disabled = 1;
1812 pr_emerg("Couldn't allocate MCE records pool!\n");
1813 return;
1814 }
1815
1816 machine_check_vector = do_machine_check;
1817
1818 __mcheck_cpu_init_early(c);
1819 __mcheck_cpu_init_generic();
1820 __mcheck_cpu_init_vendor(c);
1821 __mcheck_cpu_init_clear_banks();
1822 __mcheck_cpu_setup_timer();
1823}
1824
1825/*
1826 * Called for each booted CPU to clear some machine checks opt-ins
1827 */
1828void mcheck_cpu_clear(struct cpuinfo_x86 *c)
1829{
1830 if (mca_cfg.disabled)
1831 return;
1832
1833 if (!mce_available(c))
1834 return;
1835
1836 /*
1837 * Possibly to clear general settings generic to x86
1838 * __mcheck_cpu_clear_generic(c);
1839 */
1840 __mcheck_cpu_clear_vendor(c);
1841
1842}
1843
1844static void __mce_disable_bank(void *arg)
1845{
1846 int bank = *((int *)arg);
1847 __clear_bit(bank, this_cpu_ptr(mce_poll_banks));
1848 cmci_disable_bank(bank);
1849}
1850
1851void mce_disable_bank(int bank)
1852{
1853 if (bank >= mca_cfg.banks) {
1854 pr_warn(FW_BUG
1855 "Ignoring request to disable invalid MCA bank %d.\n",
1856 bank);
1857 return;
1858 }
1859 set_bit(bank, mce_banks_ce_disabled);
1860 on_each_cpu(__mce_disable_bank, &bank, 1);
1861}
1862
1863/*
1864 * mce=off Disables machine check
1865 * mce=no_cmci Disables CMCI
1866 * mce=no_lmce Disables LMCE
1867 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1868 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1869 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1870 * monarchtimeout is how long to wait for other CPUs on machine
1871 * check, or 0 to not wait
1872 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD Fam10h
1873 and older.
1874 * mce=nobootlog Don't log MCEs from before booting.
1875 * mce=bios_cmci_threshold Don't program the CMCI threshold
1876 * mce=recovery force enable memcpy_mcsafe()
1877 */
1878static int __init mcheck_enable(char *str)
1879{
1880 struct mca_config *cfg = &mca_cfg;
1881
1882 if (*str == 0) {
1883 enable_p5_mce();
1884 return 1;
1885 }
1886 if (*str == '=')
1887 str++;
1888 if (!strcmp(str, "off"))
1889 cfg->disabled = 1;
1890 else if (!strcmp(str, "no_cmci"))
1891 cfg->cmci_disabled = true;
1892 else if (!strcmp(str, "no_lmce"))
1893 cfg->lmce_disabled = 1;
1894 else if (!strcmp(str, "dont_log_ce"))
1895 cfg->dont_log_ce = true;
1896 else if (!strcmp(str, "ignore_ce"))
1897 cfg->ignore_ce = true;
1898 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1899 cfg->bootlog = (str[0] == 'b');
1900 else if (!strcmp(str, "bios_cmci_threshold"))
1901 cfg->bios_cmci_threshold = 1;
1902 else if (!strcmp(str, "recovery"))
1903 cfg->recovery = 1;
1904 else if (isdigit(str[0])) {
1905 if (get_option(&str, &cfg->tolerant) == 2)
1906 get_option(&str, &(cfg->monarch_timeout));
1907 } else {
1908 pr_info("mce argument %s ignored. Please use /sys\n", str);
1909 return 0;
1910 }
1911 return 1;
1912}
1913__setup("mce", mcheck_enable);
1914
1915int __init mcheck_init(void)
1916{
1917 mcheck_intel_therm_init();
1918 mce_register_decode_chain(&first_nb);
1919 mce_register_decode_chain(&mce_srao_nb);
1920 mce_register_decode_chain(&mce_default_nb);
1921 mcheck_vendor_init_severity();
1922
1923 INIT_WORK(&mce_work, mce_gen_pool_process);
1924 init_irq_work(&mce_irq_work, mce_irq_work_cb);
1925
1926 return 0;
1927}
1928
1929/*
1930 * mce_syscore: PM support
1931 */
1932
1933/*
1934 * Disable machine checks on suspend and shutdown. We can't really handle
1935 * them later.
1936 */
1937static void mce_disable_error_reporting(void)
1938{
1939 int i;
1940
1941 for (i = 0; i < mca_cfg.banks; i++) {
1942 struct mce_bank *b = &mce_banks[i];
1943
1944 if (b->init)
1945 wrmsrl(msr_ops.ctl(i), 0);
1946 }
1947 return;
1948}
1949
1950static void vendor_disable_error_reporting(void)
1951{
1952 /*
1953 * Don't clear on Intel or AMD or Hygon CPUs. Some of these MSRs
1954 * are socket-wide.
1955 * Disabling them for just a single offlined CPU is bad, since it will
1956 * inhibit reporting for all shared resources on the socket like the
1957 * last level cache (LLC), the integrated memory controller (iMC), etc.
1958 */
1959 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
1960 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ||
1961 boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1962 return;
1963
1964 mce_disable_error_reporting();
1965}
1966
1967static int mce_syscore_suspend(void)
1968{
1969 vendor_disable_error_reporting();
1970 return 0;
1971}
1972
1973static void mce_syscore_shutdown(void)
1974{
1975 vendor_disable_error_reporting();
1976}
1977
1978/*
1979 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1980 * Only one CPU is active at this time, the others get re-added later using
1981 * CPU hotplug:
1982 */
1983static void mce_syscore_resume(void)
1984{
1985 __mcheck_cpu_init_generic();
1986 __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info));
1987 __mcheck_cpu_init_clear_banks();
1988}
1989
1990static struct syscore_ops mce_syscore_ops = {
1991 .suspend = mce_syscore_suspend,
1992 .shutdown = mce_syscore_shutdown,
1993 .resume = mce_syscore_resume,
1994};
1995
1996/*
1997 * mce_device: Sysfs support
1998 */
1999
2000static void mce_cpu_restart(void *data)
2001{
2002 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2003 return;
2004 __mcheck_cpu_init_generic();
2005 __mcheck_cpu_init_clear_banks();
2006 __mcheck_cpu_init_timer();
2007}
2008
2009/* Reinit MCEs after user configuration changes */
2010static void mce_restart(void)
2011{
2012 mce_timer_delete_all();
2013 on_each_cpu(mce_cpu_restart, NULL, 1);
2014}
2015
2016/* Toggle features for corrected errors */
2017static void mce_disable_cmci(void *data)
2018{
2019 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2020 return;
2021 cmci_clear();
2022}
2023
2024static void mce_enable_ce(void *all)
2025{
2026 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2027 return;
2028 cmci_reenable();
2029 cmci_recheck();
2030 if (all)
2031 __mcheck_cpu_init_timer();
2032}
2033
2034static struct bus_type mce_subsys = {
2035 .name = "machinecheck",
2036 .dev_name = "machinecheck",
2037};
2038
2039DEFINE_PER_CPU(struct device *, mce_device);
2040
2041static inline struct mce_bank *attr_to_bank(struct device_attribute *attr)
2042{
2043 return container_of(attr, struct mce_bank, attr);
2044}
2045
2046static ssize_t show_bank(struct device *s, struct device_attribute *attr,
2047 char *buf)
2048{
2049 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
2050}
2051
2052static ssize_t set_bank(struct device *s, struct device_attribute *attr,
2053 const char *buf, size_t size)
2054{
2055 u64 new;
2056
2057 if (kstrtou64(buf, 0, &new) < 0)
2058 return -EINVAL;
2059
2060 attr_to_bank(attr)->ctl = new;
2061 mce_restart();
2062
2063 return size;
2064}
2065
2066static ssize_t set_ignore_ce(struct device *s,
2067 struct device_attribute *attr,
2068 const char *buf, size_t size)
2069{
2070 u64 new;
2071
2072 if (kstrtou64(buf, 0, &new) < 0)
2073 return -EINVAL;
2074
2075 mutex_lock(&mce_sysfs_mutex);
2076 if (mca_cfg.ignore_ce ^ !!new) {
2077 if (new) {
2078 /* disable ce features */
2079 mce_timer_delete_all();
2080 on_each_cpu(mce_disable_cmci, NULL, 1);
2081 mca_cfg.ignore_ce = true;
2082 } else {
2083 /* enable ce features */
2084 mca_cfg.ignore_ce = false;
2085 on_each_cpu(mce_enable_ce, (void *)1, 1);
2086 }
2087 }
2088 mutex_unlock(&mce_sysfs_mutex);
2089
2090 return size;
2091}
2092
2093static ssize_t set_cmci_disabled(struct device *s,
2094 struct device_attribute *attr,
2095 const char *buf, size_t size)
2096{
2097 u64 new;
2098
2099 if (kstrtou64(buf, 0, &new) < 0)
2100 return -EINVAL;
2101
2102 mutex_lock(&mce_sysfs_mutex);
2103 if (mca_cfg.cmci_disabled ^ !!new) {
2104 if (new) {
2105 /* disable cmci */
2106 on_each_cpu(mce_disable_cmci, NULL, 1);
2107 mca_cfg.cmci_disabled = true;
2108 } else {
2109 /* enable cmci */
2110 mca_cfg.cmci_disabled = false;
2111 on_each_cpu(mce_enable_ce, NULL, 1);
2112 }
2113 }
2114 mutex_unlock(&mce_sysfs_mutex);
2115
2116 return size;
2117}
2118
2119static ssize_t store_int_with_restart(struct device *s,
2120 struct device_attribute *attr,
2121 const char *buf, size_t size)
2122{
2123 unsigned long old_check_interval = check_interval;
2124 ssize_t ret = device_store_ulong(s, attr, buf, size);
2125
2126 if (check_interval == old_check_interval)
2127 return ret;
2128
2129 mutex_lock(&mce_sysfs_mutex);
2130 mce_restart();
2131 mutex_unlock(&mce_sysfs_mutex);
2132
2133 return ret;
2134}
2135
2136static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant);
2137static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout);
2138static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce);
2139
2140static struct dev_ext_attribute dev_attr_check_interval = {
2141 __ATTR(check_interval, 0644, device_show_int, store_int_with_restart),
2142 &check_interval
2143};
2144
2145static struct dev_ext_attribute dev_attr_ignore_ce = {
2146 __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce),
2147 &mca_cfg.ignore_ce
2148};
2149
2150static struct dev_ext_attribute dev_attr_cmci_disabled = {
2151 __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled),
2152 &mca_cfg.cmci_disabled
2153};
2154
2155static struct device_attribute *mce_device_attrs[] = {
2156 &dev_attr_tolerant.attr,
2157 &dev_attr_check_interval.attr,
2158#ifdef CONFIG_X86_MCELOG_LEGACY
2159 &dev_attr_trigger,
2160#endif
2161 &dev_attr_monarch_timeout.attr,
2162 &dev_attr_dont_log_ce.attr,
2163 &dev_attr_ignore_ce.attr,
2164 &dev_attr_cmci_disabled.attr,
2165 NULL
2166};
2167
2168static cpumask_var_t mce_device_initialized;
2169
2170static void mce_device_release(struct device *dev)
2171{
2172 kfree(dev);
2173}
2174
2175/* Per cpu device init. All of the cpus still share the same ctrl bank: */
2176static int mce_device_create(unsigned int cpu)
2177{
2178 struct device *dev;
2179 int err;
2180 int i, j;
2181
2182 if (!mce_available(&boot_cpu_data))
2183 return -EIO;
2184
2185 dev = per_cpu(mce_device, cpu);
2186 if (dev)
2187 return 0;
2188
2189 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2190 if (!dev)
2191 return -ENOMEM;
2192 dev->id = cpu;
2193 dev->bus = &mce_subsys;
2194 dev->release = &mce_device_release;
2195
2196 err = device_register(dev);
2197 if (err) {
2198 put_device(dev);
2199 return err;
2200 }
2201
2202 for (i = 0; mce_device_attrs[i]; i++) {
2203 err = device_create_file(dev, mce_device_attrs[i]);
2204 if (err)
2205 goto error;
2206 }
2207 for (j = 0; j < mca_cfg.banks; j++) {
2208 err = device_create_file(dev, &mce_banks[j].attr);
2209 if (err)
2210 goto error2;
2211 }
2212 cpumask_set_cpu(cpu, mce_device_initialized);
2213 per_cpu(mce_device, cpu) = dev;
2214
2215 return 0;
2216error2:
2217 while (--j >= 0)
2218 device_remove_file(dev, &mce_banks[j].attr);
2219error:
2220 while (--i >= 0)
2221 device_remove_file(dev, mce_device_attrs[i]);
2222
2223 device_unregister(dev);
2224
2225 return err;
2226}
2227
2228static void mce_device_remove(unsigned int cpu)
2229{
2230 struct device *dev = per_cpu(mce_device, cpu);
2231 int i;
2232
2233 if (!cpumask_test_cpu(cpu, mce_device_initialized))
2234 return;
2235
2236 for (i = 0; mce_device_attrs[i]; i++)
2237 device_remove_file(dev, mce_device_attrs[i]);
2238
2239 for (i = 0; i < mca_cfg.banks; i++)
2240 device_remove_file(dev, &mce_banks[i].attr);
2241
2242 device_unregister(dev);
2243 cpumask_clear_cpu(cpu, mce_device_initialized);
2244 per_cpu(mce_device, cpu) = NULL;
2245}
2246
2247/* Make sure there are no machine checks on offlined CPUs. */
2248static void mce_disable_cpu(void)
2249{
2250 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2251 return;
2252
2253 if (!cpuhp_tasks_frozen)
2254 cmci_clear();
2255
2256 vendor_disable_error_reporting();
2257}
2258
2259static void mce_reenable_cpu(void)
2260{
2261 int i;
2262
2263 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2264 return;
2265
2266 if (!cpuhp_tasks_frozen)
2267 cmci_reenable();
2268 for (i = 0; i < mca_cfg.banks; i++) {
2269 struct mce_bank *b = &mce_banks[i];
2270
2271 if (b->init)
2272 wrmsrl(msr_ops.ctl(i), b->ctl);
2273 }
2274}
2275
2276static int mce_cpu_dead(unsigned int cpu)
2277{
2278 mce_intel_hcpu_update(cpu);
2279
2280 /* intentionally ignoring frozen here */
2281 if (!cpuhp_tasks_frozen)
2282 cmci_rediscover();
2283 return 0;
2284}
2285
2286static int mce_cpu_online(unsigned int cpu)
2287{
2288 struct timer_list *t = this_cpu_ptr(&mce_timer);
2289 int ret;
2290
2291 mce_device_create(cpu);
2292
2293 ret = mce_threshold_create_device(cpu);
2294 if (ret) {
2295 mce_device_remove(cpu);
2296 return ret;
2297 }
2298 mce_reenable_cpu();
2299 mce_start_timer(t);
2300 return 0;
2301}
2302
2303static int mce_cpu_pre_down(unsigned int cpu)
2304{
2305 struct timer_list *t = this_cpu_ptr(&mce_timer);
2306
2307 mce_disable_cpu();
2308 del_timer_sync(t);
2309 mce_threshold_remove_device(cpu);
2310 mce_device_remove(cpu);
2311 return 0;
2312}
2313
2314static __init void mce_init_banks(void)
2315{
2316 int i;
2317
2318 for (i = 0; i < mca_cfg.banks; i++) {
2319 struct mce_bank *b = &mce_banks[i];
2320 struct device_attribute *a = &b->attr;
2321
2322 sysfs_attr_init(&a->attr);
2323 a->attr.name = b->attrname;
2324 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2325
2326 a->attr.mode = 0644;
2327 a->show = show_bank;
2328 a->store = set_bank;
2329 }
2330}
2331
2332static __init int mcheck_init_device(void)
2333{
2334 int err;
2335
2336 /*
2337 * Check if we have a spare virtual bit. This will only become
2338 * a problem if/when we move beyond 5-level page tables.
2339 */
2340 MAYBE_BUILD_BUG_ON(__VIRTUAL_MASK_SHIFT >= 63);
2341
2342 if (!mce_available(&boot_cpu_data)) {
2343 err = -EIO;
2344 goto err_out;
2345 }
2346
2347 if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) {
2348 err = -ENOMEM;
2349 goto err_out;
2350 }
2351
2352 mce_init_banks();
2353
2354 err = subsys_system_register(&mce_subsys, NULL);
2355 if (err)
2356 goto err_out_mem;
2357
2358 err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL,
2359 mce_cpu_dead);
2360 if (err)
2361 goto err_out_mem;
2362
2363 err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online",
2364 mce_cpu_online, mce_cpu_pre_down);
2365 if (err < 0)
2366 goto err_out_online;
2367
2368 register_syscore_ops(&mce_syscore_ops);
2369
2370 return 0;
2371
2372err_out_online:
2373 cpuhp_remove_state(CPUHP_X86_MCE_DEAD);
2374
2375err_out_mem:
2376 free_cpumask_var(mce_device_initialized);
2377
2378err_out:
2379 pr_err("Unable to init MCE device (rc: %d)\n", err);
2380
2381 return err;
2382}
2383device_initcall_sync(mcheck_init_device);
2384
2385/*
2386 * Old style boot options parsing. Only for compatibility.
2387 */
2388static int __init mcheck_disable(char *str)
2389{
2390 mca_cfg.disabled = 1;
2391 return 1;
2392}
2393__setup("nomce", mcheck_disable);
2394
2395#ifdef CONFIG_DEBUG_FS
2396struct dentry *mce_get_debugfs_dir(void)
2397{
2398 static struct dentry *dmce;
2399
2400 if (!dmce)
2401 dmce = debugfs_create_dir("mce", NULL);
2402
2403 return dmce;
2404}
2405
2406static void mce_reset(void)
2407{
2408 cpu_missing = 0;
2409 atomic_set(&mce_fake_panicked, 0);
2410 atomic_set(&mce_executing, 0);
2411 atomic_set(&mce_callin, 0);
2412 atomic_set(&global_nwo, 0);
2413}
2414
2415static int fake_panic_get(void *data, u64 *val)
2416{
2417 *val = fake_panic;
2418 return 0;
2419}
2420
2421static int fake_panic_set(void *data, u64 val)
2422{
2423 mce_reset();
2424 fake_panic = val;
2425 return 0;
2426}
2427
2428DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2429 fake_panic_set, "%llu\n");
2430
2431static int __init mcheck_debugfs_init(void)
2432{
2433 struct dentry *dmce, *ffake_panic;
2434
2435 dmce = mce_get_debugfs_dir();
2436 if (!dmce)
2437 return -ENOMEM;
2438 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2439 &fake_panic_fops);
2440 if (!ffake_panic)
2441 return -ENOMEM;
2442
2443 return 0;
2444}
2445#else
2446static int __init mcheck_debugfs_init(void) { return -EINVAL; }
2447#endif
2448
2449DEFINE_STATIC_KEY_FALSE(mcsafe_key);
2450EXPORT_SYMBOL_GPL(mcsafe_key);
2451
2452static int __init mcheck_late_init(void)
2453{
2454 if (mca_cfg.recovery)
2455 static_branch_inc(&mcsafe_key);
2456
2457 mcheck_debugfs_init();
2458 cec_init();
2459
2460 /*
2461 * Flush out everything that has been logged during early boot, now that
2462 * everything has been initialized (workqueues, decoders, ...).
2463 */
2464 mce_schedule_work();
2465
2466 return 0;
2467}
2468late_initcall(mcheck_late_init);
2469