1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit
4 *
5 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
6 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
7 * Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
8 * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
9 * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
10 */
11
12
13#include <linux/linkage.h>
14#include <linux/threads.h>
15#include <linux/init.h>
16#include <asm/segment.h>
17#include <asm/pgtable.h>
18#include <asm/page.h>
19#include <asm/msr.h>
20#include <asm/cache.h>
21#include <asm/processor-flags.h>
22#include <asm/percpu.h>
23#include <asm/nops.h>
24#include "../entry/calling.h"
25#include <asm/export.h>
26#include <asm/nospec-branch.h>
27#include <asm/fixmap.h>
28
29#ifdef CONFIG_PARAVIRT_XXL
30#include <asm/asm-offsets.h>
31#include <asm/paravirt.h>
32#define GET_CR2_INTO(reg) GET_CR2_INTO_RAX ; movq %rax, reg
33#else
34#define GET_CR2_INTO(reg) movq %cr2, reg
35#define INTERRUPT_RETURN iretq
36#endif
37
38/* we are not able to switch in one step to the final KERNEL ADDRESS SPACE
39 * because we need identity-mapped pages.
40 *
41 */
42
43#define l4_index(x) (((x) >> 39) & 511)
44#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
45
46L4_PAGE_OFFSET = l4_index(__PAGE_OFFSET_BASE_L4)
47L4_START_KERNEL = l4_index(__START_KERNEL_map)
48
49L3_START_KERNEL = pud_index(__START_KERNEL_map)
50
51 .text
52 __HEAD
53 .code64
54 .globl startup_64
55startup_64:
56 UNWIND_HINT_EMPTY
57 /*
58 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
59 * and someone has loaded an identity mapped page table
60 * for us. These identity mapped page tables map all of the
61 * kernel pages and possibly all of memory.
62 *
63 * %rsi holds a physical pointer to real_mode_data.
64 *
65 * We come here either directly from a 64bit bootloader, or from
66 * arch/x86/boot/compressed/head_64.S.
67 *
68 * We only come here initially at boot nothing else comes here.
69 *
70 * Since we may be loaded at an address different from what we were
71 * compiled to run at we first fixup the physical addresses in our page
72 * tables and then reload them.
73 */
74
75 /* Set up the stack for verify_cpu(), similar to initial_stack below */
76 leaq (__end_init_task - SIZEOF_PTREGS)(%rip), %rsp
77
78 /* Sanitize CPU configuration */
79 call verify_cpu
80
81 /*
82 * Perform pagetable fixups. Additionally, if SME is active, encrypt
83 * the kernel and retrieve the modifier (SME encryption mask if SME
84 * is active) to be added to the initial pgdir entry that will be
85 * programmed into CR3.
86 */
87 leaq _text(%rip), %rdi
88 pushq %rsi
89 call __startup_64
90 popq %rsi
91
92 /* Form the CR3 value being sure to include the CR3 modifier */
93 addq $(early_top_pgt - __START_KERNEL_map), %rax
94 jmp 1f
95ENTRY(secondary_startup_64)
96 UNWIND_HINT_EMPTY
97 /*
98 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
99 * and someone has loaded a mapped page table.
100 *
101 * %rsi holds a physical pointer to real_mode_data.
102 *
103 * We come here either from startup_64 (using physical addresses)
104 * or from trampoline.S (using virtual addresses).
105 *
106 * Using virtual addresses from trampoline.S removes the need
107 * to have any identity mapped pages in the kernel page table
108 * after the boot processor executes this code.
109 */
110
111 /* Sanitize CPU configuration */
112 call verify_cpu
113
114 /*
115 * Retrieve the modifier (SME encryption mask if SME is active) to be
116 * added to the initial pgdir entry that will be programmed into CR3.
117 */
118 pushq %rsi
119 call __startup_secondary_64
120 popq %rsi
121
122 /* Form the CR3 value being sure to include the CR3 modifier */
123 addq $(init_top_pgt - __START_KERNEL_map), %rax
1241:
125
126 /* Enable PAE mode, PGE and LA57 */
127 movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx
128#ifdef CONFIG_X86_5LEVEL
129 testl $1, __pgtable_l5_enabled(%rip)
130 jz 1f
131 orl $X86_CR4_LA57, %ecx
1321:
133#endif
134 movq %rcx, %cr4
135
136 /* Setup early boot stage 4-/5-level pagetables. */
137 addq phys_base(%rip), %rax
138 movq %rax, %cr3
139
140 /* Ensure I am executing from virtual addresses */
141 movq $1f, %rax
142 ANNOTATE_RETPOLINE_SAFE
143 jmp *%rax
1441:
145 UNWIND_HINT_EMPTY
146
147 /* Check if nx is implemented */
148 movl $0x80000001, %eax
149 cpuid
150 movl %edx,%edi
151
152 /* Setup EFER (Extended Feature Enable Register) */
153 movl $MSR_EFER, %ecx
154 rdmsr
155 btsl $_EFER_SCE, %eax /* Enable System Call */
156 btl $20,%edi /* No Execute supported? */
157 jnc 1f
158 btsl $_EFER_NX, %eax
159 btsq $_PAGE_BIT_NX,early_pmd_flags(%rip)
1601: wrmsr /* Make changes effective */
161
162 /* Setup cr0 */
163 movl $CR0_STATE, %eax
164 /* Make changes effective */
165 movq %rax, %cr0
166
167 /* Setup a boot time stack */
168 movq initial_stack(%rip), %rsp
169
170 /* zero EFLAGS after setting rsp */
171 pushq $0
172 popfq
173
174 /*
175 * We must switch to a new descriptor in kernel space for the GDT
176 * because soon the kernel won't have access anymore to the userspace
177 * addresses where we're currently running on. We have to do that here
178 * because in 32bit we couldn't load a 64bit linear address.
179 */
180 lgdt early_gdt_descr(%rip)
181
182 /* set up data segments */
183 xorl %eax,%eax
184 movl %eax,%ds
185 movl %eax,%ss
186 movl %eax,%es
187
188 /*
189 * We don't really need to load %fs or %gs, but load them anyway
190 * to kill any stale realmode selectors. This allows execution
191 * under VT hardware.
192 */
193 movl %eax,%fs
194 movl %eax,%gs
195
196 /* Set up %gs.
197 *
198 * The base of %gs always points to the bottom of the irqstack
199 * union. If the stack protector canary is enabled, it is
200 * located at %gs:40. Note that, on SMP, the boot cpu uses
201 * init data section till per cpu areas are set up.
202 */
203 movl $MSR_GS_BASE,%ecx
204 movl initial_gs(%rip),%eax
205 movl initial_gs+4(%rip),%edx
206 wrmsr
207
208 /* rsi is pointer to real mode structure with interesting info.
209 pass it to C */
210 movq %rsi, %rdi
211
212.Ljump_to_C_code:
213 /*
214 * Jump to run C code and to be on a real kernel address.
215 * Since we are running on identity-mapped space we have to jump
216 * to the full 64bit address, this is only possible as indirect
217 * jump. In addition we need to ensure %cs is set so we make this
218 * a far return.
219 *
220 * Note: do not change to far jump indirect with 64bit offset.
221 *
222 * AMD does not support far jump indirect with 64bit offset.
223 * AMD64 Architecture Programmer's Manual, Volume 3: states only
224 * JMP FAR mem16:16 FF /5 Far jump indirect,
225 * with the target specified by a far pointer in memory.
226 * JMP FAR mem16:32 FF /5 Far jump indirect,
227 * with the target specified by a far pointer in memory.
228 *
229 * Intel64 does support 64bit offset.
230 * Software Developer Manual Vol 2: states:
231 * FF /5 JMP m16:16 Jump far, absolute indirect,
232 * address given in m16:16
233 * FF /5 JMP m16:32 Jump far, absolute indirect,
234 * address given in m16:32.
235 * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect,
236 * address given in m16:64.
237 */
238 pushq $.Lafter_lret # put return address on stack for unwinder
239 xorl %ebp, %ebp # clear frame pointer
240 movq initial_code(%rip), %rax
241 pushq $__KERNEL_CS # set correct cs
242 pushq %rax # target address in negative space
243 lretq
244.Lafter_lret:
245END(secondary_startup_64)
246
247#include "verify_cpu.S"
248
249#ifdef CONFIG_HOTPLUG_CPU
250/*
251 * Boot CPU0 entry point. It's called from play_dead(). Everything has been set
252 * up already except stack. We just set up stack here. Then call
253 * start_secondary() via .Ljump_to_C_code.
254 */
255ENTRY(start_cpu0)
256 movq initial_stack(%rip), %rsp
257 UNWIND_HINT_EMPTY
258 jmp .Ljump_to_C_code
259ENDPROC(start_cpu0)
260#endif
261
262 /* Both SMP bootup and ACPI suspend change these variables */
263 __REFDATA
264 .balign 8
265 GLOBAL(initial_code)
266 .quad x86_64_start_kernel
267 GLOBAL(initial_gs)
268 .quad INIT_PER_CPU_VAR(irq_stack_union)
269 GLOBAL(initial_stack)
270 /*
271 * The SIZEOF_PTREGS gap is a convention which helps the in-kernel
272 * unwinder reliably detect the end of the stack.
273 */
274 .quad init_thread_union + THREAD_SIZE - SIZEOF_PTREGS
275 __FINITDATA
276
277 __INIT
278ENTRY(early_idt_handler_array)
279 i = 0
280 .rept NUM_EXCEPTION_VECTORS
281 .if ((EXCEPTION_ERRCODE_MASK >> i) & 1) == 0
282 UNWIND_HINT_IRET_REGS
283 pushq $0 # Dummy error code, to make stack frame uniform
284 .else
285 UNWIND_HINT_IRET_REGS offset=8
286 .endif
287 pushq $i # 72(%rsp) Vector number
288 jmp early_idt_handler_common
289 UNWIND_HINT_IRET_REGS
290 i = i + 1
291 .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc
292 .endr
293 UNWIND_HINT_IRET_REGS offset=16
294END(early_idt_handler_array)
295
296early_idt_handler_common:
297 /*
298 * The stack is the hardware frame, an error code or zero, and the
299 * vector number.
300 */
301 cld
302
303 incl early_recursion_flag(%rip)
304
305 /* The vector number is currently in the pt_regs->di slot. */
306 pushq %rsi /* pt_regs->si */
307 movq 8(%rsp), %rsi /* RSI = vector number */
308 movq %rdi, 8(%rsp) /* pt_regs->di = RDI */
309 pushq %rdx /* pt_regs->dx */
310 pushq %rcx /* pt_regs->cx */
311 pushq %rax /* pt_regs->ax */
312 pushq %r8 /* pt_regs->r8 */
313 pushq %r9 /* pt_regs->r9 */
314 pushq %r10 /* pt_regs->r10 */
315 pushq %r11 /* pt_regs->r11 */
316 pushq %rbx /* pt_regs->bx */
317 pushq %rbp /* pt_regs->bp */
318 pushq %r12 /* pt_regs->r12 */
319 pushq %r13 /* pt_regs->r13 */
320 pushq %r14 /* pt_regs->r14 */
321 pushq %r15 /* pt_regs->r15 */
322 UNWIND_HINT_REGS
323
324 cmpq $14,%rsi /* Page fault? */
325 jnz 10f
326 GET_CR2_INTO(%rdi) /* Can clobber any volatile register if pv */
327 call early_make_pgtable
328 andl %eax,%eax
329 jz 20f /* All good */
330
33110:
332 movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */
333 call early_fixup_exception
334
33520:
336 decl early_recursion_flag(%rip)
337 jmp restore_regs_and_return_to_kernel
338END(early_idt_handler_common)
339
340 __INITDATA
341
342 .balign 4
343GLOBAL(early_recursion_flag)
344 .long 0
345
346#define NEXT_PAGE(name) \
347 .balign PAGE_SIZE; \
348GLOBAL(name)
349
350#ifdef CONFIG_PAGE_TABLE_ISOLATION
351/*
352 * Each PGD needs to be 8k long and 8k aligned. We do not
353 * ever go out to userspace with these, so we do not
354 * strictly *need* the second page, but this allows us to
355 * have a single set_pgd() implementation that does not
356 * need to worry about whether it has 4k or 8k to work
357 * with.
358 *
359 * This ensures PGDs are 8k long:
360 */
361#define PTI_USER_PGD_FILL 512
362/* This ensures they are 8k-aligned: */
363#define NEXT_PGD_PAGE(name) \
364 .balign 2 * PAGE_SIZE; \
365GLOBAL(name)
366#else
367#define NEXT_PGD_PAGE(name) NEXT_PAGE(name)
368#define PTI_USER_PGD_FILL 0
369#endif
370
371/* Automate the creation of 1 to 1 mapping pmd entries */
372#define PMDS(START, PERM, COUNT) \
373 i = 0 ; \
374 .rept (COUNT) ; \
375 .quad (START) + (i << PMD_SHIFT) + (PERM) ; \
376 i = i + 1 ; \
377 .endr
378
379 __INITDATA
380NEXT_PGD_PAGE(early_top_pgt)
381 .fill 512,8,0
382 .fill PTI_USER_PGD_FILL,8,0
383
384NEXT_PAGE(early_dynamic_pgts)
385 .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0
386
387 .data
388
389#if defined(CONFIG_XEN_PV) || defined(CONFIG_PVH)
390NEXT_PGD_PAGE(init_top_pgt)
391 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
392 .org init_top_pgt + L4_PAGE_OFFSET*8, 0
393 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
394 .org init_top_pgt + L4_START_KERNEL*8, 0
395 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
396 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
397 .fill PTI_USER_PGD_FILL,8,0
398
399NEXT_PAGE(level3_ident_pgt)
400 .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
401 .fill 511, 8, 0
402NEXT_PAGE(level2_ident_pgt)
403 /*
404 * Since I easily can, map the first 1G.
405 * Don't set NX because code runs from these pages.
406 *
407 * Note: This sets _PAGE_GLOBAL despite whether
408 * the CPU supports it or it is enabled. But,
409 * the CPU should ignore the bit.
410 */
411 PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)
412#else
413NEXT_PGD_PAGE(init_top_pgt)
414 .fill 512,8,0
415 .fill PTI_USER_PGD_FILL,8,0
416#endif
417
418#ifdef CONFIG_X86_5LEVEL
419NEXT_PAGE(level4_kernel_pgt)
420 .fill 511,8,0
421 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
422#endif
423
424NEXT_PAGE(level3_kernel_pgt)
425 .fill L3_START_KERNEL,8,0
426 /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
427 .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
428 .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
429
430NEXT_PAGE(level2_kernel_pgt)
431 /*
432 * 512 MB kernel mapping. We spend a full page on this pagetable
433 * anyway.
434 *
435 * The kernel code+data+bss must not be bigger than that.
436 *
437 * (NOTE: at +512MB starts the module area, see MODULES_VADDR.
438 * If you want to increase this then increase MODULES_VADDR
439 * too.)
440 *
441 * This table is eventually used by the kernel during normal
442 * runtime. Care must be taken to clear out undesired bits
443 * later, like _PAGE_RW or _PAGE_GLOBAL in some cases.
444 */
445 PMDS(0, __PAGE_KERNEL_LARGE_EXEC,
446 KERNEL_IMAGE_SIZE/PMD_SIZE)
447
448NEXT_PAGE(level2_fixmap_pgt)
449 .fill (512 - 4 - FIXMAP_PMD_NUM),8,0
450 pgtno = 0
451 .rept (FIXMAP_PMD_NUM)
452 .quad level1_fixmap_pgt + (pgtno << PAGE_SHIFT) - __START_KERNEL_map \
453 + _PAGE_TABLE_NOENC;
454 pgtno = pgtno + 1
455 .endr
456 /* 6 MB reserved space + a 2MB hole */
457 .fill 4,8,0
458
459NEXT_PAGE(level1_fixmap_pgt)
460 .rept (FIXMAP_PMD_NUM)
461 .fill 512,8,0
462 .endr
463
464#undef PMDS
465
466 .data
467 .align 16
468 .globl early_gdt_descr
469early_gdt_descr:
470 .word GDT_ENTRIES*8-1
471early_gdt_descr_base:
472 .quad INIT_PER_CPU_VAR(gdt_page)
473
474ENTRY(phys_base)
475 /* This must match the first entry in level2_kernel_pgt */
476 .quad 0x0000000000000000
477EXPORT_SYMBOL(phys_base)
478
479#include "../../x86/xen/xen-head.S"
480
481 __PAGE_ALIGNED_BSS
482NEXT_PAGE(empty_zero_page)
483 .skip PAGE_SIZE
484EXPORT_SYMBOL(empty_zero_page)
485
486