1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | #ifndef __KVM_X86_LAPIC_H |
3 | #define __KVM_X86_LAPIC_H |
4 | |
5 | #include <kvm/iodev.h> |
6 | |
7 | #include <linux/kvm_host.h> |
8 | |
9 | #include "hyperv.h" |
10 | #include "smm.h" |
11 | |
12 | #define KVM_APIC_INIT 0 |
13 | #define KVM_APIC_SIPI 1 |
14 | |
15 | #define APIC_SHORT_MASK 0xc0000 |
16 | #define APIC_DEST_NOSHORT 0x0 |
17 | #define APIC_DEST_MASK 0x800 |
18 | |
19 | #define APIC_BUS_CYCLE_NS 1 |
20 | #define APIC_BUS_FREQUENCY (1000000000ULL / APIC_BUS_CYCLE_NS) |
21 | |
22 | #define APIC_BROADCAST 0xFF |
23 | #define X2APIC_BROADCAST 0xFFFFFFFFul |
24 | |
25 | enum lapic_mode { |
26 | LAPIC_MODE_DISABLED = 0, |
27 | LAPIC_MODE_INVALID = X2APIC_ENABLE, |
28 | LAPIC_MODE_XAPIC = MSR_IA32_APICBASE_ENABLE, |
29 | LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE, |
30 | }; |
31 | |
32 | enum lapic_lvt_entry { |
33 | LVT_TIMER, |
34 | LVT_THERMAL_MONITOR, |
35 | LVT_PERFORMANCE_COUNTER, |
36 | LVT_LINT0, |
37 | LVT_LINT1, |
38 | LVT_ERROR, |
39 | LVT_CMCI, |
40 | |
41 | KVM_APIC_MAX_NR_LVT_ENTRIES, |
42 | }; |
43 | |
44 | #define APIC_LVTx(x) ((x) == LVT_CMCI ? APIC_LVTCMCI : APIC_LVTT + 0x10 * (x)) |
45 | |
46 | struct kvm_timer { |
47 | struct hrtimer timer; |
48 | s64 period; /* unit: ns */ |
49 | ktime_t target_expiration; |
50 | u32 timer_mode; |
51 | u32 timer_mode_mask; |
52 | u64 tscdeadline; |
53 | u64 expired_tscdeadline; |
54 | u32 timer_advance_ns; |
55 | atomic_t pending; /* accumulated triggered timers */ |
56 | bool hv_timer_in_use; |
57 | }; |
58 | |
59 | struct kvm_lapic { |
60 | unsigned long base_address; |
61 | struct kvm_io_device dev; |
62 | struct kvm_timer lapic_timer; |
63 | u32 divide_count; |
64 | struct kvm_vcpu *vcpu; |
65 | bool apicv_active; |
66 | bool sw_enabled; |
67 | bool irr_pending; |
68 | bool lvt0_in_nmi_mode; |
69 | /* Number of bits set in ISR. */ |
70 | s16 isr_count; |
71 | /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */ |
72 | int highest_isr_cache; |
73 | /** |
74 | * APIC register page. The layout matches the register layout seen by |
75 | * the guest 1:1, because it is accessed by the vmx microcode. |
76 | * Note: Only one register, the TPR, is used by the microcode. |
77 | */ |
78 | void *regs; |
79 | gpa_t vapic_addr; |
80 | struct gfn_to_hva_cache vapic_cache; |
81 | unsigned long pending_events; |
82 | unsigned int sipi_vector; |
83 | int nr_lvt_entries; |
84 | }; |
85 | |
86 | struct dest_map; |
87 | |
88 | int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns); |
89 | void kvm_free_lapic(struct kvm_vcpu *vcpu); |
90 | |
91 | int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu); |
92 | int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu); |
93 | int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu); |
94 | int kvm_apic_accept_events(struct kvm_vcpu *vcpu); |
95 | void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event); |
96 | u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu); |
97 | void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8); |
98 | void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu); |
99 | void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value); |
100 | u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu); |
101 | void kvm_recalculate_apic_map(struct kvm *kvm); |
102 | void kvm_apic_set_version(struct kvm_vcpu *vcpu); |
103 | void kvm_apic_after_set_mcg_cap(struct kvm_vcpu *vcpu); |
104 | bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source, |
105 | int shorthand, unsigned int dest, int dest_mode); |
106 | int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2); |
107 | void kvm_apic_clear_irr(struct kvm_vcpu *vcpu, int vec); |
108 | bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr); |
109 | bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr); |
110 | void kvm_apic_update_ppr(struct kvm_vcpu *vcpu); |
111 | int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq, |
112 | struct dest_map *dest_map); |
113 | int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type); |
114 | void kvm_apic_update_apicv(struct kvm_vcpu *vcpu); |
115 | int kvm_alloc_apic_access_page(struct kvm *kvm); |
116 | void kvm_inhibit_apic_access_page(struct kvm_vcpu *vcpu); |
117 | |
118 | bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src, |
119 | struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map); |
120 | void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high); |
121 | |
122 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu); |
123 | int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info); |
124 | int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s); |
125 | int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s); |
126 | enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu); |
127 | int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu); |
128 | |
129 | u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu); |
130 | void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data); |
131 | |
132 | void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset); |
133 | void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector); |
134 | |
135 | int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr); |
136 | void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu); |
137 | void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu); |
138 | |
139 | int kvm_x2apic_icr_write(struct kvm_lapic *apic, u64 data); |
140 | int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); |
141 | int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); |
142 | |
143 | int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); |
144 | int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); |
145 | |
146 | int kvm_lapic_set_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len); |
147 | void kvm_lapic_exit(void); |
148 | |
149 | u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic); |
150 | |
151 | #define VEC_POS(v) ((v) & (32 - 1)) |
152 | #define REG_POS(v) (((v) >> 5) << 4) |
153 | |
154 | static inline void kvm_lapic_clear_vector(int vec, void *bitmap) |
155 | { |
156 | clear_bit(VEC_POS(vec), addr: (bitmap) + REG_POS(vec)); |
157 | } |
158 | |
159 | static inline void kvm_lapic_set_vector(int vec, void *bitmap) |
160 | { |
161 | set_bit(VEC_POS(vec), addr: (bitmap) + REG_POS(vec)); |
162 | } |
163 | |
164 | static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic) |
165 | { |
166 | kvm_lapic_set_vector(vec, bitmap: apic->regs + APIC_IRR); |
167 | /* |
168 | * irr_pending must be true if any interrupt is pending; set it after |
169 | * APIC_IRR to avoid race with apic_clear_irr |
170 | */ |
171 | apic->irr_pending = true; |
172 | } |
173 | |
174 | static inline u32 __kvm_lapic_get_reg(char *regs, int reg_off) |
175 | { |
176 | return *((u32 *) (regs + reg_off)); |
177 | } |
178 | |
179 | static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off) |
180 | { |
181 | return __kvm_lapic_get_reg(regs: apic->regs, reg_off); |
182 | } |
183 | |
184 | DECLARE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu); |
185 | |
186 | static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu) |
187 | { |
188 | if (static_branch_unlikely(&kvm_has_noapic_vcpu)) |
189 | return vcpu->arch.apic; |
190 | return true; |
191 | } |
192 | |
193 | extern struct static_key_false_deferred apic_hw_disabled; |
194 | |
195 | static inline bool kvm_apic_hw_enabled(struct kvm_lapic *apic) |
196 | { |
197 | if (static_branch_unlikely(&apic_hw_disabled.key)) |
198 | return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE; |
199 | return true; |
200 | } |
201 | |
202 | extern struct static_key_false_deferred apic_sw_disabled; |
203 | |
204 | static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic) |
205 | { |
206 | if (static_branch_unlikely(&apic_sw_disabled.key)) |
207 | return apic->sw_enabled; |
208 | return true; |
209 | } |
210 | |
211 | static inline bool kvm_apic_present(struct kvm_vcpu *vcpu) |
212 | { |
213 | return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(apic: vcpu->arch.apic); |
214 | } |
215 | |
216 | static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu) |
217 | { |
218 | return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(apic: vcpu->arch.apic); |
219 | } |
220 | |
221 | static inline int apic_x2apic_mode(struct kvm_lapic *apic) |
222 | { |
223 | return apic->vcpu->arch.apic_base & X2APIC_ENABLE; |
224 | } |
225 | |
226 | static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu) |
227 | { |
228 | return lapic_in_kernel(vcpu) && vcpu->arch.apic->apicv_active; |
229 | } |
230 | |
231 | static inline bool kvm_apic_has_pending_init_or_sipi(struct kvm_vcpu *vcpu) |
232 | { |
233 | return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events; |
234 | } |
235 | |
236 | static inline bool kvm_apic_init_sipi_allowed(struct kvm_vcpu *vcpu) |
237 | { |
238 | return !is_smm(vcpu) && |
239 | !static_call(kvm_x86_apic_init_signal_blocked)(vcpu); |
240 | } |
241 | |
242 | static inline bool kvm_lowest_prio_delivery(struct kvm_lapic_irq *irq) |
243 | { |
244 | return (irq->delivery_mode == APIC_DM_LOWEST || |
245 | irq->msi_redir_hint); |
246 | } |
247 | |
248 | static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu) |
249 | { |
250 | return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); |
251 | } |
252 | |
253 | bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector); |
254 | |
255 | void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu); |
256 | |
257 | void kvm_bitmap_or_dest_vcpus(struct kvm *kvm, struct kvm_lapic_irq *irq, |
258 | unsigned long *vcpu_bitmap); |
259 | |
260 | bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq, |
261 | struct kvm_vcpu **dest_vcpu); |
262 | int kvm_vector_to_index(u32 vector, u32 dest_vcpus, |
263 | const unsigned long *bitmap, u32 bitmap_size); |
264 | void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu); |
265 | void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu); |
266 | void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu); |
267 | bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu); |
268 | void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu); |
269 | bool kvm_can_use_hv_timer(struct kvm_vcpu *vcpu); |
270 | |
271 | static inline enum lapic_mode kvm_apic_mode(u64 apic_base) |
272 | { |
273 | return apic_base & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); |
274 | } |
275 | |
276 | static inline u8 kvm_xapic_id(struct kvm_lapic *apic) |
277 | { |
278 | return kvm_lapic_get_reg(apic, APIC_ID) >> 24; |
279 | } |
280 | |
281 | #endif |
282 | |