1/*
2 * pci_root.c - ACPI PCI Root Bridge Driver ($Revision: 40 $)
3 *
4 * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
5 * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
6 *
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or (at
12 * your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/init.h>
25#include <linux/types.h>
26#include <linux/mutex.h>
27#include <linux/pm.h>
28#include <linux/pm_runtime.h>
29#include <linux/pci.h>
30#include <linux/pci-acpi.h>
31#include <linux/pci-aspm.h>
32#include <linux/dmar.h>
33#include <linux/acpi.h>
34#include <linux/slab.h>
35#include <linux/dmi.h>
36#include <linux/platform_data/x86/apple.h>
37#include <acpi/apei.h> /* for acpi_hest_init() */
38
39#include "internal.h"
40
41#define _COMPONENT ACPI_PCI_COMPONENT
42ACPI_MODULE_NAME("pci_root");
43#define ACPI_PCI_ROOT_CLASS "pci_bridge"
44#define ACPI_PCI_ROOT_DEVICE_NAME "PCI Root Bridge"
45static int acpi_pci_root_add(struct acpi_device *device,
46 const struct acpi_device_id *not_used);
47static void acpi_pci_root_remove(struct acpi_device *device);
48
49static int acpi_pci_root_scan_dependent(struct acpi_device *adev)
50{
51 acpiphp_check_host_bridge(adev);
52 return 0;
53}
54
55#define ACPI_PCIE_REQ_SUPPORT (OSC_PCI_EXT_CONFIG_SUPPORT \
56 | OSC_PCI_ASPM_SUPPORT \
57 | OSC_PCI_CLOCK_PM_SUPPORT \
58 | OSC_PCI_MSI_SUPPORT)
59
60static const struct acpi_device_id root_device_ids[] = {
61 {"PNP0A03", 0},
62 {"", 0},
63};
64
65static struct acpi_scan_handler pci_root_handler = {
66 .ids = root_device_ids,
67 .attach = acpi_pci_root_add,
68 .detach = acpi_pci_root_remove,
69 .hotplug = {
70 .enabled = true,
71 .scan_dependent = acpi_pci_root_scan_dependent,
72 },
73};
74
75static DEFINE_MUTEX(osc_lock);
76
77/**
78 * acpi_is_root_bridge - determine whether an ACPI CA node is a PCI root bridge
79 * @handle - the ACPI CA node in question.
80 *
81 * Note: we could make this API take a struct acpi_device * instead, but
82 * for now, it's more convenient to operate on an acpi_handle.
83 */
84int acpi_is_root_bridge(acpi_handle handle)
85{
86 int ret;
87 struct acpi_device *device;
88
89 ret = acpi_bus_get_device(handle, &device);
90 if (ret)
91 return 0;
92
93 ret = acpi_match_device_ids(device, root_device_ids);
94 if (ret)
95 return 0;
96 else
97 return 1;
98}
99EXPORT_SYMBOL_GPL(acpi_is_root_bridge);
100
101static acpi_status
102get_root_bridge_busnr_callback(struct acpi_resource *resource, void *data)
103{
104 struct resource *res = data;
105 struct acpi_resource_address64 address;
106 acpi_status status;
107
108 status = acpi_resource_to_address64(resource, &address);
109 if (ACPI_FAILURE(status))
110 return AE_OK;
111
112 if ((address.address.address_length > 0) &&
113 (address.resource_type == ACPI_BUS_NUMBER_RANGE)) {
114 res->start = address.address.minimum;
115 res->end = address.address.minimum + address.address.address_length - 1;
116 }
117
118 return AE_OK;
119}
120
121static acpi_status try_get_root_bridge_busnr(acpi_handle handle,
122 struct resource *res)
123{
124 acpi_status status;
125
126 res->start = -1;
127 status =
128 acpi_walk_resources(handle, METHOD_NAME__CRS,
129 get_root_bridge_busnr_callback, res);
130 if (ACPI_FAILURE(status))
131 return status;
132 if (res->start == -1)
133 return AE_ERROR;
134 return AE_OK;
135}
136
137struct pci_osc_bit_struct {
138 u32 bit;
139 char *desc;
140};
141
142static struct pci_osc_bit_struct pci_osc_support_bit[] = {
143 { OSC_PCI_EXT_CONFIG_SUPPORT, "ExtendedConfig" },
144 { OSC_PCI_ASPM_SUPPORT, "ASPM" },
145 { OSC_PCI_CLOCK_PM_SUPPORT, "ClockPM" },
146 { OSC_PCI_SEGMENT_GROUPS_SUPPORT, "Segments" },
147 { OSC_PCI_MSI_SUPPORT, "MSI" },
148};
149
150static struct pci_osc_bit_struct pci_osc_control_bit[] = {
151 { OSC_PCI_EXPRESS_NATIVE_HP_CONTROL, "PCIeHotplug" },
152 { OSC_PCI_SHPC_NATIVE_HP_CONTROL, "SHPCHotplug" },
153 { OSC_PCI_EXPRESS_PME_CONTROL, "PME" },
154 { OSC_PCI_EXPRESS_AER_CONTROL, "AER" },
155 { OSC_PCI_EXPRESS_CAPABILITY_CONTROL, "PCIeCapability" },
156 { OSC_PCI_EXPRESS_LTR_CONTROL, "LTR" },
157};
158
159static void decode_osc_bits(struct acpi_pci_root *root, char *msg, u32 word,
160 struct pci_osc_bit_struct *table, int size)
161{
162 char buf[80];
163 int i, len = 0;
164 struct pci_osc_bit_struct *entry;
165
166 buf[0] = '\0';
167 for (i = 0, entry = table; i < size; i++, entry++)
168 if (word & entry->bit)
169 len += snprintf(buf + len, sizeof(buf) - len, "%s%s",
170 len ? " " : "", entry->desc);
171
172 dev_info(&root->device->dev, "_OSC: %s [%s]\n", msg, buf);
173}
174
175static void decode_osc_support(struct acpi_pci_root *root, char *msg, u32 word)
176{
177 decode_osc_bits(root, msg, word, pci_osc_support_bit,
178 ARRAY_SIZE(pci_osc_support_bit));
179}
180
181static void decode_osc_control(struct acpi_pci_root *root, char *msg, u32 word)
182{
183 decode_osc_bits(root, msg, word, pci_osc_control_bit,
184 ARRAY_SIZE(pci_osc_control_bit));
185}
186
187static u8 pci_osc_uuid_str[] = "33DB4D5B-1FF7-401C-9657-7441C03DD766";
188
189static acpi_status acpi_pci_run_osc(acpi_handle handle,
190 const u32 *capbuf, u32 *retval)
191{
192 struct acpi_osc_context context = {
193 .uuid_str = pci_osc_uuid_str,
194 .rev = 1,
195 .cap.length = 12,
196 .cap.pointer = (void *)capbuf,
197 };
198 acpi_status status;
199
200 status = acpi_run_osc(handle, &context);
201 if (ACPI_SUCCESS(status)) {
202 *retval = *((u32 *)(context.ret.pointer + 8));
203 kfree(context.ret.pointer);
204 }
205 return status;
206}
207
208static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root,
209 u32 support,
210 u32 *control)
211{
212 acpi_status status;
213 u32 result, capbuf[3];
214
215 support &= OSC_PCI_SUPPORT_MASKS;
216 support |= root->osc_support_set;
217
218 capbuf[OSC_QUERY_DWORD] = OSC_QUERY_ENABLE;
219 capbuf[OSC_SUPPORT_DWORD] = support;
220 if (control) {
221 *control &= OSC_PCI_CONTROL_MASKS;
222 capbuf[OSC_CONTROL_DWORD] = *control | root->osc_control_set;
223 } else {
224 /* Run _OSC query only with existing controls. */
225 capbuf[OSC_CONTROL_DWORD] = root->osc_control_set;
226 }
227
228 status = acpi_pci_run_osc(root->device->handle, capbuf, &result);
229 if (ACPI_SUCCESS(status)) {
230 root->osc_support_set = support;
231 if (control)
232 *control = result;
233 }
234 return status;
235}
236
237static acpi_status acpi_pci_osc_support(struct acpi_pci_root *root, u32 flags)
238{
239 acpi_status status;
240
241 mutex_lock(&osc_lock);
242 status = acpi_pci_query_osc(root, flags, NULL);
243 mutex_unlock(&osc_lock);
244 return status;
245}
246
247struct acpi_pci_root *acpi_pci_find_root(acpi_handle handle)
248{
249 struct acpi_pci_root *root;
250 struct acpi_device *device;
251
252 if (acpi_bus_get_device(handle, &device) ||
253 acpi_match_device_ids(device, root_device_ids))
254 return NULL;
255
256 root = acpi_driver_data(device);
257
258 return root;
259}
260EXPORT_SYMBOL_GPL(acpi_pci_find_root);
261
262struct acpi_handle_node {
263 struct list_head node;
264 acpi_handle handle;
265};
266
267/**
268 * acpi_get_pci_dev - convert ACPI CA handle to struct pci_dev
269 * @handle: the handle in question
270 *
271 * Given an ACPI CA handle, the desired PCI device is located in the
272 * list of PCI devices.
273 *
274 * If the device is found, its reference count is increased and this
275 * function returns a pointer to its data structure. The caller must
276 * decrement the reference count by calling pci_dev_put().
277 * If no device is found, %NULL is returned.
278 */
279struct pci_dev *acpi_get_pci_dev(acpi_handle handle)
280{
281 int dev, fn;
282 unsigned long long adr;
283 acpi_status status;
284 acpi_handle phandle;
285 struct pci_bus *pbus;
286 struct pci_dev *pdev = NULL;
287 struct acpi_handle_node *node, *tmp;
288 struct acpi_pci_root *root;
289 LIST_HEAD(device_list);
290
291 /*
292 * Walk up the ACPI CA namespace until we reach a PCI root bridge.
293 */
294 phandle = handle;
295 while (!acpi_is_root_bridge(phandle)) {
296 node = kzalloc(sizeof(struct acpi_handle_node), GFP_KERNEL);
297 if (!node)
298 goto out;
299
300 INIT_LIST_HEAD(&node->node);
301 node->handle = phandle;
302 list_add(&node->node, &device_list);
303
304 status = acpi_get_parent(phandle, &phandle);
305 if (ACPI_FAILURE(status))
306 goto out;
307 }
308
309 root = acpi_pci_find_root(phandle);
310 if (!root)
311 goto out;
312
313 pbus = root->bus;
314
315 /*
316 * Now, walk back down the PCI device tree until we return to our
317 * original handle. Assumes that everything between the PCI root
318 * bridge and the device we're looking for must be a P2P bridge.
319 */
320 list_for_each_entry(node, &device_list, node) {
321 acpi_handle hnd = node->handle;
322 status = acpi_evaluate_integer(hnd, "_ADR", NULL, &adr);
323 if (ACPI_FAILURE(status))
324 goto out;
325 dev = (adr >> 16) & 0xffff;
326 fn = adr & 0xffff;
327
328 pdev = pci_get_slot(pbus, PCI_DEVFN(dev, fn));
329 if (!pdev || hnd == handle)
330 break;
331
332 pbus = pdev->subordinate;
333 pci_dev_put(pdev);
334
335 /*
336 * This function may be called for a non-PCI device that has a
337 * PCI parent (eg. a disk under a PCI SATA controller). In that
338 * case pdev->subordinate will be NULL for the parent.
339 */
340 if (!pbus) {
341 dev_dbg(&pdev->dev, "Not a PCI-to-PCI bridge\n");
342 pdev = NULL;
343 break;
344 }
345 }
346out:
347 list_for_each_entry_safe(node, tmp, &device_list, node)
348 kfree(node);
349
350 return pdev;
351}
352EXPORT_SYMBOL_GPL(acpi_get_pci_dev);
353
354/**
355 * acpi_pci_osc_control_set - Request control of PCI root _OSC features.
356 * @handle: ACPI handle of a PCI root bridge (or PCIe Root Complex).
357 * @mask: Mask of _OSC bits to request control of, place to store control mask.
358 * @req: Mask of _OSC bits the control of is essential to the caller.
359 *
360 * Run _OSC query for @mask and if that is successful, compare the returned
361 * mask of control bits with @req. If all of the @req bits are set in the
362 * returned mask, run _OSC request for it.
363 *
364 * The variable at the @mask address may be modified regardless of whether or
365 * not the function returns success. On success it will contain the mask of
366 * _OSC bits the BIOS has granted control of, but its contents are meaningless
367 * on failure.
368 **/
369acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 req)
370{
371 struct acpi_pci_root *root;
372 acpi_status status = AE_OK;
373 u32 ctrl, capbuf[3];
374
375 if (!mask)
376 return AE_BAD_PARAMETER;
377
378 ctrl = *mask & OSC_PCI_CONTROL_MASKS;
379 if ((ctrl & req) != req)
380 return AE_TYPE;
381
382 root = acpi_pci_find_root(handle);
383 if (!root)
384 return AE_NOT_EXIST;
385
386 mutex_lock(&osc_lock);
387
388 *mask = ctrl | root->osc_control_set;
389 /* No need to evaluate _OSC if the control was already granted. */
390 if ((root->osc_control_set & ctrl) == ctrl)
391 goto out;
392
393 /* Need to check the available controls bits before requesting them. */
394 while (*mask) {
395 status = acpi_pci_query_osc(root, root->osc_support_set, mask);
396 if (ACPI_FAILURE(status))
397 goto out;
398 if (ctrl == *mask)
399 break;
400 decode_osc_control(root, "platform does not support",
401 ctrl & ~(*mask));
402 ctrl = *mask;
403 }
404
405 if ((ctrl & req) != req) {
406 decode_osc_control(root, "not requesting control; platform does not support",
407 req & ~(ctrl));
408 status = AE_SUPPORT;
409 goto out;
410 }
411
412 capbuf[OSC_QUERY_DWORD] = 0;
413 capbuf[OSC_SUPPORT_DWORD] = root->osc_support_set;
414 capbuf[OSC_CONTROL_DWORD] = ctrl;
415 status = acpi_pci_run_osc(handle, capbuf, mask);
416 if (ACPI_SUCCESS(status))
417 root->osc_control_set = *mask;
418out:
419 mutex_unlock(&osc_lock);
420 return status;
421}
422EXPORT_SYMBOL(acpi_pci_osc_control_set);
423
424static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm,
425 bool is_pcie)
426{
427 u32 support, control, requested;
428 acpi_status status;
429 struct acpi_device *device = root->device;
430 acpi_handle handle = device->handle;
431
432 /*
433 * Apple always return failure on _OSC calls when _OSI("Darwin") has
434 * been called successfully. We know the feature set supported by the
435 * platform, so avoid calling _OSC at all
436 */
437 if (x86_apple_machine) {
438 root->osc_control_set = ~OSC_PCI_EXPRESS_PME_CONTROL;
439 decode_osc_control(root, "OS assumes control of",
440 root->osc_control_set);
441 return;
442 }
443
444 /*
445 * All supported architectures that use ACPI have support for
446 * PCI domains, so we indicate this in _OSC support capabilities.
447 */
448 support = OSC_PCI_SEGMENT_GROUPS_SUPPORT;
449 if (pci_ext_cfg_avail())
450 support |= OSC_PCI_EXT_CONFIG_SUPPORT;
451 if (pcie_aspm_support_enabled())
452 support |= OSC_PCI_ASPM_SUPPORT | OSC_PCI_CLOCK_PM_SUPPORT;
453 if (pci_msi_enabled())
454 support |= OSC_PCI_MSI_SUPPORT;
455
456 decode_osc_support(root, "OS supports", support);
457 status = acpi_pci_osc_support(root, support);
458 if (ACPI_FAILURE(status)) {
459 *no_aspm = 1;
460
461 /* _OSC is optional for PCI host bridges */
462 if ((status == AE_NOT_FOUND) && !is_pcie)
463 return;
464
465 dev_info(&device->dev, "_OSC failed (%s)%s\n",
466 acpi_format_exception(status),
467 pcie_aspm_support_enabled() ? "; disabling ASPM" : "");
468 return;
469 }
470
471 if (pcie_ports_disabled) {
472 dev_info(&device->dev, "PCIe port services disabled; not requesting _OSC control\n");
473 return;
474 }
475
476 if ((support & ACPI_PCIE_REQ_SUPPORT) != ACPI_PCIE_REQ_SUPPORT) {
477 decode_osc_support(root, "not requesting OS control; OS requires",
478 ACPI_PCIE_REQ_SUPPORT);
479 return;
480 }
481
482 control = OSC_PCI_EXPRESS_CAPABILITY_CONTROL
483 | OSC_PCI_EXPRESS_PME_CONTROL;
484
485 if (IS_ENABLED(CONFIG_PCIEASPM))
486 control |= OSC_PCI_EXPRESS_LTR_CONTROL;
487
488 if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE))
489 control |= OSC_PCI_EXPRESS_NATIVE_HP_CONTROL;
490
491 if (IS_ENABLED(CONFIG_HOTPLUG_PCI_SHPC))
492 control |= OSC_PCI_SHPC_NATIVE_HP_CONTROL;
493
494 if (pci_aer_available()) {
495 if (aer_acpi_firmware_first())
496 dev_info(&device->dev,
497 "PCIe AER handled by firmware\n");
498 else
499 control |= OSC_PCI_EXPRESS_AER_CONTROL;
500 }
501
502 requested = control;
503 status = acpi_pci_osc_control_set(handle, &control,
504 OSC_PCI_EXPRESS_CAPABILITY_CONTROL);
505 if (ACPI_SUCCESS(status)) {
506 decode_osc_control(root, "OS now controls", control);
507 if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) {
508 /*
509 * We have ASPM control, but the FADT indicates that
510 * it's unsupported. Leave existing configuration
511 * intact and prevent the OS from touching it.
512 */
513 dev_info(&device->dev, "FADT indicates ASPM is unsupported, using BIOS configuration\n");
514 *no_aspm = 1;
515 }
516 } else {
517 decode_osc_control(root, "OS requested", requested);
518 decode_osc_control(root, "platform willing to grant", control);
519 dev_info(&device->dev, "_OSC failed (%s); disabling ASPM\n",
520 acpi_format_exception(status));
521
522 /*
523 * We want to disable ASPM here, but aspm_disabled
524 * needs to remain in its state from boot so that we
525 * properly handle PCIe 1.1 devices. So we set this
526 * flag here, to defer the action until after the ACPI
527 * root scan.
528 */
529 *no_aspm = 1;
530 }
531}
532
533static int acpi_pci_root_add(struct acpi_device *device,
534 const struct acpi_device_id *not_used)
535{
536 unsigned long long segment, bus;
537 acpi_status status;
538 int result;
539 struct acpi_pci_root *root;
540 acpi_handle handle = device->handle;
541 int no_aspm = 0;
542 bool hotadd = system_state == SYSTEM_RUNNING;
543 bool is_pcie;
544
545 root = kzalloc(sizeof(struct acpi_pci_root), GFP_KERNEL);
546 if (!root)
547 return -ENOMEM;
548
549 segment = 0;
550 status = acpi_evaluate_integer(handle, METHOD_NAME__SEG, NULL,
551 &segment);
552 if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) {
553 dev_err(&device->dev, "can't evaluate _SEG\n");
554 result = -ENODEV;
555 goto end;
556 }
557
558 /* Check _CRS first, then _BBN. If no _BBN, default to zero. */
559 root->secondary.flags = IORESOURCE_BUS;
560 status = try_get_root_bridge_busnr(handle, &root->secondary);
561 if (ACPI_FAILURE(status)) {
562 /*
563 * We need both the start and end of the downstream bus range
564 * to interpret _CBA (MMCONFIG base address), so it really is
565 * supposed to be in _CRS. If we don't find it there, all we
566 * can do is assume [_BBN-0xFF] or [0-0xFF].
567 */
568 root->secondary.end = 0xFF;
569 dev_warn(&device->dev,
570 FW_BUG "no secondary bus range in _CRS\n");
571 status = acpi_evaluate_integer(handle, METHOD_NAME__BBN,
572 NULL, &bus);
573 if (ACPI_SUCCESS(status))
574 root->secondary.start = bus;
575 else if (status == AE_NOT_FOUND)
576 root->secondary.start = 0;
577 else {
578 dev_err(&device->dev, "can't evaluate _BBN\n");
579 result = -ENODEV;
580 goto end;
581 }
582 }
583
584 root->device = device;
585 root->segment = segment & 0xFFFF;
586 strcpy(acpi_device_name(device), ACPI_PCI_ROOT_DEVICE_NAME);
587 strcpy(acpi_device_class(device), ACPI_PCI_ROOT_CLASS);
588 device->driver_data = root;
589
590 if (hotadd && dmar_device_add(handle)) {
591 result = -ENXIO;
592 goto end;
593 }
594
595 pr_info(PREFIX "%s [%s] (domain %04x %pR)\n",
596 acpi_device_name(device), acpi_device_bid(device),
597 root->segment, &root->secondary);
598
599 root->mcfg_addr = acpi_pci_root_get_mcfg_addr(handle);
600
601 is_pcie = strcmp(acpi_device_hid(device), "PNP0A08") == 0;
602 negotiate_os_control(root, &no_aspm, is_pcie);
603
604 /*
605 * TBD: Need PCI interface for enumeration/configuration of roots.
606 */
607
608 /*
609 * Scan the Root Bridge
610 * --------------------
611 * Must do this prior to any attempt to bind the root device, as the
612 * PCI namespace does not get created until this call is made (and
613 * thus the root bridge's pci_dev does not exist).
614 */
615 root->bus = pci_acpi_scan_root(root);
616 if (!root->bus) {
617 dev_err(&device->dev,
618 "Bus %04x:%02x not present in PCI namespace\n",
619 root->segment, (unsigned int)root->secondary.start);
620 device->driver_data = NULL;
621 result = -ENODEV;
622 goto remove_dmar;
623 }
624
625 if (no_aspm)
626 pcie_no_aspm();
627
628 pci_acpi_add_bus_pm_notifier(device);
629 device_set_wakeup_capable(root->bus->bridge, device->wakeup.flags.valid);
630
631 if (hotadd) {
632 pcibios_resource_survey_bus(root->bus);
633 pci_assign_unassigned_root_bus_resources(root->bus);
634 /*
635 * This is only called for the hotadd case. For the boot-time
636 * case, we need to wait until after PCI initialization in
637 * order to deal with IOAPICs mapped in on a PCI BAR.
638 *
639 * This is currently x86-specific, because acpi_ioapic_add()
640 * is an empty function without CONFIG_ACPI_HOTPLUG_IOAPIC.
641 * And CONFIG_ACPI_HOTPLUG_IOAPIC depends on CONFIG_X86_IO_APIC
642 * (see drivers/acpi/Kconfig).
643 */
644 acpi_ioapic_add(root->device->handle);
645 }
646
647 pci_lock_rescan_remove();
648 pci_bus_add_devices(root->bus);
649 pci_unlock_rescan_remove();
650 return 1;
651
652remove_dmar:
653 if (hotadd)
654 dmar_device_remove(handle);
655end:
656 kfree(root);
657 return result;
658}
659
660static void acpi_pci_root_remove(struct acpi_device *device)
661{
662 struct acpi_pci_root *root = acpi_driver_data(device);
663
664 pci_lock_rescan_remove();
665
666 pci_stop_root_bus(root->bus);
667
668 pci_ioapic_remove(root);
669 device_set_wakeup_capable(root->bus->bridge, false);
670 pci_acpi_remove_bus_pm_notifier(device);
671
672 pci_remove_root_bus(root->bus);
673 WARN_ON(acpi_ioapic_remove(root));
674
675 dmar_device_remove(device->handle);
676
677 pci_unlock_rescan_remove();
678
679 kfree(root);
680}
681
682/*
683 * Following code to support acpi_pci_root_create() is copied from
684 * arch/x86/pci/acpi.c and modified so it could be reused by x86, IA64
685 * and ARM64.
686 */
687static void acpi_pci_root_validate_resources(struct device *dev,
688 struct list_head *resources,
689 unsigned long type)
690{
691 LIST_HEAD(list);
692 struct resource *res1, *res2, *root = NULL;
693 struct resource_entry *tmp, *entry, *entry2;
694
695 BUG_ON((type & (IORESOURCE_MEM | IORESOURCE_IO)) == 0);
696 root = (type & IORESOURCE_MEM) ? &iomem_resource : &ioport_resource;
697
698 list_splice_init(resources, &list);
699 resource_list_for_each_entry_safe(entry, tmp, &list) {
700 bool free = false;
701 resource_size_t end;
702
703 res1 = entry->res;
704 if (!(res1->flags & type))
705 goto next;
706
707 /* Exclude non-addressable range or non-addressable portion */
708 end = min(res1->end, root->end);
709 if (end <= res1->start) {
710 dev_info(dev, "host bridge window %pR (ignored, not CPU addressable)\n",
711 res1);
712 free = true;
713 goto next;
714 } else if (res1->end != end) {
715 dev_info(dev, "host bridge window %pR ([%#llx-%#llx] ignored, not CPU addressable)\n",
716 res1, (unsigned long long)end + 1,
717 (unsigned long long)res1->end);
718 res1->end = end;
719 }
720
721 resource_list_for_each_entry(entry2, resources) {
722 res2 = entry2->res;
723 if (!(res2->flags & type))
724 continue;
725
726 /*
727 * I don't like throwing away windows because then
728 * our resources no longer match the ACPI _CRS, but
729 * the kernel resource tree doesn't allow overlaps.
730 */
731 if (resource_overlaps(res1, res2)) {
732 res2->start = min(res1->start, res2->start);
733 res2->end = max(res1->end, res2->end);
734 dev_info(dev, "host bridge window expanded to %pR; %pR ignored\n",
735 res2, res1);
736 free = true;
737 goto next;
738 }
739 }
740
741next:
742 resource_list_del(entry);
743 if (free)
744 resource_list_free_entry(entry);
745 else
746 resource_list_add_tail(entry, resources);
747 }
748}
749
750static void acpi_pci_root_remap_iospace(struct fwnode_handle *fwnode,
751 struct resource_entry *entry)
752{
753#ifdef PCI_IOBASE
754 struct resource *res = entry->res;
755 resource_size_t cpu_addr = res->start;
756 resource_size_t pci_addr = cpu_addr - entry->offset;
757 resource_size_t length = resource_size(res);
758 unsigned long port;
759
760 if (pci_register_io_range(fwnode, cpu_addr, length))
761 goto err;
762
763 port = pci_address_to_pio(cpu_addr);
764 if (port == (unsigned long)-1)
765 goto err;
766
767 res->start = port;
768 res->end = port + length - 1;
769 entry->offset = port - pci_addr;
770
771 if (pci_remap_iospace(res, cpu_addr) < 0)
772 goto err;
773
774 pr_info("Remapped I/O %pa to %pR\n", &cpu_addr, res);
775 return;
776err:
777 res->flags |= IORESOURCE_DISABLED;
778#endif
779}
780
781int acpi_pci_probe_root_resources(struct acpi_pci_root_info *info)
782{
783 int ret;
784 struct list_head *list = &info->resources;
785 struct acpi_device *device = info->bridge;
786 struct resource_entry *entry, *tmp;
787 unsigned long flags;
788
789 flags = IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT;
790 ret = acpi_dev_get_resources(device, list,
791 acpi_dev_filter_resource_type_cb,
792 (void *)flags);
793 if (ret < 0)
794 dev_warn(&device->dev,
795 "failed to parse _CRS method, error code %d\n", ret);
796 else if (ret == 0)
797 dev_dbg(&device->dev,
798 "no IO and memory resources present in _CRS\n");
799 else {
800 resource_list_for_each_entry_safe(entry, tmp, list) {
801 if (entry->res->flags & IORESOURCE_IO)
802 acpi_pci_root_remap_iospace(&device->fwnode,
803 entry);
804
805 if (entry->res->flags & IORESOURCE_DISABLED)
806 resource_list_destroy_entry(entry);
807 else
808 entry->res->name = info->name;
809 }
810 acpi_pci_root_validate_resources(&device->dev, list,
811 IORESOURCE_MEM);
812 acpi_pci_root_validate_resources(&device->dev, list,
813 IORESOURCE_IO);
814 }
815
816 return ret;
817}
818
819static void pci_acpi_root_add_resources(struct acpi_pci_root_info *info)
820{
821 struct resource_entry *entry, *tmp;
822 struct resource *res, *conflict, *root = NULL;
823
824 resource_list_for_each_entry_safe(entry, tmp, &info->resources) {
825 res = entry->res;
826 if (res->flags & IORESOURCE_MEM)
827 root = &iomem_resource;
828 else if (res->flags & IORESOURCE_IO)
829 root = &ioport_resource;
830 else
831 continue;
832
833 /*
834 * Some legacy x86 host bridge drivers use iomem_resource and
835 * ioport_resource as default resource pool, skip it.
836 */
837 if (res == root)
838 continue;
839
840 conflict = insert_resource_conflict(root, res);
841 if (conflict) {
842 dev_info(&info->bridge->dev,
843 "ignoring host bridge window %pR (conflicts with %s %pR)\n",
844 res, conflict->name, conflict);
845 resource_list_destroy_entry(entry);
846 }
847 }
848}
849
850static void __acpi_pci_root_release_info(struct acpi_pci_root_info *info)
851{
852 struct resource *res;
853 struct resource_entry *entry, *tmp;
854
855 if (!info)
856 return;
857
858 resource_list_for_each_entry_safe(entry, tmp, &info->resources) {
859 res = entry->res;
860 if (res->parent &&
861 (res->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
862 release_resource(res);
863 resource_list_destroy_entry(entry);
864 }
865
866 info->ops->release_info(info);
867}
868
869static void acpi_pci_root_release_info(struct pci_host_bridge *bridge)
870{
871 struct resource *res;
872 struct resource_entry *entry;
873
874 resource_list_for_each_entry(entry, &bridge->windows) {
875 res = entry->res;
876 if (res->flags & IORESOURCE_IO)
877 pci_unmap_iospace(res);
878 if (res->parent &&
879 (res->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
880 release_resource(res);
881 }
882 __acpi_pci_root_release_info(bridge->release_data);
883}
884
885struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root,
886 struct acpi_pci_root_ops *ops,
887 struct acpi_pci_root_info *info,
888 void *sysdata)
889{
890 int ret, busnum = root->secondary.start;
891 struct acpi_device *device = root->device;
892 int node = acpi_get_node(device->handle);
893 struct pci_bus *bus;
894 struct pci_host_bridge *host_bridge;
895
896 info->root = root;
897 info->bridge = device;
898 info->ops = ops;
899 INIT_LIST_HEAD(&info->resources);
900 snprintf(info->name, sizeof(info->name), "PCI Bus %04x:%02x",
901 root->segment, busnum);
902
903 if (ops->init_info && ops->init_info(info))
904 goto out_release_info;
905 if (ops->prepare_resources)
906 ret = ops->prepare_resources(info);
907 else
908 ret = acpi_pci_probe_root_resources(info);
909 if (ret < 0)
910 goto out_release_info;
911
912 pci_acpi_root_add_resources(info);
913 pci_add_resource(&info->resources, &root->secondary);
914 bus = pci_create_root_bus(NULL, busnum, ops->pci_ops,
915 sysdata, &info->resources);
916 if (!bus)
917 goto out_release_info;
918
919 host_bridge = to_pci_host_bridge(bus->bridge);
920 if (!(root->osc_control_set & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL))
921 host_bridge->native_pcie_hotplug = 0;
922 if (!(root->osc_control_set & OSC_PCI_SHPC_NATIVE_HP_CONTROL))
923 host_bridge->native_shpc_hotplug = 0;
924 if (!(root->osc_control_set & OSC_PCI_EXPRESS_AER_CONTROL))
925 host_bridge->native_aer = 0;
926 if (!(root->osc_control_set & OSC_PCI_EXPRESS_PME_CONTROL))
927 host_bridge->native_pme = 0;
928 if (!(root->osc_control_set & OSC_PCI_EXPRESS_LTR_CONTROL))
929 host_bridge->native_ltr = 0;
930
931 pci_scan_child_bus(bus);
932 pci_set_host_bridge_release(host_bridge, acpi_pci_root_release_info,
933 info);
934 if (node != NUMA_NO_NODE)
935 dev_printk(KERN_DEBUG, &bus->dev, "on NUMA node %d\n", node);
936 return bus;
937
938out_release_info:
939 __acpi_pci_root_release_info(info);
940 return NULL;
941}
942
943void __init acpi_pci_root_init(void)
944{
945 acpi_hest_init();
946 if (acpi_pci_disabled)
947 return;
948
949 pci_acpi_crs_quirks();
950 acpi_scan_add_handler_with_hotplug(&pci_root_handler, "pci_root");
951}
952