1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * pci_root.c - ACPI PCI Root Bridge Driver ($Revision: 40 $) |
4 | * |
5 | * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> |
6 | * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> |
7 | */ |
8 | |
9 | #define pr_fmt(fmt) "ACPI: " fmt |
10 | |
11 | #include <linux/kernel.h> |
12 | #include <linux/module.h> |
13 | #include <linux/init.h> |
14 | #include <linux/types.h> |
15 | #include <linux/mutex.h> |
16 | #include <linux/pm.h> |
17 | #include <linux/pm_runtime.h> |
18 | #include <linux/pci.h> |
19 | #include <linux/pci-acpi.h> |
20 | #include <linux/dmar.h> |
21 | #include <linux/acpi.h> |
22 | #include <linux/slab.h> |
23 | #include <linux/dmi.h> |
24 | #include <linux/platform_data/x86/apple.h> |
25 | #include "internal.h" |
26 | |
27 | #define ACPI_PCI_ROOT_CLASS "pci_bridge" |
28 | #define ACPI_PCI_ROOT_DEVICE_NAME "PCI Root Bridge" |
29 | static int acpi_pci_root_add(struct acpi_device *device, |
30 | const struct acpi_device_id *not_used); |
31 | static void acpi_pci_root_remove(struct acpi_device *device); |
32 | |
33 | static int acpi_pci_root_scan_dependent(struct acpi_device *adev) |
34 | { |
35 | acpiphp_check_host_bridge(adev); |
36 | return 0; |
37 | } |
38 | |
39 | #define ACPI_PCIE_REQ_SUPPORT (OSC_PCI_EXT_CONFIG_SUPPORT \ |
40 | | OSC_PCI_ASPM_SUPPORT \ |
41 | | OSC_PCI_CLOCK_PM_SUPPORT \ |
42 | | OSC_PCI_MSI_SUPPORT) |
43 | |
44 | static const struct acpi_device_id root_device_ids[] = { |
45 | {"PNP0A03" , 0}, |
46 | {"" , 0}, |
47 | }; |
48 | |
49 | static struct acpi_scan_handler pci_root_handler = { |
50 | .ids = root_device_ids, |
51 | .attach = acpi_pci_root_add, |
52 | .detach = acpi_pci_root_remove, |
53 | .hotplug = { |
54 | .enabled = true, |
55 | .scan_dependent = acpi_pci_root_scan_dependent, |
56 | }, |
57 | }; |
58 | |
59 | /** |
60 | * acpi_is_root_bridge - determine whether an ACPI CA node is a PCI root bridge |
61 | * @handle: the ACPI CA node in question. |
62 | * |
63 | * Note: we could make this API take a struct acpi_device * instead, but |
64 | * for now, it's more convenient to operate on an acpi_handle. |
65 | */ |
66 | int acpi_is_root_bridge(acpi_handle handle) |
67 | { |
68 | struct acpi_device *device = acpi_fetch_acpi_dev(handle); |
69 | int ret; |
70 | |
71 | if (!device) |
72 | return 0; |
73 | |
74 | ret = acpi_match_device_ids(device, ids: root_device_ids); |
75 | if (ret) |
76 | return 0; |
77 | else |
78 | return 1; |
79 | } |
80 | EXPORT_SYMBOL_GPL(acpi_is_root_bridge); |
81 | |
82 | static acpi_status |
83 | get_root_bridge_busnr_callback(struct acpi_resource *resource, void *data) |
84 | { |
85 | struct resource *res = data; |
86 | struct acpi_resource_address64 address; |
87 | acpi_status status; |
88 | |
89 | status = acpi_resource_to_address64(resource, out: &address); |
90 | if (ACPI_FAILURE(status)) |
91 | return AE_OK; |
92 | |
93 | if ((address.address.address_length > 0) && |
94 | (address.resource_type == ACPI_BUS_NUMBER_RANGE)) { |
95 | res->start = address.address.minimum; |
96 | res->end = address.address.minimum + address.address.address_length - 1; |
97 | } |
98 | |
99 | return AE_OK; |
100 | } |
101 | |
102 | static acpi_status try_get_root_bridge_busnr(acpi_handle handle, |
103 | struct resource *res) |
104 | { |
105 | acpi_status status; |
106 | |
107 | res->start = -1; |
108 | status = |
109 | acpi_walk_resources(device: handle, METHOD_NAME__CRS, |
110 | user_function: get_root_bridge_busnr_callback, context: res); |
111 | if (ACPI_FAILURE(status)) |
112 | return status; |
113 | if (res->start == -1) |
114 | return AE_ERROR; |
115 | return AE_OK; |
116 | } |
117 | |
118 | struct pci_osc_bit_struct { |
119 | u32 bit; |
120 | char *desc; |
121 | }; |
122 | |
123 | static struct pci_osc_bit_struct pci_osc_support_bit[] = { |
124 | { OSC_PCI_EXT_CONFIG_SUPPORT, "ExtendedConfig" }, |
125 | { OSC_PCI_ASPM_SUPPORT, "ASPM" }, |
126 | { OSC_PCI_CLOCK_PM_SUPPORT, "ClockPM" }, |
127 | { OSC_PCI_SEGMENT_GROUPS_SUPPORT, "Segments" }, |
128 | { OSC_PCI_MSI_SUPPORT, "MSI" }, |
129 | { OSC_PCI_EDR_SUPPORT, "EDR" }, |
130 | { OSC_PCI_HPX_TYPE_3_SUPPORT, "HPX-Type3" }, |
131 | }; |
132 | |
133 | static struct pci_osc_bit_struct pci_osc_control_bit[] = { |
134 | { OSC_PCI_EXPRESS_NATIVE_HP_CONTROL, "PCIeHotplug" }, |
135 | { OSC_PCI_SHPC_NATIVE_HP_CONTROL, "SHPCHotplug" }, |
136 | { OSC_PCI_EXPRESS_PME_CONTROL, "PME" }, |
137 | { OSC_PCI_EXPRESS_AER_CONTROL, "AER" }, |
138 | { OSC_PCI_EXPRESS_CAPABILITY_CONTROL, "PCIeCapability" }, |
139 | { OSC_PCI_EXPRESS_LTR_CONTROL, "LTR" }, |
140 | { OSC_PCI_EXPRESS_DPC_CONTROL, "DPC" }, |
141 | }; |
142 | |
143 | static struct pci_osc_bit_struct cxl_osc_support_bit[] = { |
144 | { OSC_CXL_1_1_PORT_REG_ACCESS_SUPPORT, "CXL11PortRegAccess" }, |
145 | { OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT, "CXL20PortDevRegAccess" }, |
146 | { OSC_CXL_PROTOCOL_ERR_REPORTING_SUPPORT, "CXLProtocolErrorReporting" }, |
147 | { OSC_CXL_NATIVE_HP_SUPPORT, "CXLNativeHotPlug" }, |
148 | }; |
149 | |
150 | static struct pci_osc_bit_struct cxl_osc_control_bit[] = { |
151 | { OSC_CXL_ERROR_REPORTING_CONTROL, "CXLMemErrorReporting" }, |
152 | }; |
153 | |
154 | static void decode_osc_bits(struct acpi_pci_root *root, char *msg, u32 word, |
155 | struct pci_osc_bit_struct *table, int size) |
156 | { |
157 | char buf[80]; |
158 | int i, len = 0; |
159 | struct pci_osc_bit_struct *entry; |
160 | |
161 | buf[0] = '\0'; |
162 | for (i = 0, entry = table; i < size; i++, entry++) |
163 | if (word & entry->bit) |
164 | len += scnprintf(buf: buf + len, size: sizeof(buf) - len, fmt: "%s%s" , |
165 | len ? " " : "" , entry->desc); |
166 | |
167 | dev_info(&root->device->dev, "_OSC: %s [%s]\n" , msg, buf); |
168 | } |
169 | |
170 | static void decode_osc_support(struct acpi_pci_root *root, char *msg, u32 word) |
171 | { |
172 | decode_osc_bits(root, msg, word, table: pci_osc_support_bit, |
173 | ARRAY_SIZE(pci_osc_support_bit)); |
174 | } |
175 | |
176 | static void decode_osc_control(struct acpi_pci_root *root, char *msg, u32 word) |
177 | { |
178 | decode_osc_bits(root, msg, word, table: pci_osc_control_bit, |
179 | ARRAY_SIZE(pci_osc_control_bit)); |
180 | } |
181 | |
182 | static void decode_cxl_osc_support(struct acpi_pci_root *root, char *msg, u32 word) |
183 | { |
184 | decode_osc_bits(root, msg, word, table: cxl_osc_support_bit, |
185 | ARRAY_SIZE(cxl_osc_support_bit)); |
186 | } |
187 | |
188 | static void decode_cxl_osc_control(struct acpi_pci_root *root, char *msg, u32 word) |
189 | { |
190 | decode_osc_bits(root, msg, word, table: cxl_osc_control_bit, |
191 | ARRAY_SIZE(cxl_osc_control_bit)); |
192 | } |
193 | |
194 | static inline bool is_pcie(struct acpi_pci_root *root) |
195 | { |
196 | return root->bridge_type == ACPI_BRIDGE_TYPE_PCIE; |
197 | } |
198 | |
199 | static inline bool is_cxl(struct acpi_pci_root *root) |
200 | { |
201 | return root->bridge_type == ACPI_BRIDGE_TYPE_CXL; |
202 | } |
203 | |
204 | static u8 pci_osc_uuid_str[] = "33DB4D5B-1FF7-401C-9657-7441C03DD766" ; |
205 | static u8 cxl_osc_uuid_str[] = "68F2D50B-C469-4d8A-BD3D-941A103FD3FC" ; |
206 | |
207 | static char *to_uuid(struct acpi_pci_root *root) |
208 | { |
209 | if (is_cxl(root)) |
210 | return cxl_osc_uuid_str; |
211 | return pci_osc_uuid_str; |
212 | } |
213 | |
214 | static int cap_length(struct acpi_pci_root *root) |
215 | { |
216 | if (is_cxl(root)) |
217 | return sizeof(u32) * OSC_CXL_CAPABILITY_DWORDS; |
218 | return sizeof(u32) * OSC_PCI_CAPABILITY_DWORDS; |
219 | } |
220 | |
221 | static acpi_status acpi_pci_run_osc(struct acpi_pci_root *root, |
222 | const u32 *capbuf, u32 *pci_control, |
223 | u32 *cxl_control) |
224 | { |
225 | struct acpi_osc_context context = { |
226 | .uuid_str = to_uuid(root), |
227 | .rev = 1, |
228 | .cap.length = cap_length(root), |
229 | .cap.pointer = (void *)capbuf, |
230 | }; |
231 | acpi_status status; |
232 | |
233 | status = acpi_run_osc(handle: root->device->handle, context: &context); |
234 | if (ACPI_SUCCESS(status)) { |
235 | *pci_control = acpi_osc_ctx_get_pci_control(context: &context); |
236 | if (is_cxl(root)) |
237 | *cxl_control = acpi_osc_ctx_get_cxl_control(context: &context); |
238 | kfree(objp: context.ret.pointer); |
239 | } |
240 | return status; |
241 | } |
242 | |
243 | static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root, u32 support, |
244 | u32 *control, u32 cxl_support, |
245 | u32 *cxl_control) |
246 | { |
247 | acpi_status status; |
248 | u32 pci_result, cxl_result, capbuf[OSC_CXL_CAPABILITY_DWORDS]; |
249 | |
250 | support |= root->osc_support_set; |
251 | |
252 | capbuf[OSC_QUERY_DWORD] = OSC_QUERY_ENABLE; |
253 | capbuf[OSC_SUPPORT_DWORD] = support; |
254 | capbuf[OSC_CONTROL_DWORD] = *control | root->osc_control_set; |
255 | |
256 | if (is_cxl(root)) { |
257 | cxl_support |= root->osc_ext_support_set; |
258 | capbuf[OSC_EXT_SUPPORT_DWORD] = cxl_support; |
259 | capbuf[OSC_EXT_CONTROL_DWORD] = *cxl_control | root->osc_ext_control_set; |
260 | } |
261 | |
262 | retry: |
263 | status = acpi_pci_run_osc(root, capbuf, pci_control: &pci_result, cxl_control: &cxl_result); |
264 | if (ACPI_SUCCESS(status)) { |
265 | root->osc_support_set = support; |
266 | *control = pci_result; |
267 | if (is_cxl(root)) { |
268 | root->osc_ext_support_set = cxl_support; |
269 | *cxl_control = cxl_result; |
270 | } |
271 | } else if (is_cxl(root)) { |
272 | /* |
273 | * CXL _OSC is optional on CXL 1.1 hosts. Fall back to PCIe _OSC |
274 | * upon any failure using CXL _OSC. |
275 | */ |
276 | root->bridge_type = ACPI_BRIDGE_TYPE_PCIE; |
277 | goto retry; |
278 | } |
279 | return status; |
280 | } |
281 | |
282 | struct acpi_pci_root *acpi_pci_find_root(acpi_handle handle) |
283 | { |
284 | struct acpi_device *device = acpi_fetch_acpi_dev(handle); |
285 | struct acpi_pci_root *root; |
286 | |
287 | if (!device || acpi_match_device_ids(device, ids: root_device_ids)) |
288 | return NULL; |
289 | |
290 | root = acpi_driver_data(d: device); |
291 | |
292 | return root; |
293 | } |
294 | EXPORT_SYMBOL_GPL(acpi_pci_find_root); |
295 | |
296 | struct acpi_handle_node { |
297 | struct list_head node; |
298 | acpi_handle handle; |
299 | }; |
300 | |
301 | /** |
302 | * acpi_get_pci_dev - convert ACPI CA handle to struct pci_dev |
303 | * @handle: the handle in question |
304 | * |
305 | * Given an ACPI CA handle, the desired PCI device is located in the |
306 | * list of PCI devices. |
307 | * |
308 | * If the device is found, its reference count is increased and this |
309 | * function returns a pointer to its data structure. The caller must |
310 | * decrement the reference count by calling pci_dev_put(). |
311 | * If no device is found, %NULL is returned. |
312 | */ |
313 | struct pci_dev *acpi_get_pci_dev(acpi_handle handle) |
314 | { |
315 | struct acpi_device *adev = acpi_fetch_acpi_dev(handle); |
316 | struct acpi_device_physical_node *pn; |
317 | struct pci_dev *pci_dev = NULL; |
318 | |
319 | if (!adev) |
320 | return NULL; |
321 | |
322 | mutex_lock(&adev->physical_node_lock); |
323 | |
324 | list_for_each_entry(pn, &adev->physical_node_list, node) { |
325 | if (dev_is_pci(pn->dev)) { |
326 | get_device(dev: pn->dev); |
327 | pci_dev = to_pci_dev(pn->dev); |
328 | break; |
329 | } |
330 | } |
331 | |
332 | mutex_unlock(lock: &adev->physical_node_lock); |
333 | |
334 | return pci_dev; |
335 | } |
336 | EXPORT_SYMBOL_GPL(acpi_get_pci_dev); |
337 | |
338 | /** |
339 | * acpi_pci_osc_control_set - Request control of PCI root _OSC features. |
340 | * @handle: ACPI handle of a PCI root bridge (or PCIe Root Complex). |
341 | * @mask: Mask of _OSC bits to request control of, place to store control mask. |
342 | * @support: _OSC supported capability. |
343 | * @cxl_mask: Mask of CXL _OSC control bits, place to store control mask. |
344 | * @cxl_support: CXL _OSC supported capability. |
345 | * |
346 | * Run _OSC query for @mask and if that is successful, compare the returned |
347 | * mask of control bits with @req. If all of the @req bits are set in the |
348 | * returned mask, run _OSC request for it. |
349 | * |
350 | * The variable at the @mask address may be modified regardless of whether or |
351 | * not the function returns success. On success it will contain the mask of |
352 | * _OSC bits the BIOS has granted control of, but its contents are meaningless |
353 | * on failure. |
354 | **/ |
355 | static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, |
356 | u32 support, u32 *cxl_mask, |
357 | u32 cxl_support) |
358 | { |
359 | u32 req = OSC_PCI_EXPRESS_CAPABILITY_CONTROL; |
360 | struct acpi_pci_root *root; |
361 | acpi_status status; |
362 | u32 ctrl, cxl_ctrl = 0, capbuf[OSC_CXL_CAPABILITY_DWORDS]; |
363 | |
364 | if (!mask) |
365 | return AE_BAD_PARAMETER; |
366 | |
367 | root = acpi_pci_find_root(handle); |
368 | if (!root) |
369 | return AE_NOT_EXIST; |
370 | |
371 | ctrl = *mask; |
372 | *mask |= root->osc_control_set; |
373 | |
374 | if (is_cxl(root)) { |
375 | cxl_ctrl = *cxl_mask; |
376 | *cxl_mask |= root->osc_ext_control_set; |
377 | } |
378 | |
379 | /* Need to check the available controls bits before requesting them. */ |
380 | do { |
381 | u32 pci_missing = 0, cxl_missing = 0; |
382 | |
383 | status = acpi_pci_query_osc(root, support, control: mask, cxl_support, |
384 | cxl_control: cxl_mask); |
385 | if (ACPI_FAILURE(status)) |
386 | return status; |
387 | if (is_cxl(root)) { |
388 | if (ctrl == *mask && cxl_ctrl == *cxl_mask) |
389 | break; |
390 | pci_missing = ctrl & ~(*mask); |
391 | cxl_missing = cxl_ctrl & ~(*cxl_mask); |
392 | } else { |
393 | if (ctrl == *mask) |
394 | break; |
395 | pci_missing = ctrl & ~(*mask); |
396 | } |
397 | if (pci_missing) |
398 | decode_osc_control(root, msg: "platform does not support" , |
399 | word: pci_missing); |
400 | if (cxl_missing) |
401 | decode_cxl_osc_control(root, msg: "CXL platform does not support" , |
402 | word: cxl_missing); |
403 | ctrl = *mask; |
404 | cxl_ctrl = *cxl_mask; |
405 | } while (*mask || *cxl_mask); |
406 | |
407 | /* No need to request _OSC if the control was already granted. */ |
408 | if ((root->osc_control_set & ctrl) == ctrl && |
409 | (root->osc_ext_control_set & cxl_ctrl) == cxl_ctrl) |
410 | return AE_OK; |
411 | |
412 | if ((ctrl & req) != req) { |
413 | decode_osc_control(root, msg: "not requesting control; platform does not support" , |
414 | word: req & ~(ctrl)); |
415 | return AE_SUPPORT; |
416 | } |
417 | |
418 | capbuf[OSC_QUERY_DWORD] = 0; |
419 | capbuf[OSC_SUPPORT_DWORD] = root->osc_support_set; |
420 | capbuf[OSC_CONTROL_DWORD] = ctrl; |
421 | if (is_cxl(root)) { |
422 | capbuf[OSC_EXT_SUPPORT_DWORD] = root->osc_ext_support_set; |
423 | capbuf[OSC_EXT_CONTROL_DWORD] = cxl_ctrl; |
424 | } |
425 | |
426 | status = acpi_pci_run_osc(root, capbuf, pci_control: mask, cxl_control: cxl_mask); |
427 | if (ACPI_FAILURE(status)) |
428 | return status; |
429 | |
430 | root->osc_control_set = *mask; |
431 | root->osc_ext_control_set = *cxl_mask; |
432 | return AE_OK; |
433 | } |
434 | |
435 | static u32 calculate_support(void) |
436 | { |
437 | u32 support; |
438 | |
439 | /* |
440 | * All supported architectures that use ACPI have support for |
441 | * PCI domains, so we indicate this in _OSC support capabilities. |
442 | */ |
443 | support = OSC_PCI_SEGMENT_GROUPS_SUPPORT; |
444 | support |= OSC_PCI_HPX_TYPE_3_SUPPORT; |
445 | if (pci_ext_cfg_avail()) |
446 | support |= OSC_PCI_EXT_CONFIG_SUPPORT; |
447 | if (pcie_aspm_support_enabled()) |
448 | support |= OSC_PCI_ASPM_SUPPORT | OSC_PCI_CLOCK_PM_SUPPORT; |
449 | if (pci_msi_enabled()) |
450 | support |= OSC_PCI_MSI_SUPPORT; |
451 | if (IS_ENABLED(CONFIG_PCIE_EDR)) |
452 | support |= OSC_PCI_EDR_SUPPORT; |
453 | |
454 | return support; |
455 | } |
456 | |
457 | /* |
458 | * Background on hotplug support, and making it depend on only |
459 | * CONFIG_HOTPLUG_PCI_PCIE vs. also considering CONFIG_MEMORY_HOTPLUG: |
460 | * |
461 | * CONFIG_ACPI_HOTPLUG_MEMORY does depend on CONFIG_MEMORY_HOTPLUG, but |
462 | * there is no existing _OSC for memory hotplug support. The reason is that |
463 | * ACPI memory hotplug requires the OS to acknowledge / coordinate with |
464 | * memory plug events via a scan handler. On the CXL side the equivalent |
465 | * would be if Linux supported the Mechanical Retention Lock [1], or |
466 | * otherwise had some coordination for the driver of a PCI device |
467 | * undergoing hotplug to be consulted on whether the hotplug should |
468 | * proceed or not. |
469 | * |
470 | * The concern is that if Linux says no to supporting CXL hotplug then |
471 | * the BIOS may say no to giving the OS hotplug control of any other PCIe |
472 | * device. So the question here is not whether hotplug is enabled, it's |
473 | * whether it is handled natively by the at all OS, and if |
474 | * CONFIG_HOTPLUG_PCI_PCIE is enabled then the answer is "yes". |
475 | * |
476 | * Otherwise, the plan for CXL coordinated remove, since the kernel does |
477 | * not support blocking hotplug, is to require the memory device to be |
478 | * disabled before hotplug is attempted. When CONFIG_MEMORY_HOTPLUG is |
479 | * disabled that step will fail and the remove attempt cancelled by the |
480 | * user. If that is not honored and the card is removed anyway then it |
481 | * does not matter if CONFIG_MEMORY_HOTPLUG is enabled or not, it will |
482 | * cause a crash and other badness. |
483 | * |
484 | * Therefore, just say yes to CXL hotplug and require removal to |
485 | * be coordinated by userspace unless and until the kernel grows better |
486 | * mechanisms for doing "managed" removal of devices in consultation with |
487 | * the driver. |
488 | * |
489 | * [1]: https://lore.kernel.org/all/20201122014203.4706-1-ashok.raj@intel.com/ |
490 | */ |
491 | static u32 calculate_cxl_support(void) |
492 | { |
493 | u32 support; |
494 | |
495 | support = OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT; |
496 | support |= OSC_CXL_1_1_PORT_REG_ACCESS_SUPPORT; |
497 | if (pci_aer_available()) |
498 | support |= OSC_CXL_PROTOCOL_ERR_REPORTING_SUPPORT; |
499 | if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE)) |
500 | support |= OSC_CXL_NATIVE_HP_SUPPORT; |
501 | |
502 | return support; |
503 | } |
504 | |
505 | static u32 calculate_control(void) |
506 | { |
507 | u32 control; |
508 | |
509 | control = OSC_PCI_EXPRESS_CAPABILITY_CONTROL |
510 | | OSC_PCI_EXPRESS_PME_CONTROL; |
511 | |
512 | if (IS_ENABLED(CONFIG_PCIEASPM)) |
513 | control |= OSC_PCI_EXPRESS_LTR_CONTROL; |
514 | |
515 | if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE)) |
516 | control |= OSC_PCI_EXPRESS_NATIVE_HP_CONTROL; |
517 | |
518 | if (IS_ENABLED(CONFIG_HOTPLUG_PCI_SHPC)) |
519 | control |= OSC_PCI_SHPC_NATIVE_HP_CONTROL; |
520 | |
521 | if (pci_aer_available()) |
522 | control |= OSC_PCI_EXPRESS_AER_CONTROL; |
523 | |
524 | /* |
525 | * Per the Downstream Port Containment Related Enhancements ECN to |
526 | * the PCI Firmware Spec, r3.2, sec 4.5.1, table 4-5, |
527 | * OSC_PCI_EXPRESS_DPC_CONTROL indicates the OS supports both DPC |
528 | * and EDR. |
529 | */ |
530 | if (IS_ENABLED(CONFIG_PCIE_DPC) && IS_ENABLED(CONFIG_PCIE_EDR)) |
531 | control |= OSC_PCI_EXPRESS_DPC_CONTROL; |
532 | |
533 | return control; |
534 | } |
535 | |
536 | static u32 calculate_cxl_control(void) |
537 | { |
538 | u32 control = 0; |
539 | |
540 | if (IS_ENABLED(CONFIG_MEMORY_FAILURE)) |
541 | control |= OSC_CXL_ERROR_REPORTING_CONTROL; |
542 | |
543 | return control; |
544 | } |
545 | |
546 | static bool os_control_query_checks(struct acpi_pci_root *root, u32 support) |
547 | { |
548 | struct acpi_device *device = root->device; |
549 | |
550 | if (pcie_ports_disabled) { |
551 | dev_info(&device->dev, "PCIe port services disabled; not requesting _OSC control\n" ); |
552 | return false; |
553 | } |
554 | |
555 | if ((support & ACPI_PCIE_REQ_SUPPORT) != ACPI_PCIE_REQ_SUPPORT) { |
556 | decode_osc_support(root, msg: "not requesting OS control; OS requires" , |
557 | ACPI_PCIE_REQ_SUPPORT); |
558 | return false; |
559 | } |
560 | |
561 | return true; |
562 | } |
563 | |
564 | static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm) |
565 | { |
566 | u32 support, control = 0, requested = 0; |
567 | u32 cxl_support = 0, cxl_control = 0, cxl_requested = 0; |
568 | acpi_status status; |
569 | struct acpi_device *device = root->device; |
570 | acpi_handle handle = device->handle; |
571 | |
572 | /* |
573 | * Apple always return failure on _OSC calls when _OSI("Darwin") has |
574 | * been called successfully. We know the feature set supported by the |
575 | * platform, so avoid calling _OSC at all |
576 | */ |
577 | if (x86_apple_machine) { |
578 | root->osc_control_set = ~OSC_PCI_EXPRESS_PME_CONTROL; |
579 | decode_osc_control(root, msg: "OS assumes control of" , |
580 | word: root->osc_control_set); |
581 | return; |
582 | } |
583 | |
584 | support = calculate_support(); |
585 | |
586 | decode_osc_support(root, msg: "OS supports" , word: support); |
587 | |
588 | if (os_control_query_checks(root, support)) |
589 | requested = control = calculate_control(); |
590 | |
591 | if (is_cxl(root)) { |
592 | cxl_support = calculate_cxl_support(); |
593 | decode_cxl_osc_support(root, msg: "OS supports" , word: cxl_support); |
594 | cxl_requested = cxl_control = calculate_cxl_control(); |
595 | } |
596 | |
597 | status = acpi_pci_osc_control_set(handle, mask: &control, support, |
598 | cxl_mask: &cxl_control, cxl_support); |
599 | if (ACPI_SUCCESS(status)) { |
600 | if (control) |
601 | decode_osc_control(root, msg: "OS now controls" , word: control); |
602 | if (cxl_control) |
603 | decode_cxl_osc_control(root, msg: "OS now controls" , |
604 | word: cxl_control); |
605 | |
606 | if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) { |
607 | /* |
608 | * We have ASPM control, but the FADT indicates that |
609 | * it's unsupported. Leave existing configuration |
610 | * intact and prevent the OS from touching it. |
611 | */ |
612 | dev_info(&device->dev, "FADT indicates ASPM is unsupported, using BIOS configuration\n" ); |
613 | *no_aspm = 1; |
614 | } |
615 | } else { |
616 | /* |
617 | * We want to disable ASPM here, but aspm_disabled |
618 | * needs to remain in its state from boot so that we |
619 | * properly handle PCIe 1.1 devices. So we set this |
620 | * flag here, to defer the action until after the ACPI |
621 | * root scan. |
622 | */ |
623 | *no_aspm = 1; |
624 | |
625 | /* _OSC is optional for PCI host bridges */ |
626 | if (status == AE_NOT_FOUND && !is_pcie(root)) |
627 | return; |
628 | |
629 | if (control) { |
630 | decode_osc_control(root, msg: "OS requested" , word: requested); |
631 | decode_osc_control(root, msg: "platform willing to grant" , word: control); |
632 | } |
633 | if (cxl_control) { |
634 | decode_cxl_osc_control(root, msg: "OS requested" , word: cxl_requested); |
635 | decode_cxl_osc_control(root, msg: "platform willing to grant" , |
636 | word: cxl_control); |
637 | } |
638 | |
639 | dev_info(&device->dev, "_OSC: platform retains control of PCIe features (%s)\n" , |
640 | acpi_format_exception(status)); |
641 | } |
642 | } |
643 | |
644 | static int acpi_pci_root_add(struct acpi_device *device, |
645 | const struct acpi_device_id *not_used) |
646 | { |
647 | unsigned long long segment, bus; |
648 | acpi_status status; |
649 | int result; |
650 | struct acpi_pci_root *root; |
651 | acpi_handle handle = device->handle; |
652 | int no_aspm = 0; |
653 | bool hotadd = system_state == SYSTEM_RUNNING; |
654 | const char *acpi_hid; |
655 | |
656 | root = kzalloc(size: sizeof(struct acpi_pci_root), GFP_KERNEL); |
657 | if (!root) |
658 | return -ENOMEM; |
659 | |
660 | segment = 0; |
661 | status = acpi_evaluate_integer(handle, METHOD_NAME__SEG, NULL, |
662 | data: &segment); |
663 | if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) { |
664 | dev_err(&device->dev, "can't evaluate _SEG\n" ); |
665 | result = -ENODEV; |
666 | goto end; |
667 | } |
668 | |
669 | /* Check _CRS first, then _BBN. If no _BBN, default to zero. */ |
670 | root->secondary.flags = IORESOURCE_BUS; |
671 | status = try_get_root_bridge_busnr(handle, res: &root->secondary); |
672 | if (ACPI_FAILURE(status)) { |
673 | /* |
674 | * We need both the start and end of the downstream bus range |
675 | * to interpret _CBA (MMCONFIG base address), so it really is |
676 | * supposed to be in _CRS. If we don't find it there, all we |
677 | * can do is assume [_BBN-0xFF] or [0-0xFF]. |
678 | */ |
679 | root->secondary.end = 0xFF; |
680 | dev_warn(&device->dev, |
681 | FW_BUG "no secondary bus range in _CRS\n" ); |
682 | status = acpi_evaluate_integer(handle, METHOD_NAME__BBN, |
683 | NULL, data: &bus); |
684 | if (ACPI_SUCCESS(status)) |
685 | root->secondary.start = bus; |
686 | else if (status == AE_NOT_FOUND) |
687 | root->secondary.start = 0; |
688 | else { |
689 | dev_err(&device->dev, "can't evaluate _BBN\n" ); |
690 | result = -ENODEV; |
691 | goto end; |
692 | } |
693 | } |
694 | |
695 | root->device = device; |
696 | root->segment = segment & 0xFFFF; |
697 | strcpy(acpi_device_name(device), ACPI_PCI_ROOT_DEVICE_NAME); |
698 | strcpy(acpi_device_class(device), ACPI_PCI_ROOT_CLASS); |
699 | device->driver_data = root; |
700 | |
701 | if (hotadd && dmar_device_add(handle)) { |
702 | result = -ENXIO; |
703 | goto end; |
704 | } |
705 | |
706 | pr_info("%s [%s] (domain %04x %pR)\n" , |
707 | acpi_device_name(device), acpi_device_bid(device), |
708 | root->segment, &root->secondary); |
709 | |
710 | root->mcfg_addr = acpi_pci_root_get_mcfg_addr(handle); |
711 | |
712 | acpi_hid = acpi_device_hid(device: root->device); |
713 | if (strcmp(acpi_hid, "PNP0A08" ) == 0) |
714 | root->bridge_type = ACPI_BRIDGE_TYPE_PCIE; |
715 | else if (strcmp(acpi_hid, "ACPI0016" ) == 0) |
716 | root->bridge_type = ACPI_BRIDGE_TYPE_CXL; |
717 | else |
718 | dev_dbg(&device->dev, "Assuming non-PCIe host bridge\n" ); |
719 | |
720 | negotiate_os_control(root, no_aspm: &no_aspm); |
721 | |
722 | /* |
723 | * TBD: Need PCI interface for enumeration/configuration of roots. |
724 | */ |
725 | |
726 | /* |
727 | * Scan the Root Bridge |
728 | * -------------------- |
729 | * Must do this prior to any attempt to bind the root device, as the |
730 | * PCI namespace does not get created until this call is made (and |
731 | * thus the root bridge's pci_dev does not exist). |
732 | */ |
733 | root->bus = pci_acpi_scan_root(root); |
734 | if (!root->bus) { |
735 | dev_err(&device->dev, |
736 | "Bus %04x:%02x not present in PCI namespace\n" , |
737 | root->segment, (unsigned int)root->secondary.start); |
738 | device->driver_data = NULL; |
739 | result = -ENODEV; |
740 | goto remove_dmar; |
741 | } |
742 | |
743 | if (no_aspm) |
744 | pcie_no_aspm(); |
745 | |
746 | pci_acpi_add_bus_pm_notifier(dev: device); |
747 | device_set_wakeup_capable(dev: root->bus->bridge, capable: device->wakeup.flags.valid); |
748 | |
749 | if (hotadd) { |
750 | pcibios_resource_survey_bus(bus: root->bus); |
751 | pci_assign_unassigned_root_bus_resources(bus: root->bus); |
752 | /* |
753 | * This is only called for the hotadd case. For the boot-time |
754 | * case, we need to wait until after PCI initialization in |
755 | * order to deal with IOAPICs mapped in on a PCI BAR. |
756 | * |
757 | * This is currently x86-specific, because acpi_ioapic_add() |
758 | * is an empty function without CONFIG_ACPI_HOTPLUG_IOAPIC. |
759 | * And CONFIG_ACPI_HOTPLUG_IOAPIC depends on CONFIG_X86_IO_APIC |
760 | * (see drivers/acpi/Kconfig). |
761 | */ |
762 | acpi_ioapic_add(root: root->device->handle); |
763 | } |
764 | |
765 | pci_lock_rescan_remove(); |
766 | pci_bus_add_devices(bus: root->bus); |
767 | pci_unlock_rescan_remove(); |
768 | return 1; |
769 | |
770 | remove_dmar: |
771 | if (hotadd) |
772 | dmar_device_remove(handle); |
773 | end: |
774 | kfree(objp: root); |
775 | return result; |
776 | } |
777 | |
778 | static void acpi_pci_root_remove(struct acpi_device *device) |
779 | { |
780 | struct acpi_pci_root *root = acpi_driver_data(d: device); |
781 | |
782 | pci_lock_rescan_remove(); |
783 | |
784 | pci_stop_root_bus(bus: root->bus); |
785 | |
786 | pci_ioapic_remove(root); |
787 | device_set_wakeup_capable(dev: root->bus->bridge, capable: false); |
788 | pci_acpi_remove_bus_pm_notifier(dev: device); |
789 | |
790 | pci_remove_root_bus(bus: root->bus); |
791 | WARN_ON(acpi_ioapic_remove(root)); |
792 | |
793 | dmar_device_remove(handle: device->handle); |
794 | |
795 | pci_unlock_rescan_remove(); |
796 | |
797 | kfree(objp: root); |
798 | } |
799 | |
800 | /* |
801 | * Following code to support acpi_pci_root_create() is copied from |
802 | * arch/x86/pci/acpi.c and modified so it could be reused by x86, IA64 |
803 | * and ARM64. |
804 | */ |
805 | static void acpi_pci_root_validate_resources(struct device *dev, |
806 | struct list_head *resources, |
807 | unsigned long type) |
808 | { |
809 | LIST_HEAD(list); |
810 | struct resource *res1, *res2, *root = NULL; |
811 | struct resource_entry *tmp, *entry, *entry2; |
812 | |
813 | BUG_ON((type & (IORESOURCE_MEM | IORESOURCE_IO)) == 0); |
814 | root = (type & IORESOURCE_MEM) ? &iomem_resource : &ioport_resource; |
815 | |
816 | list_splice_init(list: resources, head: &list); |
817 | resource_list_for_each_entry_safe(entry, tmp, &list) { |
818 | bool free = false; |
819 | resource_size_t end; |
820 | |
821 | res1 = entry->res; |
822 | if (!(res1->flags & type)) |
823 | goto next; |
824 | |
825 | /* Exclude non-addressable range or non-addressable portion */ |
826 | end = min(res1->end, root->end); |
827 | if (end <= res1->start) { |
828 | dev_info(dev, "host bridge window %pR (ignored, not CPU addressable)\n" , |
829 | res1); |
830 | free = true; |
831 | goto next; |
832 | } else if (res1->end != end) { |
833 | dev_info(dev, "host bridge window %pR ([%#llx-%#llx] ignored, not CPU addressable)\n" , |
834 | res1, (unsigned long long)end + 1, |
835 | (unsigned long long)res1->end); |
836 | res1->end = end; |
837 | } |
838 | |
839 | resource_list_for_each_entry(entry2, resources) { |
840 | res2 = entry2->res; |
841 | if (!(res2->flags & type)) |
842 | continue; |
843 | |
844 | /* |
845 | * I don't like throwing away windows because then |
846 | * our resources no longer match the ACPI _CRS, but |
847 | * the kernel resource tree doesn't allow overlaps. |
848 | */ |
849 | if (resource_union(r1: res1, r2: res2, r: res2)) { |
850 | dev_info(dev, "host bridge window expanded to %pR; %pR ignored\n" , |
851 | res2, res1); |
852 | free = true; |
853 | goto next; |
854 | } |
855 | } |
856 | |
857 | next: |
858 | resource_list_del(entry); |
859 | if (free) |
860 | resource_list_free_entry(entry); |
861 | else |
862 | resource_list_add_tail(entry, head: resources); |
863 | } |
864 | } |
865 | |
866 | static void acpi_pci_root_remap_iospace(struct fwnode_handle *fwnode, |
867 | struct resource_entry *entry) |
868 | { |
869 | #ifdef PCI_IOBASE |
870 | struct resource *res = entry->res; |
871 | resource_size_t cpu_addr = res->start; |
872 | resource_size_t pci_addr = cpu_addr - entry->offset; |
873 | resource_size_t length = resource_size(res); |
874 | unsigned long port; |
875 | |
876 | if (pci_register_io_range(fwnode, cpu_addr, length)) |
877 | goto err; |
878 | |
879 | port = pci_address_to_pio(cpu_addr); |
880 | if (port == (unsigned long)-1) |
881 | goto err; |
882 | |
883 | res->start = port; |
884 | res->end = port + length - 1; |
885 | entry->offset = port - pci_addr; |
886 | |
887 | if (pci_remap_iospace(res, cpu_addr) < 0) |
888 | goto err; |
889 | |
890 | pr_info("Remapped I/O %pa to %pR\n" , &cpu_addr, res); |
891 | return; |
892 | err: |
893 | res->flags |= IORESOURCE_DISABLED; |
894 | #endif |
895 | } |
896 | |
897 | int acpi_pci_probe_root_resources(struct acpi_pci_root_info *info) |
898 | { |
899 | int ret; |
900 | struct list_head *list = &info->resources; |
901 | struct acpi_device *device = info->bridge; |
902 | struct resource_entry *entry, *tmp; |
903 | unsigned long flags; |
904 | |
905 | flags = IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT; |
906 | ret = acpi_dev_get_resources(adev: device, list, |
907 | preproc: acpi_dev_filter_resource_type_cb, |
908 | preproc_data: (void *)flags); |
909 | if (ret < 0) |
910 | dev_warn(&device->dev, |
911 | "failed to parse _CRS method, error code %d\n" , ret); |
912 | else if (ret == 0) |
913 | dev_dbg(&device->dev, |
914 | "no IO and memory resources present in _CRS\n" ); |
915 | else { |
916 | resource_list_for_each_entry_safe(entry, tmp, list) { |
917 | if (entry->res->flags & IORESOURCE_IO) |
918 | acpi_pci_root_remap_iospace(fwnode: &device->fwnode, |
919 | entry); |
920 | |
921 | if (entry->res->flags & IORESOURCE_DISABLED) |
922 | resource_list_destroy_entry(entry); |
923 | else |
924 | entry->res->name = info->name; |
925 | } |
926 | acpi_pci_root_validate_resources(dev: &device->dev, resources: list, |
927 | IORESOURCE_MEM); |
928 | acpi_pci_root_validate_resources(dev: &device->dev, resources: list, |
929 | IORESOURCE_IO); |
930 | } |
931 | |
932 | return ret; |
933 | } |
934 | |
935 | static void pci_acpi_root_add_resources(struct acpi_pci_root_info *info) |
936 | { |
937 | struct resource_entry *entry, *tmp; |
938 | struct resource *res, *conflict, *root = NULL; |
939 | |
940 | resource_list_for_each_entry_safe(entry, tmp, &info->resources) { |
941 | res = entry->res; |
942 | if (res->flags & IORESOURCE_MEM) |
943 | root = &iomem_resource; |
944 | else if (res->flags & IORESOURCE_IO) |
945 | root = &ioport_resource; |
946 | else |
947 | continue; |
948 | |
949 | /* |
950 | * Some legacy x86 host bridge drivers use iomem_resource and |
951 | * ioport_resource as default resource pool, skip it. |
952 | */ |
953 | if (res == root) |
954 | continue; |
955 | |
956 | conflict = insert_resource_conflict(parent: root, new: res); |
957 | if (conflict) { |
958 | dev_info(&info->bridge->dev, |
959 | "ignoring host bridge window %pR (conflicts with %s %pR)\n" , |
960 | res, conflict->name, conflict); |
961 | resource_list_destroy_entry(entry); |
962 | } |
963 | } |
964 | } |
965 | |
966 | static void __acpi_pci_root_release_info(struct acpi_pci_root_info *info) |
967 | { |
968 | struct resource *res; |
969 | struct resource_entry *entry, *tmp; |
970 | |
971 | if (!info) |
972 | return; |
973 | |
974 | resource_list_for_each_entry_safe(entry, tmp, &info->resources) { |
975 | res = entry->res; |
976 | if (res->parent && |
977 | (res->flags & (IORESOURCE_MEM | IORESOURCE_IO))) |
978 | release_resource(new: res); |
979 | resource_list_destroy_entry(entry); |
980 | } |
981 | |
982 | info->ops->release_info(info); |
983 | } |
984 | |
985 | static void acpi_pci_root_release_info(struct pci_host_bridge *bridge) |
986 | { |
987 | struct resource *res; |
988 | struct resource_entry *entry; |
989 | |
990 | resource_list_for_each_entry(entry, &bridge->windows) { |
991 | res = entry->res; |
992 | if (res->flags & IORESOURCE_IO) |
993 | pci_unmap_iospace(res); |
994 | if (res->parent && |
995 | (res->flags & (IORESOURCE_MEM | IORESOURCE_IO))) |
996 | release_resource(new: res); |
997 | } |
998 | __acpi_pci_root_release_info(info: bridge->release_data); |
999 | } |
1000 | |
1001 | struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root, |
1002 | struct acpi_pci_root_ops *ops, |
1003 | struct acpi_pci_root_info *info, |
1004 | void *sysdata) |
1005 | { |
1006 | int ret, busnum = root->secondary.start; |
1007 | struct acpi_device *device = root->device; |
1008 | int node = acpi_get_node(handle: device->handle); |
1009 | struct pci_bus *bus; |
1010 | struct pci_host_bridge *host_bridge; |
1011 | union acpi_object *obj; |
1012 | |
1013 | info->root = root; |
1014 | info->bridge = device; |
1015 | info->ops = ops; |
1016 | INIT_LIST_HEAD(list: &info->resources); |
1017 | snprintf(buf: info->name, size: sizeof(info->name), fmt: "PCI Bus %04x:%02x" , |
1018 | root->segment, busnum); |
1019 | |
1020 | if (ops->init_info && ops->init_info(info)) |
1021 | goto out_release_info; |
1022 | if (ops->prepare_resources) |
1023 | ret = ops->prepare_resources(info); |
1024 | else |
1025 | ret = acpi_pci_probe_root_resources(info); |
1026 | if (ret < 0) |
1027 | goto out_release_info; |
1028 | |
1029 | pci_acpi_root_add_resources(info); |
1030 | pci_add_resource(resources: &info->resources, res: &root->secondary); |
1031 | bus = pci_create_root_bus(NULL, bus: busnum, ops: ops->pci_ops, |
1032 | sysdata, resources: &info->resources); |
1033 | if (!bus) |
1034 | goto out_release_info; |
1035 | |
1036 | host_bridge = to_pci_host_bridge(bus->bridge); |
1037 | if (!(root->osc_control_set & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL)) |
1038 | host_bridge->native_pcie_hotplug = 0; |
1039 | if (!(root->osc_control_set & OSC_PCI_SHPC_NATIVE_HP_CONTROL)) |
1040 | host_bridge->native_shpc_hotplug = 0; |
1041 | if (!(root->osc_control_set & OSC_PCI_EXPRESS_AER_CONTROL)) |
1042 | host_bridge->native_aer = 0; |
1043 | if (!(root->osc_control_set & OSC_PCI_EXPRESS_PME_CONTROL)) |
1044 | host_bridge->native_pme = 0; |
1045 | if (!(root->osc_control_set & OSC_PCI_EXPRESS_LTR_CONTROL)) |
1046 | host_bridge->native_ltr = 0; |
1047 | if (!(root->osc_control_set & OSC_PCI_EXPRESS_DPC_CONTROL)) |
1048 | host_bridge->native_dpc = 0; |
1049 | |
1050 | if (!(root->osc_ext_control_set & OSC_CXL_ERROR_REPORTING_CONTROL)) |
1051 | host_bridge->native_cxl_error = 0; |
1052 | |
1053 | /* |
1054 | * Evaluate the "PCI Boot Configuration" _DSM Function. If it |
1055 | * exists and returns 0, we must preserve any PCI resource |
1056 | * assignments made by firmware for this host bridge. |
1057 | */ |
1058 | obj = acpi_evaluate_dsm_typed(ACPI_HANDLE(bus->bridge), guid: &pci_acpi_dsm_guid, rev: 1, |
1059 | DSM_PCI_PRESERVE_BOOT_CONFIG, NULL, ACPI_TYPE_INTEGER); |
1060 | if (obj && obj->integer.value == 0) |
1061 | host_bridge->preserve_config = 1; |
1062 | ACPI_FREE(obj); |
1063 | |
1064 | acpi_dev_power_up_children_with_adr(adev: device); |
1065 | |
1066 | pci_scan_child_bus(bus); |
1067 | pci_set_host_bridge_release(bridge: host_bridge, release_fn: acpi_pci_root_release_info, |
1068 | release_data: info); |
1069 | if (node != NUMA_NO_NODE) |
1070 | dev_printk(KERN_DEBUG, &bus->dev, "on NUMA node %d\n" , node); |
1071 | return bus; |
1072 | |
1073 | out_release_info: |
1074 | __acpi_pci_root_release_info(info); |
1075 | return NULL; |
1076 | } |
1077 | |
1078 | void __init acpi_pci_root_init(void) |
1079 | { |
1080 | if (acpi_pci_disabled) |
1081 | return; |
1082 | |
1083 | pci_acpi_crs_quirks(); |
1084 | acpi_scan_add_handler_with_hotplug(handler: &pci_root_handler, hotplug_profile_name: "pci_root" ); |
1085 | } |
1086 | |