1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * ahci.c - AHCI SATA support |
4 | * |
5 | * Maintained by: Tejun Heo <tj@kernel.org> |
6 | * Please ALWAYS copy linux-ide@vger.kernel.org |
7 | * on emails. |
8 | * |
9 | * Copyright 2004-2005 Red Hat, Inc. |
10 | * |
11 | * libata documentation is available via 'make {ps|pdf}docs', |
12 | * as Documentation/driver-api/libata.rst |
13 | * |
14 | * AHCI hardware documentation: |
15 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
16 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
17 | */ |
18 | |
19 | #include <linux/kernel.h> |
20 | #include <linux/module.h> |
21 | #include <linux/pci.h> |
22 | #include <linux/blkdev.h> |
23 | #include <linux/delay.h> |
24 | #include <linux/interrupt.h> |
25 | #include <linux/dma-mapping.h> |
26 | #include <linux/device.h> |
27 | #include <linux/dmi.h> |
28 | #include <linux/gfp.h> |
29 | #include <scsi/scsi_host.h> |
30 | #include <scsi/scsi_cmnd.h> |
31 | #include <linux/libata.h> |
32 | #include <linux/ahci-remap.h> |
33 | #include <linux/io-64-nonatomic-lo-hi.h> |
34 | #include "ahci.h" |
35 | |
36 | #define DRV_NAME "ahci" |
37 | #define DRV_VERSION "3.0" |
38 | |
39 | enum { |
40 | AHCI_PCI_BAR_STA2X11 = 0, |
41 | AHCI_PCI_BAR_CAVIUM = 0, |
42 | AHCI_PCI_BAR_LOONGSON = 0, |
43 | AHCI_PCI_BAR_ENMOTUS = 2, |
44 | AHCI_PCI_BAR_CAVIUM_GEN5 = 4, |
45 | AHCI_PCI_BAR_STANDARD = 5, |
46 | }; |
47 | |
48 | enum board_ids { |
49 | /* board IDs by feature in alphabetical order */ |
50 | board_ahci, |
51 | board_ahci_ign_iferr, |
52 | board_ahci_low_power, |
53 | board_ahci_no_debounce_delay, |
54 | board_ahci_nomsi, |
55 | board_ahci_noncq, |
56 | board_ahci_nosntf, |
57 | board_ahci_yes_fbs, |
58 | |
59 | /* board IDs for specific chipsets in alphabetical order */ |
60 | board_ahci_al, |
61 | board_ahci_avn, |
62 | board_ahci_mcp65, |
63 | board_ahci_mcp77, |
64 | board_ahci_mcp89, |
65 | board_ahci_mv, |
66 | board_ahci_sb600, |
67 | board_ahci_sb700, /* for SB700 and SB800 */ |
68 | board_ahci_vt8251, |
69 | |
70 | /* |
71 | * board IDs for Intel chipsets that support more than 6 ports |
72 | * *and* end up needing the PCS quirk. |
73 | */ |
74 | board_ahci_pcs7, |
75 | |
76 | /* aliases */ |
77 | board_ahci_mcp_linux = board_ahci_mcp65, |
78 | board_ahci_mcp67 = board_ahci_mcp65, |
79 | board_ahci_mcp73 = board_ahci_mcp65, |
80 | board_ahci_mcp79 = board_ahci_mcp77, |
81 | }; |
82 | |
83 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
84 | static void ahci_remove_one(struct pci_dev *dev); |
85 | static void ahci_shutdown_one(struct pci_dev *dev); |
86 | static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv); |
87 | static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, |
88 | unsigned long deadline); |
89 | static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, |
90 | unsigned long deadline); |
91 | static void ahci_mcp89_apple_enable(struct pci_dev *pdev); |
92 | static bool is_mcp89_apple(struct pci_dev *pdev); |
93 | static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, |
94 | unsigned long deadline); |
95 | #ifdef CONFIG_PM |
96 | static int ahci_pci_device_runtime_suspend(struct device *dev); |
97 | static int ahci_pci_device_runtime_resume(struct device *dev); |
98 | #ifdef CONFIG_PM_SLEEP |
99 | static int ahci_pci_device_suspend(struct device *dev); |
100 | static int ahci_pci_device_resume(struct device *dev); |
101 | #endif |
102 | #endif /* CONFIG_PM */ |
103 | |
104 | static const struct scsi_host_template ahci_sht = { |
105 | AHCI_SHT("ahci" ), |
106 | }; |
107 | |
108 | static struct ata_port_operations ahci_vt8251_ops = { |
109 | .inherits = &ahci_ops, |
110 | .hardreset = ahci_vt8251_hardreset, |
111 | }; |
112 | |
113 | static struct ata_port_operations ahci_p5wdh_ops = { |
114 | .inherits = &ahci_ops, |
115 | .hardreset = ahci_p5wdh_hardreset, |
116 | }; |
117 | |
118 | static struct ata_port_operations ahci_avn_ops = { |
119 | .inherits = &ahci_ops, |
120 | .hardreset = ahci_avn_hardreset, |
121 | }; |
122 | |
123 | static const struct ata_port_info ahci_port_info[] = { |
124 | /* by features */ |
125 | [board_ahci] = { |
126 | .flags = AHCI_FLAG_COMMON, |
127 | .pio_mask = ATA_PIO4, |
128 | .udma_mask = ATA_UDMA6, |
129 | .port_ops = &ahci_ops, |
130 | }, |
131 | [board_ahci_ign_iferr] = { |
132 | AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), |
133 | .flags = AHCI_FLAG_COMMON, |
134 | .pio_mask = ATA_PIO4, |
135 | .udma_mask = ATA_UDMA6, |
136 | .port_ops = &ahci_ops, |
137 | }, |
138 | [board_ahci_low_power] = { |
139 | AHCI_HFLAGS (AHCI_HFLAG_USE_LPM_POLICY), |
140 | .flags = AHCI_FLAG_COMMON, |
141 | .pio_mask = ATA_PIO4, |
142 | .udma_mask = ATA_UDMA6, |
143 | .port_ops = &ahci_ops, |
144 | }, |
145 | [board_ahci_no_debounce_delay] = { |
146 | .flags = AHCI_FLAG_COMMON, |
147 | .link_flags = ATA_LFLAG_NO_DEBOUNCE_DELAY, |
148 | .pio_mask = ATA_PIO4, |
149 | .udma_mask = ATA_UDMA6, |
150 | .port_ops = &ahci_ops, |
151 | }, |
152 | [board_ahci_nomsi] = { |
153 | AHCI_HFLAGS (AHCI_HFLAG_NO_MSI), |
154 | .flags = AHCI_FLAG_COMMON, |
155 | .pio_mask = ATA_PIO4, |
156 | .udma_mask = ATA_UDMA6, |
157 | .port_ops = &ahci_ops, |
158 | }, |
159 | [board_ahci_noncq] = { |
160 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ), |
161 | .flags = AHCI_FLAG_COMMON, |
162 | .pio_mask = ATA_PIO4, |
163 | .udma_mask = ATA_UDMA6, |
164 | .port_ops = &ahci_ops, |
165 | }, |
166 | [board_ahci_nosntf] = { |
167 | AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF), |
168 | .flags = AHCI_FLAG_COMMON, |
169 | .pio_mask = ATA_PIO4, |
170 | .udma_mask = ATA_UDMA6, |
171 | .port_ops = &ahci_ops, |
172 | }, |
173 | [board_ahci_yes_fbs] = { |
174 | AHCI_HFLAGS (AHCI_HFLAG_YES_FBS), |
175 | .flags = AHCI_FLAG_COMMON, |
176 | .pio_mask = ATA_PIO4, |
177 | .udma_mask = ATA_UDMA6, |
178 | .port_ops = &ahci_ops, |
179 | }, |
180 | /* by chipsets */ |
181 | [board_ahci_al] = { |
182 | AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI), |
183 | .flags = AHCI_FLAG_COMMON, |
184 | .pio_mask = ATA_PIO4, |
185 | .udma_mask = ATA_UDMA6, |
186 | .port_ops = &ahci_ops, |
187 | }, |
188 | [board_ahci_avn] = { |
189 | .flags = AHCI_FLAG_COMMON, |
190 | .pio_mask = ATA_PIO4, |
191 | .udma_mask = ATA_UDMA6, |
192 | .port_ops = &ahci_avn_ops, |
193 | }, |
194 | [board_ahci_mcp65] = { |
195 | AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP | |
196 | AHCI_HFLAG_YES_NCQ), |
197 | .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM, |
198 | .pio_mask = ATA_PIO4, |
199 | .udma_mask = ATA_UDMA6, |
200 | .port_ops = &ahci_ops, |
201 | }, |
202 | [board_ahci_mcp77] = { |
203 | AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP), |
204 | .flags = AHCI_FLAG_COMMON, |
205 | .pio_mask = ATA_PIO4, |
206 | .udma_mask = ATA_UDMA6, |
207 | .port_ops = &ahci_ops, |
208 | }, |
209 | [board_ahci_mcp89] = { |
210 | AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA), |
211 | .flags = AHCI_FLAG_COMMON, |
212 | .pio_mask = ATA_PIO4, |
213 | .udma_mask = ATA_UDMA6, |
214 | .port_ops = &ahci_ops, |
215 | }, |
216 | [board_ahci_mv] = { |
217 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | |
218 | AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP), |
219 | .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, |
220 | .pio_mask = ATA_PIO4, |
221 | .udma_mask = ATA_UDMA6, |
222 | .port_ops = &ahci_ops, |
223 | }, |
224 | [board_ahci_sb600] = { |
225 | AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | |
226 | AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 | |
227 | AHCI_HFLAG_32BIT_ONLY), |
228 | .flags = AHCI_FLAG_COMMON, |
229 | .pio_mask = ATA_PIO4, |
230 | .udma_mask = ATA_UDMA6, |
231 | .port_ops = &ahci_pmp_retry_srst_ops, |
232 | }, |
233 | [board_ahci_sb700] = { /* for SB700 and SB800 */ |
234 | AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL), |
235 | .flags = AHCI_FLAG_COMMON, |
236 | .pio_mask = ATA_PIO4, |
237 | .udma_mask = ATA_UDMA6, |
238 | .port_ops = &ahci_pmp_retry_srst_ops, |
239 | }, |
240 | [board_ahci_vt8251] = { |
241 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), |
242 | .flags = AHCI_FLAG_COMMON, |
243 | .pio_mask = ATA_PIO4, |
244 | .udma_mask = ATA_UDMA6, |
245 | .port_ops = &ahci_vt8251_ops, |
246 | }, |
247 | [board_ahci_pcs7] = { |
248 | .flags = AHCI_FLAG_COMMON, |
249 | .pio_mask = ATA_PIO4, |
250 | .udma_mask = ATA_UDMA6, |
251 | .port_ops = &ahci_ops, |
252 | }, |
253 | }; |
254 | |
255 | static const struct pci_device_id ahci_pci_tbl[] = { |
256 | /* Intel */ |
257 | { PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */ |
258 | { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ |
259 | { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ |
260 | { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ |
261 | { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ |
262 | { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ |
263 | { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ |
264 | { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ |
265 | { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ |
266 | { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ |
267 | { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ |
268 | { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ |
269 | { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8/Lewisburg RAID*/ |
270 | { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ |
271 | { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ |
272 | { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ |
273 | { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ |
274 | { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ |
275 | { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ |
276 | { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ |
277 | { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ |
278 | { PCI_VDEVICE(INTEL, 0x2929), board_ahci_low_power }, /* ICH9M */ |
279 | { PCI_VDEVICE(INTEL, 0x292a), board_ahci_low_power }, /* ICH9M */ |
280 | { PCI_VDEVICE(INTEL, 0x292b), board_ahci_low_power }, /* ICH9M */ |
281 | { PCI_VDEVICE(INTEL, 0x292c), board_ahci_low_power }, /* ICH9M */ |
282 | { PCI_VDEVICE(INTEL, 0x292f), board_ahci_low_power }, /* ICH9M */ |
283 | { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ |
284 | { PCI_VDEVICE(INTEL, 0x294e), board_ahci_low_power }, /* ICH9M */ |
285 | { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ |
286 | { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ |
287 | { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */ |
288 | { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */ |
289 | { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */ |
290 | { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */ |
291 | { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */ |
292 | { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */ |
293 | { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */ |
294 | { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_low_power }, /* PCH M AHCI */ |
295 | { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */ |
296 | { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_low_power }, /* PCH M RAID */ |
297 | { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */ |
298 | { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */ |
299 | { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */ |
300 | { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */ |
301 | { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */ |
302 | { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */ |
303 | { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */ |
304 | { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */ |
305 | { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */ |
306 | { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */ |
307 | { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */ |
308 | { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */ |
309 | { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */ |
310 | { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */ |
311 | { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */ |
312 | { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */ |
313 | { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */ |
314 | { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */ |
315 | { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */ |
316 | { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */ |
317 | { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */ |
318 | { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */ |
319 | { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_low_power }, /* CPT M AHCI */ |
320 | { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */ |
321 | { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_low_power }, /* CPT M RAID */ |
322 | { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */ |
323 | { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */ |
324 | { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */ |
325 | { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */ |
326 | { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */ |
327 | { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */ |
328 | { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */ |
329 | { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_low_power }, /* Panther M AHCI */ |
330 | { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */ |
331 | { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */ |
332 | { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */ |
333 | { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_low_power }, /* Panther M RAID */ |
334 | { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */ |
335 | { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */ |
336 | { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_low_power }, /* Lynx M AHCI */ |
337 | { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */ |
338 | { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_low_power }, /* Lynx M RAID */ |
339 | { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */ |
340 | { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_low_power }, /* Lynx M RAID */ |
341 | { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */ |
342 | { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_low_power }, /* Lynx M RAID */ |
343 | { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_low_power }, /* Lynx LP AHCI */ |
344 | { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_low_power }, /* Lynx LP AHCI */ |
345 | { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_low_power }, /* Lynx LP RAID */ |
346 | { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_low_power }, /* Lynx LP RAID */ |
347 | { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_low_power }, /* Lynx LP RAID */ |
348 | { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_low_power }, /* Lynx LP RAID */ |
349 | { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_low_power }, /* Lynx LP RAID */ |
350 | { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_low_power }, /* Lynx LP RAID */ |
351 | { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_low_power }, /* Cannon Lake PCH-LP AHCI */ |
352 | { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */ |
353 | { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */ |
354 | { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */ |
355 | { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */ |
356 | { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */ |
357 | { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */ |
358 | { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */ |
359 | { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */ |
360 | { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */ |
361 | { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */ |
362 | { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */ |
363 | { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */ |
364 | { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */ |
365 | { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */ |
366 | { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */ |
367 | { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */ |
368 | { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg/Lewisburg AHCI*/ |
369 | { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* *burg SATA0 'RAID' */ |
370 | { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* *burg SATA1 'RAID' */ |
371 | { PCI_VDEVICE(INTEL, 0x282f), board_ahci }, /* *burg SATA2 'RAID' */ |
372 | { PCI_VDEVICE(INTEL, 0x43d4), board_ahci }, /* Rocket Lake PCH-H RAID */ |
373 | { PCI_VDEVICE(INTEL, 0x43d5), board_ahci }, /* Rocket Lake PCH-H RAID */ |
374 | { PCI_VDEVICE(INTEL, 0x43d6), board_ahci }, /* Rocket Lake PCH-H RAID */ |
375 | { PCI_VDEVICE(INTEL, 0x43d7), board_ahci }, /* Rocket Lake PCH-H RAID */ |
376 | { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */ |
377 | { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */ |
378 | { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */ |
379 | { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */ |
380 | { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */ |
381 | { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */ |
382 | { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */ |
383 | { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */ |
384 | { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */ |
385 | { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_low_power }, /* Wildcat LP AHCI */ |
386 | { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_low_power }, /* Wildcat LP RAID */ |
387 | { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_low_power }, /* Wildcat LP RAID */ |
388 | { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_low_power }, /* Wildcat LP RAID */ |
389 | { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */ |
390 | { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_low_power }, /* 9 Series M AHCI */ |
391 | { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */ |
392 | { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_low_power }, /* 9 Series M RAID */ |
393 | { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */ |
394 | { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_low_power }, /* 9 Series M RAID */ |
395 | { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */ |
396 | { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_low_power }, /* 9 Series M RAID */ |
397 | { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_low_power }, /* Sunrise LP AHCI */ |
398 | { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_low_power }, /* Sunrise LP RAID */ |
399 | { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_low_power }, /* Sunrise LP RAID */ |
400 | { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */ |
401 | { PCI_VDEVICE(INTEL, 0xa103), board_ahci_low_power }, /* Sunrise M AHCI */ |
402 | { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */ |
403 | { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */ |
404 | { PCI_VDEVICE(INTEL, 0xa107), board_ahci_low_power }, /* Sunrise M RAID */ |
405 | { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */ |
406 | { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/ |
407 | { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/ |
408 | { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/ |
409 | { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/ |
410 | { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/ |
411 | { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/ |
412 | { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/ |
413 | { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/ |
414 | { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */ |
415 | { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */ |
416 | { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */ |
417 | { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_low_power }, /* Bay Trail AHCI */ |
418 | { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_low_power }, /* Bay Trail AHCI */ |
419 | { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_low_power }, /* Cherry Tr. AHCI */ |
420 | { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_low_power }, /* ApolloLake AHCI */ |
421 | { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_low_power }, /* Ice Lake LP AHCI */ |
422 | { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_low_power }, /* Comet Lake PCH-U AHCI */ |
423 | { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_low_power }, /* Comet Lake PCH RAID */ |
424 | /* Elkhart Lake IDs 0x4b60 & 0x4b62 https://sata-io.org/product/8803 not tested yet */ |
425 | { PCI_VDEVICE(INTEL, 0x4b63), board_ahci_low_power }, /* Elkhart Lake AHCI */ |
426 | { PCI_VDEVICE(INTEL, 0x7ae2), board_ahci_low_power }, /* Alder Lake-P AHCI */ |
427 | |
428 | /* JMicron 360/1/3/5/6, match class to avoid IDE function */ |
429 | { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
430 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, |
431 | /* JMicron 362B and 362C have an AHCI function with IDE class code */ |
432 | { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr }, |
433 | { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr }, |
434 | /* May need to update quirk_jmicron_async_suspend() for additions */ |
435 | |
436 | /* ATI */ |
437 | { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ |
438 | { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ |
439 | { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ |
440 | { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ |
441 | { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ |
442 | { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ |
443 | { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ |
444 | |
445 | /* Amazon's Annapurna Labs support */ |
446 | { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031), |
447 | .class = PCI_CLASS_STORAGE_SATA_AHCI, |
448 | .class_mask = 0xffffff, |
449 | board_ahci_al }, |
450 | /* AMD */ |
451 | { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */ |
452 | { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */ |
453 | { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */ |
454 | { PCI_VDEVICE(AMD, 0x7901), board_ahci_low_power }, /* AMD Green Sardine */ |
455 | /* AMD is using RAID class only for ahci controllers */ |
456 | { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
457 | PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci }, |
458 | |
459 | /* Dell S140/S150 */ |
460 | { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID, |
461 | PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci }, |
462 | |
463 | /* VIA */ |
464 | { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ |
465 | { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ |
466 | |
467 | /* NVIDIA */ |
468 | { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */ |
469 | { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */ |
470 | { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */ |
471 | { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */ |
472 | { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */ |
473 | { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */ |
474 | { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */ |
475 | { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */ |
476 | { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */ |
477 | { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */ |
478 | { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */ |
479 | { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */ |
480 | { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */ |
481 | { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */ |
482 | { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */ |
483 | { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */ |
484 | { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */ |
485 | { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */ |
486 | { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */ |
487 | { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */ |
488 | { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */ |
489 | { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */ |
490 | { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */ |
491 | { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */ |
492 | { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */ |
493 | { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */ |
494 | { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */ |
495 | { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */ |
496 | { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */ |
497 | { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */ |
498 | { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */ |
499 | { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */ |
500 | { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */ |
501 | { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */ |
502 | { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */ |
503 | { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */ |
504 | { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */ |
505 | { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */ |
506 | { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */ |
507 | { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */ |
508 | { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */ |
509 | { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */ |
510 | { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */ |
511 | { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */ |
512 | { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */ |
513 | { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */ |
514 | { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */ |
515 | { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */ |
516 | { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */ |
517 | { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */ |
518 | { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */ |
519 | { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */ |
520 | { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */ |
521 | { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */ |
522 | { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */ |
523 | { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */ |
524 | { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */ |
525 | { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */ |
526 | { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */ |
527 | { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */ |
528 | { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */ |
529 | { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */ |
530 | { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */ |
531 | { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */ |
532 | { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */ |
533 | { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */ |
534 | { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */ |
535 | { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */ |
536 | { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */ |
537 | { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */ |
538 | { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */ |
539 | { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */ |
540 | { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */ |
541 | { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */ |
542 | { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */ |
543 | { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */ |
544 | { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */ |
545 | { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */ |
546 | { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */ |
547 | { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */ |
548 | { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */ |
549 | { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */ |
550 | { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */ |
551 | { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */ |
552 | |
553 | /* SiS */ |
554 | { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ |
555 | { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */ |
556 | { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ |
557 | |
558 | /* ST Microelectronics */ |
559 | { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */ |
560 | |
561 | /* Marvell */ |
562 | { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ |
563 | { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ |
564 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123), |
565 | .class = PCI_CLASS_STORAGE_SATA_AHCI, |
566 | .class_mask = 0xffffff, |
567 | .driver_data = board_ahci_yes_fbs }, /* 88se9128 */ |
568 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125), |
569 | .driver_data = board_ahci_yes_fbs }, /* 88se9125 */ |
570 | { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178, |
571 | PCI_VENDOR_ID_MARVELL_EXT, 0x9170), |
572 | .driver_data = board_ahci_yes_fbs }, /* 88se9170 */ |
573 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a), |
574 | .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ |
575 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172), |
576 | .driver_data = board_ahci_yes_fbs }, /* 88se9182 */ |
577 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182), |
578 | .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ |
579 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192), |
580 | .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */ |
581 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0), |
582 | .driver_data = board_ahci_yes_fbs }, |
583 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */ |
584 | .driver_data = board_ahci_yes_fbs }, |
585 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3), |
586 | .driver_data = board_ahci_yes_fbs }, |
587 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230), |
588 | .driver_data = board_ahci_yes_fbs }, |
589 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9235), |
590 | .driver_data = board_ahci_no_debounce_delay }, |
591 | { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */ |
592 | .driver_data = board_ahci_yes_fbs }, |
593 | { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */ |
594 | .driver_data = board_ahci_yes_fbs }, |
595 | |
596 | /* Promise */ |
597 | { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */ |
598 | { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */ |
599 | |
600 | /* Asmedia */ |
601 | { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */ |
602 | { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */ |
603 | { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */ |
604 | { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */ |
605 | { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */ |
606 | { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */ |
607 | { PCI_VDEVICE(ASMEDIA, 0x0624), board_ahci }, /* ASM1062+JMB575 */ |
608 | { PCI_VDEVICE(ASMEDIA, 0x1062), board_ahci }, /* ASM1062A */ |
609 | { PCI_VDEVICE(ASMEDIA, 0x1064), board_ahci }, /* ASM1064 */ |
610 | { PCI_VDEVICE(ASMEDIA, 0x1164), board_ahci }, /* ASM1164 */ |
611 | { PCI_VDEVICE(ASMEDIA, 0x1165), board_ahci }, /* ASM1165 */ |
612 | { PCI_VDEVICE(ASMEDIA, 0x1166), board_ahci }, /* ASM1166 */ |
613 | |
614 | /* |
615 | * Samsung SSDs found on some macbooks. NCQ times out if MSI is |
616 | * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731 |
617 | */ |
618 | { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi }, |
619 | { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi }, |
620 | |
621 | /* Enmotus */ |
622 | { PCI_DEVICE(0x1c44, 0x8000), board_ahci }, |
623 | |
624 | /* Loongson */ |
625 | { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci }, |
626 | |
627 | /* Generic, PCI class code for AHCI */ |
628 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
629 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, |
630 | |
631 | { } /* terminate list */ |
632 | }; |
633 | |
634 | static const struct dev_pm_ops ahci_pci_pm_ops = { |
635 | SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume) |
636 | SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend, |
637 | ahci_pci_device_runtime_resume, NULL) |
638 | }; |
639 | |
640 | static struct pci_driver ahci_pci_driver = { |
641 | .name = DRV_NAME, |
642 | .id_table = ahci_pci_tbl, |
643 | .probe = ahci_init_one, |
644 | .remove = ahci_remove_one, |
645 | .shutdown = ahci_shutdown_one, |
646 | .driver = { |
647 | .pm = &ahci_pci_pm_ops, |
648 | }, |
649 | }; |
650 | |
651 | #if IS_ENABLED(CONFIG_PATA_MARVELL) |
652 | static int marvell_enable; |
653 | #else |
654 | static int marvell_enable = 1; |
655 | #endif |
656 | module_param(marvell_enable, int, 0644); |
657 | MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)" ); |
658 | |
659 | static int mobile_lpm_policy = -1; |
660 | module_param(mobile_lpm_policy, int, 0644); |
661 | MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets" ); |
662 | |
663 | static void ahci_pci_save_initial_config(struct pci_dev *pdev, |
664 | struct ahci_host_priv *hpriv) |
665 | { |
666 | if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) { |
667 | dev_info(&pdev->dev, "JMB361 has only one port\n" ); |
668 | hpriv->saved_port_map = 1; |
669 | } |
670 | |
671 | /* |
672 | * Temporary Marvell 6145 hack: PATA port presence |
673 | * is asserted through the standard AHCI port |
674 | * presence register, as bit 4 (counting from 0) |
675 | */ |
676 | if (hpriv->flags & AHCI_HFLAG_MV_PATA) { |
677 | if (pdev->device == 0x6121) |
678 | hpriv->mask_port_map = 0x3; |
679 | else |
680 | hpriv->mask_port_map = 0xf; |
681 | dev_info(&pdev->dev, |
682 | "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n" ); |
683 | } |
684 | |
685 | ahci_save_initial_config(dev: &pdev->dev, hpriv); |
686 | } |
687 | |
688 | static int ahci_pci_reset_controller(struct ata_host *host) |
689 | { |
690 | struct pci_dev *pdev = to_pci_dev(host->dev); |
691 | struct ahci_host_priv *hpriv = host->private_data; |
692 | int rc; |
693 | |
694 | rc = ahci_reset_controller(host); |
695 | if (rc) |
696 | return rc; |
697 | |
698 | /* |
699 | * If platform firmware failed to enable ports, try to enable |
700 | * them here. |
701 | */ |
702 | ahci_intel_pcs_quirk(pdev, hpriv); |
703 | |
704 | return 0; |
705 | } |
706 | |
707 | static void ahci_pci_init_controller(struct ata_host *host) |
708 | { |
709 | struct ahci_host_priv *hpriv = host->private_data; |
710 | struct pci_dev *pdev = to_pci_dev(host->dev); |
711 | void __iomem *port_mmio; |
712 | u32 tmp; |
713 | int mv; |
714 | |
715 | if (hpriv->flags & AHCI_HFLAG_MV_PATA) { |
716 | if (pdev->device == 0x6121) |
717 | mv = 2; |
718 | else |
719 | mv = 4; |
720 | port_mmio = __ahci_port_base(hpriv, port_no: mv); |
721 | |
722 | writel(val: 0, addr: port_mmio + PORT_IRQ_MASK); |
723 | |
724 | /* clear port IRQ */ |
725 | tmp = readl(addr: port_mmio + PORT_IRQ_STAT); |
726 | dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n" , tmp); |
727 | if (tmp) |
728 | writel(val: tmp, addr: port_mmio + PORT_IRQ_STAT); |
729 | } |
730 | |
731 | ahci_init_controller(host); |
732 | } |
733 | |
734 | static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, |
735 | unsigned long deadline) |
736 | { |
737 | struct ata_port *ap = link->ap; |
738 | struct ahci_host_priv *hpriv = ap->host->private_data; |
739 | bool online; |
740 | int rc; |
741 | |
742 | hpriv->stop_engine(ap); |
743 | |
744 | rc = sata_link_hardreset(link, timing: sata_ehc_deb_timing(ehc: &link->eh_context), |
745 | deadline, online: &online, NULL); |
746 | |
747 | hpriv->start_engine(ap); |
748 | |
749 | /* vt8251 doesn't clear BSY on signature FIS reception, |
750 | * request follow-up softreset. |
751 | */ |
752 | return online ? -EAGAIN : rc; |
753 | } |
754 | |
755 | static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, |
756 | unsigned long deadline) |
757 | { |
758 | struct ata_port *ap = link->ap; |
759 | struct ahci_port_priv *pp = ap->private_data; |
760 | struct ahci_host_priv *hpriv = ap->host->private_data; |
761 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; |
762 | struct ata_taskfile tf; |
763 | bool online; |
764 | int rc; |
765 | |
766 | hpriv->stop_engine(ap); |
767 | |
768 | /* clear D2H reception area to properly wait for D2H FIS */ |
769 | ata_tf_init(dev: link->device, tf: &tf); |
770 | tf.status = ATA_BUSY; |
771 | ata_tf_to_fis(tf: &tf, pmp: 0, is_cmd: 0, fis: d2h_fis); |
772 | |
773 | rc = sata_link_hardreset(link, timing: sata_ehc_deb_timing(ehc: &link->eh_context), |
774 | deadline, online: &online, NULL); |
775 | |
776 | hpriv->start_engine(ap); |
777 | |
778 | /* The pseudo configuration device on SIMG4726 attached to |
779 | * ASUS P5W-DH Deluxe doesn't send signature FIS after |
780 | * hardreset if no device is attached to the first downstream |
781 | * port && the pseudo device locks up on SRST w/ PMP==0. To |
782 | * work around this, wait for !BSY only briefly. If BSY isn't |
783 | * cleared, perform CLO and proceed to IDENTIFY (achieved by |
784 | * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). |
785 | * |
786 | * Wait for two seconds. Devices attached to downstream port |
787 | * which can't process the following IDENTIFY after this will |
788 | * have to be reset again. For most cases, this should |
789 | * suffice while making probing snappish enough. |
790 | */ |
791 | if (online) { |
792 | rc = ata_wait_after_reset(link, deadline: jiffies + 2 * HZ, |
793 | check_ready: ahci_check_ready); |
794 | if (rc) |
795 | ahci_kick_engine(ap); |
796 | } |
797 | return rc; |
798 | } |
799 | |
800 | /* |
801 | * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports. |
802 | * |
803 | * It has been observed with some SSDs that the timing of events in the |
804 | * link synchronization phase can leave the port in a state that can not |
805 | * be recovered by a SATA-hard-reset alone. The failing signature is |
806 | * SStatus.DET stuck at 1 ("Device presence detected but Phy |
807 | * communication not established"). It was found that unloading and |
808 | * reloading the driver when this problem occurs allows the drive |
809 | * connection to be recovered (DET advanced to 0x3). The critical |
810 | * component of reloading the driver is that the port state machines are |
811 | * reset by bouncing "port enable" in the AHCI PCS configuration |
812 | * register. So, reproduce that effect by bouncing a port whenever we |
813 | * see DET==1 after a reset. |
814 | */ |
815 | static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, |
816 | unsigned long deadline) |
817 | { |
818 | const unsigned int *timing = sata_ehc_deb_timing(ehc: &link->eh_context); |
819 | struct ata_port *ap = link->ap; |
820 | struct ahci_port_priv *pp = ap->private_data; |
821 | struct ahci_host_priv *hpriv = ap->host->private_data; |
822 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; |
823 | unsigned long tmo = deadline - jiffies; |
824 | struct ata_taskfile tf; |
825 | bool online; |
826 | int rc, i; |
827 | |
828 | hpriv->stop_engine(ap); |
829 | |
830 | for (i = 0; i < 2; i++) { |
831 | u16 val; |
832 | u32 sstatus; |
833 | int port = ap->port_no; |
834 | struct ata_host *host = ap->host; |
835 | struct pci_dev *pdev = to_pci_dev(host->dev); |
836 | |
837 | /* clear D2H reception area to properly wait for D2H FIS */ |
838 | ata_tf_init(dev: link->device, tf: &tf); |
839 | tf.status = ATA_BUSY; |
840 | ata_tf_to_fis(tf: &tf, pmp: 0, is_cmd: 0, fis: d2h_fis); |
841 | |
842 | rc = sata_link_hardreset(link, timing, deadline, online: &online, |
843 | check_ready: ahci_check_ready); |
844 | |
845 | if (sata_scr_read(link, reg: SCR_STATUS, val: &sstatus) != 0 || |
846 | (sstatus & 0xf) != 1) |
847 | break; |
848 | |
849 | ata_link_info(link, "avn bounce port%d\n" , port); |
850 | |
851 | pci_read_config_word(dev: pdev, where: 0x92, val: &val); |
852 | val &= ~(1 << port); |
853 | pci_write_config_word(dev: pdev, where: 0x92, val); |
854 | ata_msleep(ap, msecs: 1000); |
855 | val |= 1 << port; |
856 | pci_write_config_word(dev: pdev, where: 0x92, val); |
857 | deadline += tmo; |
858 | } |
859 | |
860 | hpriv->start_engine(ap); |
861 | |
862 | if (online) |
863 | *class = ahci_dev_classify(ap); |
864 | |
865 | return rc; |
866 | } |
867 | |
868 | |
869 | #ifdef CONFIG_PM |
870 | static void ahci_pci_disable_interrupts(struct ata_host *host) |
871 | { |
872 | struct ahci_host_priv *hpriv = host->private_data; |
873 | void __iomem *mmio = hpriv->mmio; |
874 | u32 ctl; |
875 | |
876 | /* AHCI spec rev1.1 section 8.3.3: |
877 | * Software must disable interrupts prior to requesting a |
878 | * transition of the HBA to D3 state. |
879 | */ |
880 | ctl = readl(addr: mmio + HOST_CTL); |
881 | ctl &= ~HOST_IRQ_EN; |
882 | writel(val: ctl, addr: mmio + HOST_CTL); |
883 | readl(addr: mmio + HOST_CTL); /* flush */ |
884 | } |
885 | |
886 | static int ahci_pci_device_runtime_suspend(struct device *dev) |
887 | { |
888 | struct pci_dev *pdev = to_pci_dev(dev); |
889 | struct ata_host *host = pci_get_drvdata(pdev); |
890 | |
891 | ahci_pci_disable_interrupts(host); |
892 | return 0; |
893 | } |
894 | |
895 | static int ahci_pci_device_runtime_resume(struct device *dev) |
896 | { |
897 | struct pci_dev *pdev = to_pci_dev(dev); |
898 | struct ata_host *host = pci_get_drvdata(pdev); |
899 | int rc; |
900 | |
901 | rc = ahci_pci_reset_controller(host); |
902 | if (rc) |
903 | return rc; |
904 | ahci_pci_init_controller(host); |
905 | return 0; |
906 | } |
907 | |
908 | #ifdef CONFIG_PM_SLEEP |
909 | static int ahci_pci_device_suspend(struct device *dev) |
910 | { |
911 | struct pci_dev *pdev = to_pci_dev(dev); |
912 | struct ata_host *host = pci_get_drvdata(pdev); |
913 | struct ahci_host_priv *hpriv = host->private_data; |
914 | |
915 | if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { |
916 | dev_err(&pdev->dev, |
917 | "BIOS update required for suspend/resume\n" ); |
918 | return -EIO; |
919 | } |
920 | |
921 | ahci_pci_disable_interrupts(host); |
922 | ata_host_suspend(host, PMSG_SUSPEND); |
923 | return 0; |
924 | } |
925 | |
926 | static int ahci_pci_device_resume(struct device *dev) |
927 | { |
928 | struct pci_dev *pdev = to_pci_dev(dev); |
929 | struct ata_host *host = pci_get_drvdata(pdev); |
930 | int rc; |
931 | |
932 | /* Apple BIOS helpfully mangles the registers on resume */ |
933 | if (is_mcp89_apple(pdev)) |
934 | ahci_mcp89_apple_enable(pdev); |
935 | |
936 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { |
937 | rc = ahci_pci_reset_controller(host); |
938 | if (rc) |
939 | return rc; |
940 | |
941 | ahci_pci_init_controller(host); |
942 | } |
943 | |
944 | ata_host_resume(host); |
945 | |
946 | return 0; |
947 | } |
948 | #endif |
949 | |
950 | #endif /* CONFIG_PM */ |
951 | |
952 | static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) |
953 | { |
954 | const int dma_bits = using_dac ? 64 : 32; |
955 | int rc; |
956 | |
957 | /* |
958 | * If the device fixup already set the dma_mask to some non-standard |
959 | * value, don't extend it here. This happens on STA2X11, for example. |
960 | * |
961 | * XXX: manipulating the DMA mask from platform code is completely |
962 | * bogus, platform code should use dev->bus_dma_limit instead.. |
963 | */ |
964 | if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32)) |
965 | return 0; |
966 | |
967 | rc = dma_set_mask_and_coherent(dev: &pdev->dev, DMA_BIT_MASK(dma_bits)); |
968 | if (rc) |
969 | dev_err(&pdev->dev, "DMA enable failed\n" ); |
970 | return rc; |
971 | } |
972 | |
973 | static void ahci_pci_print_info(struct ata_host *host) |
974 | { |
975 | struct pci_dev *pdev = to_pci_dev(host->dev); |
976 | u16 cc; |
977 | const char *scc_s; |
978 | |
979 | pci_read_config_word(dev: pdev, where: 0x0a, val: &cc); |
980 | if (cc == PCI_CLASS_STORAGE_IDE) |
981 | scc_s = "IDE" ; |
982 | else if (cc == PCI_CLASS_STORAGE_SATA) |
983 | scc_s = "SATA" ; |
984 | else if (cc == PCI_CLASS_STORAGE_RAID) |
985 | scc_s = "RAID" ; |
986 | else |
987 | scc_s = "unknown" ; |
988 | |
989 | ahci_print_info(host, scc_s); |
990 | } |
991 | |
992 | /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is |
993 | * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't |
994 | * support PMP and the 4726 either directly exports the device |
995 | * attached to the first downstream port or acts as a hardware storage |
996 | * controller and emulate a single ATA device (can be RAID 0/1 or some |
997 | * other configuration). |
998 | * |
999 | * When there's no device attached to the first downstream port of the |
1000 | * 4726, "Config Disk" appears, which is a pseudo ATA device to |
1001 | * configure the 4726. However, ATA emulation of the device is very |
1002 | * lame. It doesn't send signature D2H Reg FIS after the initial |
1003 | * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. |
1004 | * |
1005 | * The following function works around the problem by always using |
1006 | * hardreset on the port and not depending on receiving signature FIS |
1007 | * afterward. If signature FIS isn't received soon, ATA class is |
1008 | * assumed without follow-up softreset. |
1009 | */ |
1010 | static void ahci_p5wdh_workaround(struct ata_host *host) |
1011 | { |
1012 | static const struct dmi_system_id sysids[] = { |
1013 | { |
1014 | .ident = "P5W DH Deluxe" , |
1015 | .matches = { |
1016 | DMI_MATCH(DMI_SYS_VENDOR, |
1017 | "ASUSTEK COMPUTER INC" ), |
1018 | DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe" ), |
1019 | }, |
1020 | }, |
1021 | { } |
1022 | }; |
1023 | struct pci_dev *pdev = to_pci_dev(host->dev); |
1024 | |
1025 | if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && |
1026 | dmi_check_system(list: sysids)) { |
1027 | struct ata_port *ap = host->ports[1]; |
1028 | |
1029 | dev_info(&pdev->dev, |
1030 | "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n" ); |
1031 | |
1032 | ap->ops = &ahci_p5wdh_ops; |
1033 | ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; |
1034 | } |
1035 | } |
1036 | |
1037 | /* |
1038 | * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when |
1039 | * booting in BIOS compatibility mode. We restore the registers but not ID. |
1040 | */ |
1041 | static void ahci_mcp89_apple_enable(struct pci_dev *pdev) |
1042 | { |
1043 | u32 val; |
1044 | |
1045 | printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n" ); |
1046 | |
1047 | pci_read_config_dword(dev: pdev, where: 0xf8, val: &val); |
1048 | val |= 1 << 0x1b; |
1049 | /* the following changes the device ID, but appears not to affect function */ |
1050 | /* val = (val & ~0xf0000000) | 0x80000000; */ |
1051 | pci_write_config_dword(dev: pdev, where: 0xf8, val); |
1052 | |
1053 | pci_read_config_dword(dev: pdev, where: 0x54c, val: &val); |
1054 | val |= 1 << 0xc; |
1055 | pci_write_config_dword(dev: pdev, where: 0x54c, val); |
1056 | |
1057 | pci_read_config_dword(dev: pdev, where: 0x4a4, val: &val); |
1058 | val &= 0xff; |
1059 | val |= 0x01060100; |
1060 | pci_write_config_dword(dev: pdev, where: 0x4a4, val); |
1061 | |
1062 | pci_read_config_dword(dev: pdev, where: 0x54c, val: &val); |
1063 | val &= ~(1 << 0xc); |
1064 | pci_write_config_dword(dev: pdev, where: 0x54c, val); |
1065 | |
1066 | pci_read_config_dword(dev: pdev, where: 0xf8, val: &val); |
1067 | val &= ~(1 << 0x1b); |
1068 | pci_write_config_dword(dev: pdev, where: 0xf8, val); |
1069 | } |
1070 | |
1071 | static bool is_mcp89_apple(struct pci_dev *pdev) |
1072 | { |
1073 | return pdev->vendor == PCI_VENDOR_ID_NVIDIA && |
1074 | pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA && |
1075 | pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE && |
1076 | pdev->subsystem_device == 0xcb89; |
1077 | } |
1078 | |
1079 | /* only some SB600 ahci controllers can do 64bit DMA */ |
1080 | static bool ahci_sb600_enable_64bit(struct pci_dev *pdev) |
1081 | { |
1082 | static const struct dmi_system_id sysids[] = { |
1083 | /* |
1084 | * The oldest version known to be broken is 0901 and |
1085 | * working is 1501 which was released on 2007-10-26. |
1086 | * Enable 64bit DMA on 1501 and anything newer. |
1087 | * |
1088 | * Please read bko#9412 for more info. |
1089 | */ |
1090 | { |
1091 | .ident = "ASUS M2A-VM" , |
1092 | .matches = { |
1093 | DMI_MATCH(DMI_BOARD_VENDOR, |
1094 | "ASUSTeK Computer INC." ), |
1095 | DMI_MATCH(DMI_BOARD_NAME, "M2A-VM" ), |
1096 | }, |
1097 | .driver_data = "20071026" , /* yyyymmdd */ |
1098 | }, |
1099 | /* |
1100 | * All BIOS versions for the MSI K9A2 Platinum (MS-7376) |
1101 | * support 64bit DMA. |
1102 | * |
1103 | * BIOS versions earlier than 1.5 had the Manufacturer DMI |
1104 | * fields as "MICRO-STAR INTERANTIONAL CO.,LTD". |
1105 | * This spelling mistake was fixed in BIOS version 1.5, so |
1106 | * 1.5 and later have the Manufacturer as |
1107 | * "MICRO-STAR INTERNATIONAL CO.,LTD". |
1108 | * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER". |
1109 | * |
1110 | * BIOS versions earlier than 1.9 had a Board Product Name |
1111 | * DMI field of "MS-7376". This was changed to be |
1112 | * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still |
1113 | * match on DMI_BOARD_NAME of "MS-7376". |
1114 | */ |
1115 | { |
1116 | .ident = "MSI K9A2 Platinum" , |
1117 | .matches = { |
1118 | DMI_MATCH(DMI_BOARD_VENDOR, |
1119 | "MICRO-STAR INTER" ), |
1120 | DMI_MATCH(DMI_BOARD_NAME, "MS-7376" ), |
1121 | }, |
1122 | }, |
1123 | /* |
1124 | * All BIOS versions for the MSI K9AGM2 (MS-7327) support |
1125 | * 64bit DMA. |
1126 | * |
1127 | * This board also had the typo mentioned above in the |
1128 | * Manufacturer DMI field (fixed in BIOS version 1.5), so |
1129 | * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again. |
1130 | */ |
1131 | { |
1132 | .ident = "MSI K9AGM2" , |
1133 | .matches = { |
1134 | DMI_MATCH(DMI_BOARD_VENDOR, |
1135 | "MICRO-STAR INTER" ), |
1136 | DMI_MATCH(DMI_BOARD_NAME, "MS-7327" ), |
1137 | }, |
1138 | }, |
1139 | /* |
1140 | * All BIOS versions for the Asus M3A support 64bit DMA. |
1141 | * (all release versions from 0301 to 1206 were tested) |
1142 | */ |
1143 | { |
1144 | .ident = "ASUS M3A" , |
1145 | .matches = { |
1146 | DMI_MATCH(DMI_BOARD_VENDOR, |
1147 | "ASUSTeK Computer INC." ), |
1148 | DMI_MATCH(DMI_BOARD_NAME, "M3A" ), |
1149 | }, |
1150 | }, |
1151 | { } |
1152 | }; |
1153 | const struct dmi_system_id *match; |
1154 | int year, month, date; |
1155 | char buf[9]; |
1156 | |
1157 | match = dmi_first_match(list: sysids); |
1158 | if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) || |
1159 | !match) |
1160 | return false; |
1161 | |
1162 | if (!match->driver_data) |
1163 | goto enable_64bit; |
1164 | |
1165 | dmi_get_date(field: DMI_BIOS_DATE, yearp: &year, monthp: &month, dayp: &date); |
1166 | snprintf(buf, size: sizeof(buf), fmt: "%04d%02d%02d" , year, month, date); |
1167 | |
1168 | if (strcmp(buf, match->driver_data) >= 0) |
1169 | goto enable_64bit; |
1170 | else { |
1171 | dev_warn(&pdev->dev, |
1172 | "%s: BIOS too old, forcing 32bit DMA, update BIOS\n" , |
1173 | match->ident); |
1174 | return false; |
1175 | } |
1176 | |
1177 | enable_64bit: |
1178 | dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n" , match->ident); |
1179 | return true; |
1180 | } |
1181 | |
1182 | static bool ahci_broken_system_poweroff(struct pci_dev *pdev) |
1183 | { |
1184 | static const struct dmi_system_id broken_systems[] = { |
1185 | { |
1186 | .ident = "HP Compaq nx6310" , |
1187 | .matches = { |
1188 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard" ), |
1189 | DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310" ), |
1190 | }, |
1191 | /* PCI slot number of the controller */ |
1192 | .driver_data = (void *)0x1FUL, |
1193 | }, |
1194 | { |
1195 | .ident = "HP Compaq 6720s" , |
1196 | .matches = { |
1197 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard" ), |
1198 | DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s" ), |
1199 | }, |
1200 | /* PCI slot number of the controller */ |
1201 | .driver_data = (void *)0x1FUL, |
1202 | }, |
1203 | |
1204 | { } /* terminate list */ |
1205 | }; |
1206 | const struct dmi_system_id *dmi = dmi_first_match(list: broken_systems); |
1207 | |
1208 | if (dmi) { |
1209 | unsigned long slot = (unsigned long)dmi->driver_data; |
1210 | /* apply the quirk only to on-board controllers */ |
1211 | return slot == PCI_SLOT(pdev->devfn); |
1212 | } |
1213 | |
1214 | return false; |
1215 | } |
1216 | |
1217 | static bool ahci_broken_suspend(struct pci_dev *pdev) |
1218 | { |
1219 | static const struct dmi_system_id sysids[] = { |
1220 | /* |
1221 | * On HP dv[4-6] and HDX18 with earlier BIOSen, link |
1222 | * to the harddisk doesn't become online after |
1223 | * resuming from STR. Warn and fail suspend. |
1224 | * |
1225 | * http://bugzilla.kernel.org/show_bug.cgi?id=12276 |
1226 | * |
1227 | * Use dates instead of versions to match as HP is |
1228 | * apparently recycling both product and version |
1229 | * strings. |
1230 | * |
1231 | * http://bugzilla.kernel.org/show_bug.cgi?id=15462 |
1232 | */ |
1233 | { |
1234 | .ident = "dv4" , |
1235 | .matches = { |
1236 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard" ), |
1237 | DMI_MATCH(DMI_PRODUCT_NAME, |
1238 | "HP Pavilion dv4 Notebook PC" ), |
1239 | }, |
1240 | .driver_data = "20090105" , /* F.30 */ |
1241 | }, |
1242 | { |
1243 | .ident = "dv5" , |
1244 | .matches = { |
1245 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard" ), |
1246 | DMI_MATCH(DMI_PRODUCT_NAME, |
1247 | "HP Pavilion dv5 Notebook PC" ), |
1248 | }, |
1249 | .driver_data = "20090506" , /* F.16 */ |
1250 | }, |
1251 | { |
1252 | .ident = "dv6" , |
1253 | .matches = { |
1254 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard" ), |
1255 | DMI_MATCH(DMI_PRODUCT_NAME, |
1256 | "HP Pavilion dv6 Notebook PC" ), |
1257 | }, |
1258 | .driver_data = "20090423" , /* F.21 */ |
1259 | }, |
1260 | { |
1261 | .ident = "HDX18" , |
1262 | .matches = { |
1263 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard" ), |
1264 | DMI_MATCH(DMI_PRODUCT_NAME, |
1265 | "HP HDX18 Notebook PC" ), |
1266 | }, |
1267 | .driver_data = "20090430" , /* F.23 */ |
1268 | }, |
1269 | /* |
1270 | * Acer eMachines G725 has the same problem. BIOS |
1271 | * V1.03 is known to be broken. V3.04 is known to |
1272 | * work. Between, there are V1.06, V2.06 and V3.03 |
1273 | * that we don't have much idea about. For now, |
1274 | * blacklist anything older than V3.04. |
1275 | * |
1276 | * http://bugzilla.kernel.org/show_bug.cgi?id=15104 |
1277 | */ |
1278 | { |
1279 | .ident = "G725" , |
1280 | .matches = { |
1281 | DMI_MATCH(DMI_SYS_VENDOR, "eMachines" ), |
1282 | DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725" ), |
1283 | }, |
1284 | .driver_data = "20091216" , /* V3.04 */ |
1285 | }, |
1286 | { } /* terminate list */ |
1287 | }; |
1288 | const struct dmi_system_id *dmi = dmi_first_match(list: sysids); |
1289 | int year, month, date; |
1290 | char buf[9]; |
1291 | |
1292 | if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2)) |
1293 | return false; |
1294 | |
1295 | dmi_get_date(field: DMI_BIOS_DATE, yearp: &year, monthp: &month, dayp: &date); |
1296 | snprintf(buf, size: sizeof(buf), fmt: "%04d%02d%02d" , year, month, date); |
1297 | |
1298 | return strcmp(buf, dmi->driver_data) < 0; |
1299 | } |
1300 | |
1301 | static bool ahci_broken_lpm(struct pci_dev *pdev) |
1302 | { |
1303 | static const struct dmi_system_id sysids[] = { |
1304 | /* Various Lenovo 50 series have LPM issues with older BIOSen */ |
1305 | { |
1306 | .matches = { |
1307 | DMI_MATCH(DMI_SYS_VENDOR, "LENOVO" ), |
1308 | DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250" ), |
1309 | }, |
1310 | .driver_data = "20180406" , /* 1.31 */ |
1311 | }, |
1312 | { |
1313 | .matches = { |
1314 | DMI_MATCH(DMI_SYS_VENDOR, "LENOVO" ), |
1315 | DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450" ), |
1316 | }, |
1317 | .driver_data = "20180420" , /* 1.28 */ |
1318 | }, |
1319 | { |
1320 | .matches = { |
1321 | DMI_MATCH(DMI_SYS_VENDOR, "LENOVO" ), |
1322 | DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s" ), |
1323 | }, |
1324 | .driver_data = "20180315" , /* 1.33 */ |
1325 | }, |
1326 | { |
1327 | .matches = { |
1328 | DMI_MATCH(DMI_SYS_VENDOR, "LENOVO" ), |
1329 | DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541" ), |
1330 | }, |
1331 | /* |
1332 | * Note date based on release notes, 2.35 has been |
1333 | * reported to be good, but I've been unable to get |
1334 | * a hold of the reporter to get the DMI BIOS date. |
1335 | * TODO: fix this. |
1336 | */ |
1337 | .driver_data = "20180310" , /* 2.35 */ |
1338 | }, |
1339 | { } /* terminate list */ |
1340 | }; |
1341 | const struct dmi_system_id *dmi = dmi_first_match(list: sysids); |
1342 | int year, month, date; |
1343 | char buf[9]; |
1344 | |
1345 | if (!dmi) |
1346 | return false; |
1347 | |
1348 | dmi_get_date(field: DMI_BIOS_DATE, yearp: &year, monthp: &month, dayp: &date); |
1349 | snprintf(buf, size: sizeof(buf), fmt: "%04d%02d%02d" , year, month, date); |
1350 | |
1351 | return strcmp(buf, dmi->driver_data) < 0; |
1352 | } |
1353 | |
1354 | static bool ahci_broken_online(struct pci_dev *pdev) |
1355 | { |
1356 | #define ENCODE_BUSDEVFN(bus, slot, func) \ |
1357 | (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func))) |
1358 | static const struct dmi_system_id sysids[] = { |
1359 | /* |
1360 | * There are several gigabyte boards which use |
1361 | * SIMG5723s configured as hardware RAID. Certain |
1362 | * 5723 firmware revisions shipped there keep the link |
1363 | * online but fail to answer properly to SRST or |
1364 | * IDENTIFY when no device is attached downstream |
1365 | * causing libata to retry quite a few times leading |
1366 | * to excessive detection delay. |
1367 | * |
1368 | * As these firmwares respond to the second reset try |
1369 | * with invalid device signature, considering unknown |
1370 | * sig as offline works around the problem acceptably. |
1371 | */ |
1372 | { |
1373 | .ident = "EP45-DQ6" , |
1374 | .matches = { |
1375 | DMI_MATCH(DMI_BOARD_VENDOR, |
1376 | "Gigabyte Technology Co., Ltd." ), |
1377 | DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6" ), |
1378 | }, |
1379 | .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0), |
1380 | }, |
1381 | { |
1382 | .ident = "EP45-DS5" , |
1383 | .matches = { |
1384 | DMI_MATCH(DMI_BOARD_VENDOR, |
1385 | "Gigabyte Technology Co., Ltd." ), |
1386 | DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5" ), |
1387 | }, |
1388 | .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0), |
1389 | }, |
1390 | { } /* terminate list */ |
1391 | }; |
1392 | #undef ENCODE_BUSDEVFN |
1393 | const struct dmi_system_id *dmi = dmi_first_match(list: sysids); |
1394 | unsigned int val; |
1395 | |
1396 | if (!dmi) |
1397 | return false; |
1398 | |
1399 | val = (unsigned long)dmi->driver_data; |
1400 | |
1401 | return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff); |
1402 | } |
1403 | |
1404 | static bool ahci_broken_devslp(struct pci_dev *pdev) |
1405 | { |
1406 | /* device with broken DEVSLP but still showing SDS capability */ |
1407 | static const struct pci_device_id ids[] = { |
1408 | { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */ |
1409 | {} |
1410 | }; |
1411 | |
1412 | return pci_match_id(ids, dev: pdev); |
1413 | } |
1414 | |
1415 | #ifdef CONFIG_ATA_ACPI |
1416 | static void ahci_gtf_filter_workaround(struct ata_host *host) |
1417 | { |
1418 | static const struct dmi_system_id sysids[] = { |
1419 | /* |
1420 | * Aspire 3810T issues a bunch of SATA enable commands |
1421 | * via _GTF including an invalid one and one which is |
1422 | * rejected by the device. Among the successful ones |
1423 | * is FPDMA non-zero offset enable which when enabled |
1424 | * only on the drive side leads to NCQ command |
1425 | * failures. Filter it out. |
1426 | */ |
1427 | { |
1428 | .ident = "Aspire 3810T" , |
1429 | .matches = { |
1430 | DMI_MATCH(DMI_SYS_VENDOR, "Acer" ), |
1431 | DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T" ), |
1432 | }, |
1433 | .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET, |
1434 | }, |
1435 | { } |
1436 | }; |
1437 | const struct dmi_system_id *dmi = dmi_first_match(list: sysids); |
1438 | unsigned int filter; |
1439 | int i; |
1440 | |
1441 | if (!dmi) |
1442 | return; |
1443 | |
1444 | filter = (unsigned long)dmi->driver_data; |
1445 | dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n" , |
1446 | filter, dmi->ident); |
1447 | |
1448 | for (i = 0; i < host->n_ports; i++) { |
1449 | struct ata_port *ap = host->ports[i]; |
1450 | struct ata_link *link; |
1451 | struct ata_device *dev; |
1452 | |
1453 | ata_for_each_link(link, ap, EDGE) |
1454 | ata_for_each_dev(dev, link, ALL) |
1455 | dev->gtf_filter |= filter; |
1456 | } |
1457 | } |
1458 | #else |
1459 | static inline void ahci_gtf_filter_workaround(struct ata_host *host) |
1460 | {} |
1461 | #endif |
1462 | |
1463 | /* |
1464 | * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected |
1465 | * as DUMMY, or detected but eventually get a "link down" and never get up |
1466 | * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the |
1467 | * port_map may hold a value of 0x00. |
1468 | * |
1469 | * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports |
1470 | * and can significantly reduce the occurrence of the problem. |
1471 | * |
1472 | * https://bugzilla.kernel.org/show_bug.cgi?id=189471 |
1473 | */ |
1474 | static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv, |
1475 | struct pci_dev *pdev) |
1476 | { |
1477 | static const struct dmi_system_id sysids[] = { |
1478 | { |
1479 | .ident = "Acer Switch Alpha 12" , |
1480 | .matches = { |
1481 | DMI_MATCH(DMI_SYS_VENDOR, "Acer" ), |
1482 | DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271" ) |
1483 | }, |
1484 | }, |
1485 | { } |
1486 | }; |
1487 | |
1488 | if (dmi_check_system(list: sysids)) { |
1489 | dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n" ); |
1490 | if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) { |
1491 | hpriv->port_map = 0x7; |
1492 | hpriv->cap = 0xC734FF02; |
1493 | } |
1494 | } |
1495 | } |
1496 | |
1497 | #ifdef CONFIG_ARM64 |
1498 | /* |
1499 | * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently. |
1500 | * Workaround is to make sure all pending IRQs are served before leaving |
1501 | * handler. |
1502 | */ |
1503 | static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance) |
1504 | { |
1505 | struct ata_host *host = dev_instance; |
1506 | struct ahci_host_priv *hpriv; |
1507 | unsigned int rc = 0; |
1508 | void __iomem *mmio; |
1509 | u32 irq_stat, irq_masked; |
1510 | unsigned int handled = 1; |
1511 | |
1512 | hpriv = host->private_data; |
1513 | mmio = hpriv->mmio; |
1514 | irq_stat = readl(mmio + HOST_IRQ_STAT); |
1515 | if (!irq_stat) |
1516 | return IRQ_NONE; |
1517 | |
1518 | do { |
1519 | irq_masked = irq_stat & hpriv->port_map; |
1520 | spin_lock(&host->lock); |
1521 | rc = ahci_handle_port_intr(host, irq_masked); |
1522 | if (!rc) |
1523 | handled = 0; |
1524 | writel(irq_stat, mmio + HOST_IRQ_STAT); |
1525 | irq_stat = readl(mmio + HOST_IRQ_STAT); |
1526 | spin_unlock(&host->lock); |
1527 | } while (irq_stat); |
1528 | |
1529 | return IRQ_RETVAL(handled); |
1530 | } |
1531 | #endif |
1532 | |
1533 | static void ahci_remap_check(struct pci_dev *pdev, int bar, |
1534 | struct ahci_host_priv *hpriv) |
1535 | { |
1536 | int i; |
1537 | u32 cap; |
1538 | |
1539 | /* |
1540 | * Check if this device might have remapped nvme devices. |
1541 | */ |
1542 | if (pdev->vendor != PCI_VENDOR_ID_INTEL || |
1543 | pci_resource_len(pdev, bar) < SZ_512K || |
1544 | bar != AHCI_PCI_BAR_STANDARD || |
1545 | !(readl(addr: hpriv->mmio + AHCI_VSCAP) & 1)) |
1546 | return; |
1547 | |
1548 | cap = readq(addr: hpriv->mmio + AHCI_REMAP_CAP); |
1549 | for (i = 0; i < AHCI_MAX_REMAP; i++) { |
1550 | if ((cap & (1 << i)) == 0) |
1551 | continue; |
1552 | if (readl(addr: hpriv->mmio + ahci_remap_dcc(i)) |
1553 | != PCI_CLASS_STORAGE_EXPRESS) |
1554 | continue; |
1555 | |
1556 | /* We've found a remapped device */ |
1557 | hpriv->remapped_nvme++; |
1558 | } |
1559 | |
1560 | if (!hpriv->remapped_nvme) |
1561 | return; |
1562 | |
1563 | dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n" , |
1564 | hpriv->remapped_nvme); |
1565 | dev_warn(&pdev->dev, |
1566 | "Switch your BIOS from RAID to AHCI mode to use them.\n" ); |
1567 | |
1568 | /* |
1569 | * Don't rely on the msi-x capability in the remap case, |
1570 | * share the legacy interrupt across ahci and remapped devices. |
1571 | */ |
1572 | hpriv->flags |= AHCI_HFLAG_NO_MSI; |
1573 | } |
1574 | |
1575 | static int ahci_get_irq_vector(struct ata_host *host, int port) |
1576 | { |
1577 | return pci_irq_vector(to_pci_dev(host->dev), nr: port); |
1578 | } |
1579 | |
1580 | static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports, |
1581 | struct ahci_host_priv *hpriv) |
1582 | { |
1583 | int nvec; |
1584 | |
1585 | if (hpriv->flags & AHCI_HFLAG_NO_MSI) |
1586 | return -ENODEV; |
1587 | |
1588 | /* |
1589 | * If number of MSIs is less than number of ports then Sharing Last |
1590 | * Message mode could be enforced. In this case assume that advantage |
1591 | * of multipe MSIs is negated and use single MSI mode instead. |
1592 | */ |
1593 | if (n_ports > 1) { |
1594 | nvec = pci_alloc_irq_vectors(dev: pdev, min_vecs: n_ports, INT_MAX, |
1595 | PCI_IRQ_MSIX | PCI_IRQ_MSI); |
1596 | if (nvec > 0) { |
1597 | if (!(readl(addr: hpriv->mmio + HOST_CTL) & HOST_MRSM)) { |
1598 | hpriv->get_irq_vector = ahci_get_irq_vector; |
1599 | hpriv->flags |= AHCI_HFLAG_MULTI_MSI; |
1600 | return nvec; |
1601 | } |
1602 | |
1603 | /* |
1604 | * Fallback to single MSI mode if the controller |
1605 | * enforced MRSM mode. |
1606 | */ |
1607 | printk(KERN_INFO |
1608 | "ahci: MRSM is on, fallback to single MSI\n" ); |
1609 | pci_free_irq_vectors(dev: pdev); |
1610 | } |
1611 | } |
1612 | |
1613 | /* |
1614 | * If the host is not capable of supporting per-port vectors, fall |
1615 | * back to single MSI before finally attempting single MSI-X. |
1616 | */ |
1617 | nvec = pci_alloc_irq_vectors(dev: pdev, min_vecs: 1, max_vecs: 1, PCI_IRQ_MSI); |
1618 | if (nvec == 1) |
1619 | return nvec; |
1620 | return pci_alloc_irq_vectors(dev: pdev, min_vecs: 1, max_vecs: 1, PCI_IRQ_MSIX); |
1621 | } |
1622 | |
1623 | static void ahci_update_initial_lpm_policy(struct ata_port *ap, |
1624 | struct ahci_host_priv *hpriv) |
1625 | { |
1626 | int policy = CONFIG_SATA_MOBILE_LPM_POLICY; |
1627 | |
1628 | |
1629 | /* Ignore processing for chipsets that don't use policy */ |
1630 | if (!(hpriv->flags & AHCI_HFLAG_USE_LPM_POLICY)) |
1631 | return; |
1632 | |
1633 | /* user modified policy via module param */ |
1634 | if (mobile_lpm_policy != -1) { |
1635 | policy = mobile_lpm_policy; |
1636 | goto update_policy; |
1637 | } |
1638 | |
1639 | if (policy > ATA_LPM_MED_POWER && pm_suspend_default_s2idle()) { |
1640 | if (hpriv->cap & HOST_CAP_PART) |
1641 | policy = ATA_LPM_MIN_POWER_WITH_PARTIAL; |
1642 | else if (hpriv->cap & HOST_CAP_SSC) |
1643 | policy = ATA_LPM_MIN_POWER; |
1644 | } |
1645 | |
1646 | update_policy: |
1647 | if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER) |
1648 | ap->target_lpm_policy = policy; |
1649 | } |
1650 | |
1651 | static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv) |
1652 | { |
1653 | const struct pci_device_id *id = pci_match_id(ids: ahci_pci_tbl, dev: pdev); |
1654 | u16 tmp16; |
1655 | |
1656 | /* |
1657 | * Only apply the 6-port PCS quirk for known legacy platforms. |
1658 | */ |
1659 | if (!id || id->vendor != PCI_VENDOR_ID_INTEL) |
1660 | return; |
1661 | |
1662 | /* Skip applying the quirk on Denverton and beyond */ |
1663 | if (((enum board_ids) id->driver_data) >= board_ahci_pcs7) |
1664 | return; |
1665 | |
1666 | /* |
1667 | * port_map is determined from PORTS_IMPL PCI register which is |
1668 | * implemented as write or write-once register. If the register |
1669 | * isn't programmed, ahci automatically generates it from number |
1670 | * of ports, which is good enough for PCS programming. It is |
1671 | * otherwise expected that platform firmware enables the ports |
1672 | * before the OS boots. |
1673 | */ |
1674 | pci_read_config_word(dev: pdev, where: PCS_6, val: &tmp16); |
1675 | if ((tmp16 & hpriv->port_map) != hpriv->port_map) { |
1676 | tmp16 |= hpriv->port_map; |
1677 | pci_write_config_word(dev: pdev, where: PCS_6, val: tmp16); |
1678 | } |
1679 | } |
1680 | |
1681 | static ssize_t remapped_nvme_show(struct device *dev, |
1682 | struct device_attribute *attr, |
1683 | char *buf) |
1684 | { |
1685 | struct ata_host *host = dev_get_drvdata(dev); |
1686 | struct ahci_host_priv *hpriv = host->private_data; |
1687 | |
1688 | return sysfs_emit(buf, fmt: "%u\n" , hpriv->remapped_nvme); |
1689 | } |
1690 | |
1691 | static DEVICE_ATTR_RO(remapped_nvme); |
1692 | |
1693 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1694 | { |
1695 | unsigned int board_id = ent->driver_data; |
1696 | struct ata_port_info pi = ahci_port_info[board_id]; |
1697 | const struct ata_port_info *ppi[] = { &pi, NULL }; |
1698 | struct device *dev = &pdev->dev; |
1699 | struct ahci_host_priv *hpriv; |
1700 | struct ata_host *host; |
1701 | int n_ports, i, rc; |
1702 | int ahci_pci_bar = AHCI_PCI_BAR_STANDARD; |
1703 | |
1704 | WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS); |
1705 | |
1706 | ata_print_version_once(&pdev->dev, DRV_VERSION); |
1707 | |
1708 | /* The AHCI driver can only drive the SATA ports, the PATA driver |
1709 | can drive them all so if both drivers are selected make sure |
1710 | AHCI stays out of the way */ |
1711 | if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable) |
1712 | return -ENODEV; |
1713 | |
1714 | /* Apple BIOS on MCP89 prevents us using AHCI */ |
1715 | if (is_mcp89_apple(pdev)) |
1716 | ahci_mcp89_apple_enable(pdev); |
1717 | |
1718 | /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode. |
1719 | * At the moment, we can only use the AHCI mode. Let the users know |
1720 | * that for SAS drives they're out of luck. |
1721 | */ |
1722 | if (pdev->vendor == PCI_VENDOR_ID_PROMISE) |
1723 | dev_info(&pdev->dev, |
1724 | "PDC42819 can only drive SATA devices with this driver\n" ); |
1725 | |
1726 | /* Some devices use non-standard BARs */ |
1727 | if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06) |
1728 | ahci_pci_bar = AHCI_PCI_BAR_STA2X11; |
1729 | else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000) |
1730 | ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS; |
1731 | else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) { |
1732 | if (pdev->device == 0xa01c) |
1733 | ahci_pci_bar = AHCI_PCI_BAR_CAVIUM; |
1734 | if (pdev->device == 0xa084) |
1735 | ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5; |
1736 | } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) { |
1737 | if (pdev->device == 0x7a08) |
1738 | ahci_pci_bar = AHCI_PCI_BAR_LOONGSON; |
1739 | } |
1740 | |
1741 | /* acquire resources */ |
1742 | rc = pcim_enable_device(pdev); |
1743 | if (rc) |
1744 | return rc; |
1745 | |
1746 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
1747 | (pdev->device == 0x2652 || pdev->device == 0x2653)) { |
1748 | u8 map; |
1749 | |
1750 | /* ICH6s share the same PCI ID for both piix and ahci |
1751 | * modes. Enabling ahci mode while MAP indicates |
1752 | * combined mode is a bad idea. Yield to ata_piix. |
1753 | */ |
1754 | pci_read_config_byte(dev: pdev, where: ICH_MAP, val: &map); |
1755 | if (map & 0x3) { |
1756 | dev_info(&pdev->dev, |
1757 | "controller is in combined mode, can't enable AHCI mode\n" ); |
1758 | return -ENODEV; |
1759 | } |
1760 | } |
1761 | |
1762 | /* AHCI controllers often implement SFF compatible interface. |
1763 | * Grab all PCI BARs just in case. |
1764 | */ |
1765 | rc = pcim_iomap_regions_request_all(pdev, mask: 1 << ahci_pci_bar, DRV_NAME); |
1766 | if (rc == -EBUSY) |
1767 | pcim_pin_device(pdev); |
1768 | if (rc) |
1769 | return rc; |
1770 | |
1771 | hpriv = devm_kzalloc(dev, size: sizeof(*hpriv), GFP_KERNEL); |
1772 | if (!hpriv) |
1773 | return -ENOMEM; |
1774 | hpriv->flags |= (unsigned long)pi.private_data; |
1775 | |
1776 | /* MCP65 revision A1 and A2 can't do MSI */ |
1777 | if (board_id == board_ahci_mcp65 && |
1778 | (pdev->revision == 0xa1 || pdev->revision == 0xa2)) |
1779 | hpriv->flags |= AHCI_HFLAG_NO_MSI; |
1780 | |
1781 | /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */ |
1782 | if (board_id == board_ahci_sb700 && pdev->revision >= 0x40) |
1783 | hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL; |
1784 | |
1785 | /* only some SB600s can do 64bit DMA */ |
1786 | if (ahci_sb600_enable_64bit(pdev)) |
1787 | hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY; |
1788 | |
1789 | hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar]; |
1790 | |
1791 | /* detect remapped nvme devices */ |
1792 | ahci_remap_check(pdev, bar: ahci_pci_bar, hpriv); |
1793 | |
1794 | sysfs_add_file_to_group(kobj: &pdev->dev.kobj, |
1795 | attr: &dev_attr_remapped_nvme.attr, |
1796 | NULL); |
1797 | |
1798 | /* must set flag prior to save config in order to take effect */ |
1799 | if (ahci_broken_devslp(pdev)) |
1800 | hpriv->flags |= AHCI_HFLAG_NO_DEVSLP; |
1801 | |
1802 | #ifdef CONFIG_ARM64 |
1803 | if (pdev->vendor == PCI_VENDOR_ID_HUAWEI && |
1804 | pdev->device == 0xa235 && |
1805 | pdev->revision < 0x30) |
1806 | hpriv->flags |= AHCI_HFLAG_NO_SXS; |
1807 | |
1808 | if (pdev->vendor == 0x177d && pdev->device == 0xa01c) |
1809 | hpriv->irq_handler = ahci_thunderx_irq_handler; |
1810 | #endif |
1811 | |
1812 | /* save initial config */ |
1813 | ahci_pci_save_initial_config(pdev, hpriv); |
1814 | |
1815 | /* prepare host */ |
1816 | if (hpriv->cap & HOST_CAP_NCQ) { |
1817 | pi.flags |= ATA_FLAG_NCQ; |
1818 | /* |
1819 | * Auto-activate optimization is supposed to be |
1820 | * supported on all AHCI controllers indicating NCQ |
1821 | * capability, but it seems to be broken on some |
1822 | * chipsets including NVIDIAs. |
1823 | */ |
1824 | if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA)) |
1825 | pi.flags |= ATA_FLAG_FPDMA_AA; |
1826 | |
1827 | /* |
1828 | * All AHCI controllers should be forward-compatible |
1829 | * with the new auxiliary field. This code should be |
1830 | * conditionalized if any buggy AHCI controllers are |
1831 | * encountered. |
1832 | */ |
1833 | pi.flags |= ATA_FLAG_FPDMA_AUX; |
1834 | } |
1835 | |
1836 | if (hpriv->cap & HOST_CAP_PMP) |
1837 | pi.flags |= ATA_FLAG_PMP; |
1838 | |
1839 | ahci_set_em_messages(hpriv, pi: &pi); |
1840 | |
1841 | if (ahci_broken_system_poweroff(pdev)) { |
1842 | pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN; |
1843 | dev_info(&pdev->dev, |
1844 | "quirky BIOS, skipping spindown on poweroff\n" ); |
1845 | } |
1846 | |
1847 | if (ahci_broken_lpm(pdev)) { |
1848 | pi.flags |= ATA_FLAG_NO_LPM; |
1849 | dev_warn(&pdev->dev, |
1850 | "BIOS update required for Link Power Management support\n" ); |
1851 | } |
1852 | |
1853 | if (ahci_broken_suspend(pdev)) { |
1854 | hpriv->flags |= AHCI_HFLAG_NO_SUSPEND; |
1855 | dev_warn(&pdev->dev, |
1856 | "BIOS update required for suspend/resume\n" ); |
1857 | } |
1858 | |
1859 | if (ahci_broken_online(pdev)) { |
1860 | hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE; |
1861 | dev_info(&pdev->dev, |
1862 | "online status unreliable, applying workaround\n" ); |
1863 | } |
1864 | |
1865 | |
1866 | /* Acer SA5-271 workaround modifies private_data */ |
1867 | acer_sa5_271_workaround(hpriv, pdev); |
1868 | |
1869 | /* CAP.NP sometimes indicate the index of the last enabled |
1870 | * port, at other times, that of the last possible port, so |
1871 | * determining the maximum port number requires looking at |
1872 | * both CAP.NP and port_map. |
1873 | */ |
1874 | n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); |
1875 | |
1876 | host = ata_host_alloc_pinfo(dev: &pdev->dev, ppi, n_ports); |
1877 | if (!host) |
1878 | return -ENOMEM; |
1879 | host->private_data = hpriv; |
1880 | |
1881 | if (ahci_init_msi(pdev, n_ports, hpriv) < 0) { |
1882 | /* legacy intx interrupts */ |
1883 | pci_intx(dev: pdev, enable: 1); |
1884 | } |
1885 | hpriv->irq = pci_irq_vector(dev: pdev, nr: 0); |
1886 | |
1887 | if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) |
1888 | host->flags |= ATA_HOST_PARALLEL_SCAN; |
1889 | else |
1890 | dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n" ); |
1891 | |
1892 | if (!(hpriv->cap & HOST_CAP_PART)) |
1893 | host->flags |= ATA_HOST_NO_PART; |
1894 | |
1895 | if (!(hpriv->cap & HOST_CAP_SSC)) |
1896 | host->flags |= ATA_HOST_NO_SSC; |
1897 | |
1898 | if (!(hpriv->cap2 & HOST_CAP2_SDS)) |
1899 | host->flags |= ATA_HOST_NO_DEVSLP; |
1900 | |
1901 | if (pi.flags & ATA_FLAG_EM) |
1902 | ahci_reset_em(host); |
1903 | |
1904 | for (i = 0; i < host->n_ports; i++) { |
1905 | struct ata_port *ap = host->ports[i]; |
1906 | |
1907 | ata_port_pbar_desc(ap, bar: ahci_pci_bar, offset: -1, name: "abar" ); |
1908 | ata_port_pbar_desc(ap, bar: ahci_pci_bar, |
1909 | offset: 0x100 + ap->port_no * 0x80, name: "port" ); |
1910 | |
1911 | /* set enclosure management message type */ |
1912 | if (ap->flags & ATA_FLAG_EM) |
1913 | ap->em_message_type = hpriv->em_msg_type; |
1914 | |
1915 | ahci_update_initial_lpm_policy(ap, hpriv); |
1916 | |
1917 | /* disabled/not-implemented port */ |
1918 | if (!(hpriv->port_map & (1 << i))) |
1919 | ap->ops = &ata_dummy_port_ops; |
1920 | } |
1921 | |
1922 | /* apply workaround for ASUS P5W DH Deluxe mainboard */ |
1923 | ahci_p5wdh_workaround(host); |
1924 | |
1925 | /* apply gtf filter quirk */ |
1926 | ahci_gtf_filter_workaround(host); |
1927 | |
1928 | /* initialize adapter */ |
1929 | rc = ahci_configure_dma_masks(pdev, using_dac: hpriv->cap & HOST_CAP_64); |
1930 | if (rc) |
1931 | return rc; |
1932 | |
1933 | rc = ahci_pci_reset_controller(host); |
1934 | if (rc) |
1935 | return rc; |
1936 | |
1937 | ahci_pci_init_controller(host); |
1938 | ahci_pci_print_info(host); |
1939 | |
1940 | pci_set_master(dev: pdev); |
1941 | |
1942 | rc = ahci_host_activate(host, sht: &ahci_sht); |
1943 | if (rc) |
1944 | return rc; |
1945 | |
1946 | pm_runtime_put_noidle(dev: &pdev->dev); |
1947 | return 0; |
1948 | } |
1949 | |
1950 | static void ahci_shutdown_one(struct pci_dev *pdev) |
1951 | { |
1952 | ata_pci_shutdown_one(pdev); |
1953 | } |
1954 | |
1955 | static void ahci_remove_one(struct pci_dev *pdev) |
1956 | { |
1957 | sysfs_remove_file_from_group(kobj: &pdev->dev.kobj, |
1958 | attr: &dev_attr_remapped_nvme.attr, |
1959 | NULL); |
1960 | pm_runtime_get_noresume(dev: &pdev->dev); |
1961 | ata_pci_remove_one(pdev); |
1962 | } |
1963 | |
1964 | module_pci_driver(ahci_pci_driver); |
1965 | |
1966 | MODULE_AUTHOR("Jeff Garzik" ); |
1967 | MODULE_DESCRIPTION("AHCI SATA low-level driver" ); |
1968 | MODULE_LICENSE("GPL" ); |
1969 | MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); |
1970 | MODULE_VERSION(DRV_VERSION); |
1971 | |