1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * ahci.h - Common AHCI SATA definitions and declarations |
4 | * |
5 | * Maintained by: Tejun Heo <tj@kernel.org> |
6 | * Please ALWAYS copy linux-ide@vger.kernel.org |
7 | * on emails. |
8 | * |
9 | * Copyright 2004-2005 Red Hat, Inc. |
10 | * |
11 | * libata documentation is available via 'make {ps|pdf}docs', |
12 | * as Documentation/driver-api/libata.rst |
13 | * |
14 | * AHCI hardware documentation: |
15 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
16 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
17 | */ |
18 | |
19 | #ifndef _AHCI_H |
20 | #define _AHCI_H |
21 | |
22 | #include <linux/pci.h> |
23 | #include <linux/clk.h> |
24 | #include <linux/libata.h> |
25 | #include <linux/phy/phy.h> |
26 | #include <linux/regulator/consumer.h> |
27 | #include <linux/bits.h> |
28 | |
29 | /* Enclosure Management Control */ |
30 | #define EM_CTRL_MSG_TYPE 0x000f0000 |
31 | |
32 | /* Enclosure Management LED Message Type */ |
33 | #define EM_MSG_LED_HBA_PORT 0x0000000f |
34 | #define EM_MSG_LED_PMP_SLOT 0x0000ff00 |
35 | #define EM_MSG_LED_VALUE 0xffff0000 |
36 | #define EM_MSG_LED_VALUE_ACTIVITY 0x00070000 |
37 | #define EM_MSG_LED_VALUE_OFF 0xfff80000 |
38 | #define EM_MSG_LED_VALUE_ON 0x00010000 |
39 | |
40 | enum { |
41 | AHCI_MAX_PORTS = 32, |
42 | AHCI_MAX_SG = 168, /* hardware max is 64K */ |
43 | AHCI_DMA_BOUNDARY = 0xffffffff, |
44 | AHCI_MAX_CMDS = 32, |
45 | AHCI_CMD_SZ = 32, |
46 | AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, |
47 | AHCI_RX_FIS_SZ = 256, |
48 | AHCI_CMD_TBL_CDB = 0x40, |
49 | AHCI_CMD_TBL_HDR_SZ = 0x80, |
50 | AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), |
51 | AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, |
52 | AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + |
53 | AHCI_RX_FIS_SZ, |
54 | AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ + |
55 | AHCI_CMD_TBL_AR_SZ + |
56 | (AHCI_RX_FIS_SZ * 16), |
57 | AHCI_IRQ_ON_SG = BIT(31), |
58 | AHCI_CMD_ATAPI = BIT(5), |
59 | AHCI_CMD_WRITE = BIT(6), |
60 | AHCI_CMD_PREFETCH = BIT(7), |
61 | AHCI_CMD_RESET = BIT(8), |
62 | AHCI_CMD_CLR_BUSY = BIT(10), |
63 | |
64 | RX_FIS_PIO_SETUP = 0x20, /* offset of PIO Setup FIS data */ |
65 | RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ |
66 | RX_FIS_SDB = 0x58, /* offset of SDB FIS data */ |
67 | RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ |
68 | |
69 | /* global controller registers */ |
70 | HOST_CAP = 0x00, /* host capabilities */ |
71 | HOST_CTL = 0x04, /* global host control */ |
72 | HOST_IRQ_STAT = 0x08, /* interrupt status */ |
73 | HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ |
74 | HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ |
75 | HOST_EM_LOC = 0x1c, /* Enclosure Management location */ |
76 | HOST_EM_CTL = 0x20, /* Enclosure Management Control */ |
77 | HOST_CAP2 = 0x24, /* host capabilities, extended */ |
78 | |
79 | /* HOST_CTL bits */ |
80 | HOST_RESET = BIT(0), /* reset controller; self-clear */ |
81 | HOST_IRQ_EN = BIT(1), /* global IRQ enable */ |
82 | HOST_MRSM = BIT(2), /* MSI Revert to Single Message */ |
83 | HOST_AHCI_EN = BIT(31), /* AHCI enabled */ |
84 | |
85 | /* HOST_CAP bits */ |
86 | HOST_CAP_SXS = BIT(5), /* Supports External SATA */ |
87 | HOST_CAP_EMS = BIT(6), /* Enclosure Management support */ |
88 | HOST_CAP_CCC = BIT(7), /* Command Completion Coalescing */ |
89 | HOST_CAP_PART = BIT(13), /* Partial state capable */ |
90 | HOST_CAP_SSC = BIT(14), /* Slumber state capable */ |
91 | HOST_CAP_PIO_MULTI = BIT(15), /* PIO multiple DRQ support */ |
92 | HOST_CAP_FBS = BIT(16), /* FIS-based switching support */ |
93 | HOST_CAP_PMP = BIT(17), /* Port Multiplier support */ |
94 | HOST_CAP_ONLY = BIT(18), /* Supports AHCI mode only */ |
95 | HOST_CAP_CLO = BIT(24), /* Command List Override support */ |
96 | HOST_CAP_LED = BIT(25), /* Supports activity LED */ |
97 | HOST_CAP_ALPM = BIT(26), /* Aggressive Link PM support */ |
98 | HOST_CAP_SSS = BIT(27), /* Staggered Spin-up */ |
99 | HOST_CAP_MPS = BIT(28), /* Mechanical presence switch */ |
100 | HOST_CAP_SNTF = BIT(29), /* SNotification register */ |
101 | HOST_CAP_NCQ = BIT(30), /* Native Command Queueing */ |
102 | HOST_CAP_64 = BIT(31), /* PCI DAC (64-bit DMA) support */ |
103 | |
104 | /* HOST_CAP2 bits */ |
105 | HOST_CAP2_BOH = BIT(0), /* BIOS/OS handoff supported */ |
106 | HOST_CAP2_NVMHCI = BIT(1), /* NVMHCI supported */ |
107 | HOST_CAP2_APST = BIT(2), /* Automatic partial to slumber */ |
108 | HOST_CAP2_SDS = BIT(3), /* Support device sleep */ |
109 | HOST_CAP2_SADM = BIT(4), /* Support aggressive DevSlp */ |
110 | HOST_CAP2_DESO = BIT(5), /* DevSlp from slumber only */ |
111 | |
112 | /* registers for each SATA port */ |
113 | PORT_LST_ADDR = 0x00, /* command list DMA addr */ |
114 | PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ |
115 | PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ |
116 | PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ |
117 | PORT_IRQ_STAT = 0x10, /* interrupt status */ |
118 | PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ |
119 | PORT_CMD = 0x18, /* port command */ |
120 | PORT_TFDATA = 0x20, /* taskfile data */ |
121 | PORT_SIG = 0x24, /* device TF signature */ |
122 | PORT_CMD_ISSUE = 0x38, /* command issue */ |
123 | PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ |
124 | PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ |
125 | PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ |
126 | PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ |
127 | PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */ |
128 | PORT_FBS = 0x40, /* FIS-based Switching */ |
129 | PORT_DEVSLP = 0x44, /* device sleep */ |
130 | |
131 | /* PORT_IRQ_{STAT,MASK} bits */ |
132 | PORT_IRQ_COLD_PRES = BIT(31), /* cold presence detect */ |
133 | PORT_IRQ_TF_ERR = BIT(30), /* task file error */ |
134 | PORT_IRQ_HBUS_ERR = BIT(29), /* host bus fatal error */ |
135 | PORT_IRQ_HBUS_DATA_ERR = BIT(28), /* host bus data error */ |
136 | PORT_IRQ_IF_ERR = BIT(27), /* interface fatal error */ |
137 | PORT_IRQ_IF_NONFATAL = BIT(26), /* interface non-fatal error */ |
138 | PORT_IRQ_OVERFLOW = BIT(24), /* xfer exhausted available S/G */ |
139 | PORT_IRQ_BAD_PMP = BIT(23), /* incorrect port multiplier */ |
140 | |
141 | PORT_IRQ_PHYRDY = BIT(22), /* PhyRdy changed */ |
142 | PORT_IRQ_DMPS = BIT(7), /* mechanical presence status */ |
143 | PORT_IRQ_CONNECT = BIT(6), /* port connect change status */ |
144 | PORT_IRQ_SG_DONE = BIT(5), /* descriptor processed */ |
145 | PORT_IRQ_UNK_FIS = BIT(4), /* unknown FIS rx'd */ |
146 | PORT_IRQ_SDB_FIS = BIT(3), /* Set Device Bits FIS rx'd */ |
147 | PORT_IRQ_DMAS_FIS = BIT(2), /* DMA Setup FIS rx'd */ |
148 | PORT_IRQ_PIOS_FIS = BIT(1), /* PIO Setup FIS rx'd */ |
149 | PORT_IRQ_D2H_REG_FIS = BIT(0), /* D2H Register FIS rx'd */ |
150 | |
151 | PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | |
152 | PORT_IRQ_IF_ERR | |
153 | PORT_IRQ_CONNECT | |
154 | PORT_IRQ_PHYRDY | |
155 | PORT_IRQ_UNK_FIS | |
156 | PORT_IRQ_BAD_PMP, |
157 | PORT_IRQ_ERROR = PORT_IRQ_FREEZE | |
158 | PORT_IRQ_TF_ERR | |
159 | PORT_IRQ_HBUS_DATA_ERR, |
160 | DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | |
161 | PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | |
162 | PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, |
163 | |
164 | /* PORT_CMD bits */ |
165 | PORT_CMD_ASP = BIT(27), /* Aggressive Slumber/Partial */ |
166 | PORT_CMD_ALPE = BIT(26), /* Aggressive Link PM enable */ |
167 | PORT_CMD_ATAPI = BIT(24), /* Device is ATAPI */ |
168 | PORT_CMD_FBSCP = BIT(22), /* FBS Capable Port */ |
169 | PORT_CMD_ESP = BIT(21), /* External Sata Port */ |
170 | PORT_CMD_CPD = BIT(20), /* Cold Presence Detection */ |
171 | PORT_CMD_MPSP = BIT(19), /* Mechanical Presence Switch */ |
172 | PORT_CMD_HPCP = BIT(18), /* HotPlug Capable Port */ |
173 | PORT_CMD_PMP = BIT(17), /* PMP attached */ |
174 | PORT_CMD_LIST_ON = BIT(15), /* cmd list DMA engine running */ |
175 | PORT_CMD_FIS_ON = BIT(14), /* FIS DMA engine running */ |
176 | PORT_CMD_FIS_RX = BIT(4), /* Enable FIS receive DMA engine */ |
177 | PORT_CMD_CLO = BIT(3), /* Command list override */ |
178 | PORT_CMD_POWER_ON = BIT(2), /* Power up device */ |
179 | PORT_CMD_SPIN_UP = BIT(1), /* Spin up device */ |
180 | PORT_CMD_START = BIT(0), /* Enable port DMA engine */ |
181 | |
182 | PORT_CMD_ICC_MASK = (0xfu << 28), /* i/f ICC state mask */ |
183 | PORT_CMD_ICC_ACTIVE = (0x1u << 28), /* Put i/f in active state */ |
184 | PORT_CMD_ICC_PARTIAL = (0x2u << 28), /* Put i/f in partial state */ |
185 | PORT_CMD_ICC_SLUMBER = (0x6u << 28), /* Put i/f in slumber state */ |
186 | |
187 | /* PORT_CMD capabilities mask */ |
188 | PORT_CMD_CAP = PORT_CMD_HPCP | PORT_CMD_MPSP | |
189 | PORT_CMD_CPD | PORT_CMD_ESP | PORT_CMD_FBSCP, |
190 | |
191 | /* PORT_FBS bits */ |
192 | PORT_FBS_DWE_OFFSET = 16, /* FBS device with error offset */ |
193 | PORT_FBS_ADO_OFFSET = 12, /* FBS active dev optimization offset */ |
194 | PORT_FBS_DEV_OFFSET = 8, /* FBS device to issue offset */ |
195 | PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET), /* FBS.DEV */ |
196 | PORT_FBS_SDE = BIT(2), /* FBS single device error */ |
197 | PORT_FBS_DEC = BIT(1), /* FBS device error clear */ |
198 | PORT_FBS_EN = BIT(0), /* Enable FBS */ |
199 | |
200 | /* PORT_DEVSLP bits */ |
201 | PORT_DEVSLP_DM_OFFSET = 25, /* DITO multiplier offset */ |
202 | PORT_DEVSLP_DM_MASK = (0xf << 25), /* DITO multiplier mask */ |
203 | PORT_DEVSLP_DITO_OFFSET = 15, /* DITO offset */ |
204 | PORT_DEVSLP_MDAT_OFFSET = 10, /* Minimum assertion time */ |
205 | PORT_DEVSLP_DETO_OFFSET = 2, /* DevSlp exit timeout */ |
206 | PORT_DEVSLP_DSP = BIT(1), /* DevSlp present */ |
207 | PORT_DEVSLP_ADSE = BIT(0), /* Aggressive DevSlp enable */ |
208 | |
209 | /* hpriv->flags bits */ |
210 | |
211 | #define AHCI_HFLAGS(flags) .private_data = (void *)(flags) |
212 | |
213 | AHCI_HFLAG_NO_NCQ = BIT(0), |
214 | AHCI_HFLAG_IGN_IRQ_IF_ERR = BIT(1), /* ignore IRQ_IF_ERR */ |
215 | AHCI_HFLAG_IGN_SERR_INTERNAL = BIT(2), /* ignore SERR_INTERNAL */ |
216 | AHCI_HFLAG_32BIT_ONLY = BIT(3), /* force 32bit */ |
217 | AHCI_HFLAG_MV_PATA = BIT(4), /* PATA port */ |
218 | AHCI_HFLAG_NO_MSI = BIT(5), /* no PCI MSI */ |
219 | AHCI_HFLAG_NO_PMP = BIT(6), /* no PMP */ |
220 | AHCI_HFLAG_SECT255 = BIT(8), /* max 255 sectors */ |
221 | AHCI_HFLAG_YES_NCQ = BIT(9), /* force NCQ cap on */ |
222 | AHCI_HFLAG_NO_SUSPEND = BIT(10), /* don't suspend */ |
223 | AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = BIT(11), /* treat SRST timeout as |
224 | link offline */ |
225 | AHCI_HFLAG_NO_SNTF = BIT(12), /* no sntf */ |
226 | AHCI_HFLAG_NO_FPDMA_AA = BIT(13), /* no FPDMA AA */ |
227 | AHCI_HFLAG_YES_FBS = BIT(14), /* force FBS cap on */ |
228 | AHCI_HFLAG_DELAY_ENGINE = BIT(15), /* do not start engine on |
229 | port start (wait until |
230 | error-handling stage) */ |
231 | AHCI_HFLAG_NO_DEVSLP = BIT(17), /* no device sleep */ |
232 | AHCI_HFLAG_NO_FBS = BIT(18), /* no FBS */ |
233 | |
234 | #ifdef CONFIG_PCI_MSI |
235 | AHCI_HFLAG_MULTI_MSI = BIT(20), /* per-port MSI(-X) */ |
236 | #else |
237 | /* compile out MSI infrastructure */ |
238 | AHCI_HFLAG_MULTI_MSI = 0, |
239 | #endif |
240 | AHCI_HFLAG_WAKE_BEFORE_STOP = BIT(22), /* wake before DMA stop */ |
241 | AHCI_HFLAG_YES_ALPM = BIT(23), /* force ALPM cap on */ |
242 | AHCI_HFLAG_NO_WRITE_TO_RO = BIT(24), /* don't write to read |
243 | only registers */ |
244 | AHCI_HFLAG_USE_LPM_POLICY = BIT(25), /* chipset that should use |
245 | SATA_MOBILE_LPM_POLICY |
246 | as default lpm_policy */ |
247 | AHCI_HFLAG_SUSPEND_PHYS = BIT(26), /* handle PHYs during |
248 | suspend/resume */ |
249 | AHCI_HFLAG_NO_SXS = BIT(28), /* SXS not supported */ |
250 | |
251 | /* ap->flags bits */ |
252 | |
253 | AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA | |
254 | ATA_FLAG_ACPI_SATA | ATA_FLAG_AN, |
255 | |
256 | ICH_MAP = 0x90, /* ICH MAP register */ |
257 | PCS_6 = 0x92, /* 6 port PCS */ |
258 | PCS_7 = 0x94, /* 7+ port PCS (Denverton) */ |
259 | |
260 | /* em constants */ |
261 | EM_MAX_SLOTS = SATA_PMP_MAX_PORTS, |
262 | EM_MAX_RETRY = 5, |
263 | |
264 | /* em_ctl bits */ |
265 | EM_CTL_RST = BIT(9), /* Reset */ |
266 | EM_CTL_TM = BIT(8), /* Transmit Message */ |
267 | EM_CTL_MR = BIT(0), /* Message Received */ |
268 | EM_CTL_ALHD = BIT(26), /* Activity LED */ |
269 | EM_CTL_XMT = BIT(25), /* Transmit Only */ |
270 | EM_CTL_SMB = BIT(24), /* Single Message Buffer */ |
271 | EM_CTL_SGPIO = BIT(19), /* SGPIO messages supported */ |
272 | EM_CTL_SES = BIT(18), /* SES-2 messages supported */ |
273 | EM_CTL_SAFTE = BIT(17), /* SAF-TE messages supported */ |
274 | EM_CTL_LED = BIT(16), /* LED messages supported */ |
275 | |
276 | /* em message type */ |
277 | EM_MSG_TYPE_LED = BIT(0), /* LED */ |
278 | EM_MSG_TYPE_SAFTE = BIT(1), /* SAF-TE */ |
279 | EM_MSG_TYPE_SES2 = BIT(2), /* SES-2 */ |
280 | EM_MSG_TYPE_SGPIO = BIT(3), /* SGPIO */ |
281 | }; |
282 | |
283 | struct ahci_cmd_hdr { |
284 | __le32 opts; |
285 | __le32 status; |
286 | __le32 tbl_addr; |
287 | __le32 tbl_addr_hi; |
288 | __le32 reserved[4]; |
289 | }; |
290 | |
291 | struct ahci_sg { |
292 | __le32 addr; |
293 | __le32 addr_hi; |
294 | __le32 reserved; |
295 | __le32 flags_size; |
296 | }; |
297 | |
298 | struct ahci_em_priv { |
299 | enum sw_activity blink_policy; |
300 | struct timer_list timer; |
301 | unsigned long saved_activity; |
302 | unsigned long activity; |
303 | unsigned long led_state; |
304 | struct ata_link *link; |
305 | }; |
306 | |
307 | struct ahci_port_priv { |
308 | struct ata_link *active_link; |
309 | struct ahci_cmd_hdr *cmd_slot; |
310 | dma_addr_t cmd_slot_dma; |
311 | void *cmd_tbl; |
312 | dma_addr_t cmd_tbl_dma; |
313 | void *rx_fis; |
314 | dma_addr_t rx_fis_dma; |
315 | /* for NCQ spurious interrupt analysis */ |
316 | unsigned int ncq_saw_d2h:1; |
317 | unsigned int ncq_saw_dmas:1; |
318 | unsigned int ncq_saw_sdb:1; |
319 | spinlock_t lock; /* protects parent ata_port */ |
320 | u32 intr_mask; /* interrupts to enable */ |
321 | bool fbs_supported; /* set iff FBS is supported */ |
322 | bool fbs_enabled; /* set iff FBS is enabled */ |
323 | int fbs_last_dev; /* save FBS.DEV of last FIS */ |
324 | /* enclosure management info per PM slot */ |
325 | struct ahci_em_priv em_priv[EM_MAX_SLOTS]; |
326 | char *irq_desc; /* desc in /proc/interrupts */ |
327 | }; |
328 | |
329 | struct ahci_host_priv { |
330 | /* Input fields */ |
331 | unsigned int flags; /* AHCI_HFLAG_* */ |
332 | u32 mask_port_map; /* mask out particular bits */ |
333 | |
334 | void __iomem * mmio; /* bus-independent mem map */ |
335 | u32 cap; /* cap to use */ |
336 | u32 cap2; /* cap2 to use */ |
337 | u32 version; /* cached version */ |
338 | u32 port_map; /* port map to use */ |
339 | u32 saved_cap; /* saved initial cap */ |
340 | u32 saved_cap2; /* saved initial cap2 */ |
341 | u32 saved_port_map; /* saved initial port_map */ |
342 | u32 saved_port_cap[AHCI_MAX_PORTS]; /* saved port_cap */ |
343 | u32 em_loc; /* enclosure management location */ |
344 | u32 em_buf_sz; /* EM buffer size in byte */ |
345 | u32 em_msg_type; /* EM message type */ |
346 | u32 remapped_nvme; /* NVMe remapped device count */ |
347 | bool got_runtime_pm; /* Did we do pm_runtime_get? */ |
348 | unsigned int n_clks; |
349 | struct clk_bulk_data *clks; /* Optional */ |
350 | unsigned int f_rsts; |
351 | struct reset_control *rsts; /* Optional */ |
352 | struct regulator **target_pwrs; /* Optional */ |
353 | struct regulator *ahci_regulator;/* Optional */ |
354 | struct regulator *phy_regulator;/* Optional */ |
355 | /* |
356 | * If platform uses PHYs. There is a 1:1 relation between the port number and |
357 | * the PHY position in this array. |
358 | */ |
359 | struct phy **phys; |
360 | unsigned nports; /* Number of ports */ |
361 | void *plat_data; /* Other platform data */ |
362 | unsigned int irq; /* interrupt line */ |
363 | /* |
364 | * Optional ahci_start_engine override, if not set this gets set to the |
365 | * default ahci_start_engine during ahci_save_initial_config, this can |
366 | * be overridden anytime before the host is activated. |
367 | */ |
368 | void (*start_engine)(struct ata_port *ap); |
369 | /* |
370 | * Optional ahci_stop_engine override, if not set this gets set to the |
371 | * default ahci_stop_engine during ahci_save_initial_config, this can |
372 | * be overridden anytime before the host is activated. |
373 | */ |
374 | int (*stop_engine)(struct ata_port *ap); |
375 | |
376 | irqreturn_t (*irq_handler)(int irq, void *dev_instance); |
377 | |
378 | /* only required for per-port MSI(-X) support */ |
379 | int (*get_irq_vector)(struct ata_host *host, |
380 | int port); |
381 | }; |
382 | |
383 | extern int ahci_ignore_sss; |
384 | |
385 | extern const struct attribute_group *ahci_shost_groups[]; |
386 | extern const struct attribute_group *ahci_sdev_groups[]; |
387 | |
388 | /* |
389 | * This must be instantiated by the edge drivers. Read the comments |
390 | * for ATA_BASE_SHT |
391 | */ |
392 | #define AHCI_SHT(drv_name) \ |
393 | __ATA_BASE_SHT(drv_name), \ |
394 | .can_queue = AHCI_MAX_CMDS, \ |
395 | .sg_tablesize = AHCI_MAX_SG, \ |
396 | .dma_boundary = AHCI_DMA_BOUNDARY, \ |
397 | .shost_groups = ahci_shost_groups, \ |
398 | .sdev_groups = ahci_sdev_groups, \ |
399 | .change_queue_depth = ata_scsi_change_queue_depth, \ |
400 | .tag_alloc_policy = BLK_TAG_ALLOC_RR, \ |
401 | .slave_configure = ata_scsi_slave_config |
402 | |
403 | extern struct ata_port_operations ahci_ops; |
404 | extern struct ata_port_operations ahci_platform_ops; |
405 | extern struct ata_port_operations ahci_pmp_retry_srst_ops; |
406 | |
407 | unsigned int ahci_dev_classify(struct ata_port *ap); |
408 | void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
409 | u32 opts); |
410 | void ahci_save_initial_config(struct device *dev, |
411 | struct ahci_host_priv *hpriv); |
412 | void ahci_init_controller(struct ata_host *host); |
413 | int ahci_reset_controller(struct ata_host *host); |
414 | |
415 | int ahci_do_softreset(struct ata_link *link, unsigned int *class, |
416 | int pmp, unsigned long deadline, |
417 | int (*check_ready)(struct ata_link *link)); |
418 | |
419 | int ahci_do_hardreset(struct ata_link *link, unsigned int *class, |
420 | unsigned long deadline, bool *online); |
421 | |
422 | unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); |
423 | int ahci_stop_engine(struct ata_port *ap); |
424 | void ahci_start_fis_rx(struct ata_port *ap); |
425 | void ahci_start_engine(struct ata_port *ap); |
426 | int ahci_check_ready(struct ata_link *link); |
427 | int ahci_kick_engine(struct ata_port *ap); |
428 | int ahci_port_resume(struct ata_port *ap); |
429 | void ahci_set_em_messages(struct ahci_host_priv *hpriv, |
430 | struct ata_port_info *pi); |
431 | int ahci_reset_em(struct ata_host *host); |
432 | void ahci_print_info(struct ata_host *host, const char *scc_s); |
433 | int ahci_host_activate(struct ata_host *host, const struct scsi_host_template *sht); |
434 | void ahci_error_handler(struct ata_port *ap); |
435 | u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked); |
436 | |
437 | static inline void __iomem *__ahci_port_base(struct ahci_host_priv *hpriv, |
438 | unsigned int port_no) |
439 | { |
440 | void __iomem *mmio = hpriv->mmio; |
441 | |
442 | return mmio + 0x100 + (port_no * 0x80); |
443 | } |
444 | |
445 | static inline void __iomem *ahci_port_base(struct ata_port *ap) |
446 | { |
447 | struct ahci_host_priv *hpriv = ap->host->private_data; |
448 | |
449 | return __ahci_port_base(hpriv, port_no: ap->port_no); |
450 | } |
451 | |
452 | static inline int ahci_nr_ports(u32 cap) |
453 | { |
454 | return (cap & 0x1f) + 1; |
455 | } |
456 | |
457 | #endif /* _AHCI_H */ |
458 | |