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1/*
2 * drivers/ata/ahci_tegra.c
3 *
4 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Author:
7 * Mikko Perttunen <mperttunen@nvidia.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#include <linux/ahci_platform.h>
21#include <linux/errno.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/of_device.h>
25#include <linux/platform_device.h>
26#include <linux/regulator/consumer.h>
27#include <linux/reset.h>
28
29#include <soc/tegra/fuse.h>
30#include <soc/tegra/pmc.h>
31
32#include "ahci.h"
33
34#define DRV_NAME "tegra-ahci"
35
36#define SATA_CONFIGURATION_0 0x180
37#define SATA_CONFIGURATION_0_EN_FPCI BIT(0)
38#define SATA_CONFIGURATION_0_CLK_OVERRIDE BIT(31)
39
40#define SCFG_OFFSET 0x1000
41
42#define T_SATA0_CFG_1 0x04
43#define T_SATA0_CFG_1_IO_SPACE BIT(0)
44#define T_SATA0_CFG_1_MEMORY_SPACE BIT(1)
45#define T_SATA0_CFG_1_BUS_MASTER BIT(2)
46#define T_SATA0_CFG_1_SERR BIT(8)
47
48#define T_SATA0_CFG_9 0x24
49#define T_SATA0_CFG_9_BASE_ADDRESS 0x40020000
50
51#define SATA_FPCI_BAR5 0x94
52#define SATA_FPCI_BAR5_START_MASK (0xfffffff << 4)
53#define SATA_FPCI_BAR5_START (0x0040020 << 4)
54#define SATA_FPCI_BAR5_ACCESS_TYPE (0x1)
55
56#define SATA_INTR_MASK 0x188
57#define SATA_INTR_MASK_IP_INT_MASK BIT(16)
58
59#define T_SATA0_CFG_35 0x94
60#define T_SATA0_CFG_35_IDP_INDEX_MASK (0x7ff << 2)
61#define T_SATA0_CFG_35_IDP_INDEX (0x2a << 2)
62
63#define T_SATA0_AHCI_IDP1 0x98
64#define T_SATA0_AHCI_IDP1_DATA (0x400040)
65
66#define T_SATA0_CFG_PHY_1 0x12c
67#define T_SATA0_CFG_PHY_1_PADS_IDDQ_EN BIT(23)
68#define T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN BIT(22)
69
70#define T_SATA0_NVOOB 0x114
71#define T_SATA0_NVOOB_COMMA_CNT_MASK (0xff << 16)
72#define T_SATA0_NVOOB_COMMA_CNT (0x07 << 16)
73#define T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK (0x3 << 24)
74#define T_SATA0_NVOOB_SQUELCH_FILTER_MODE (0x1 << 24)
75#define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK (0x3 << 26)
76#define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH (0x3 << 26)
77
78#define T_SATA_CFG_PHY_0 0x120
79#define T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD BIT(11)
80#define T_SATA_CFG_PHY_0_MASK_SQUELCH BIT(24)
81
82#define T_SATA0_CFG2NVOOB_2 0x134
83#define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK (0x1ff << 18)
84#define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW (0xc << 18)
85
86#define T_SATA0_AHCI_HBA_CAP_BKDR 0x300
87#define T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP BIT(13)
88#define T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP BIT(14)
89#define T_SATA0_AHCI_HBA_CAP_BKDR_SALP BIT(26)
90#define T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM BIT(17)
91#define T_SATA0_AHCI_HBA_CAP_BKDR_SNCQ BIT(30)
92
93#define T_SATA0_BKDOOR_CC 0x4a4
94#define T_SATA0_BKDOOR_CC_CLASS_CODE_MASK (0xffff << 16)
95#define T_SATA0_BKDOOR_CC_CLASS_CODE (0x0106 << 16)
96#define T_SATA0_BKDOOR_CC_PROG_IF_MASK (0xff << 8)
97#define T_SATA0_BKDOOR_CC_PROG_IF (0x01 << 8)
98
99#define T_SATA0_CFG_SATA 0x54c
100#define T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN BIT(12)
101
102#define T_SATA0_CFG_MISC 0x550
103
104#define T_SATA0_INDEX 0x680
105
106#define T_SATA0_CHX_PHY_CTRL1_GEN1 0x690
107#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK 0xff
108#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT 0
109#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK (0xff << 8)
110#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT 8
111
112#define T_SATA0_CHX_PHY_CTRL1_GEN2 0x694
113#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK 0xff
114#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT 0
115#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK (0xff << 12)
116#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT 12
117
118#define T_SATA0_CHX_PHY_CTRL2 0x69c
119#define T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1 0x23
120
121#define T_SATA0_CHX_PHY_CTRL11 0x6d0
122#define T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ (0x2800 << 16)
123
124#define T_SATA0_CHX_PHY_CTRL17_0 0x6e8
125#define T_SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1 0x55010000
126#define T_SATA0_CHX_PHY_CTRL18_0 0x6ec
127#define T_SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2 0x55010000
128#define T_SATA0_CHX_PHY_CTRL20_0 0x6f4
129#define T_SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1 0x1
130#define T_SATA0_CHX_PHY_CTRL21_0 0x6f8
131#define T_SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2 0x1
132
133/* AUX Registers */
134#define SATA_AUX_MISC_CNTL_1_0 0x8
135#define SATA_AUX_MISC_CNTL_1_0_DEVSLP_OVERRIDE BIT(17)
136#define SATA_AUX_MISC_CNTL_1_0_SDS_SUPPORT BIT(13)
137#define SATA_AUX_MISC_CNTL_1_0_DESO_SUPPORT BIT(15)
138
139#define SATA_AUX_RX_STAT_INT_0 0xc
140#define SATA_AUX_RX_STAT_INT_0_SATA_DEVSLP BIT(7)
141
142#define SATA_AUX_SPARE_CFG0_0 0x18
143#define SATA_AUX_SPARE_CFG0_0_MDAT_TIMER_AFTER_PG_VALID BIT(14)
144
145#define FUSE_SATA_CALIB 0x124
146#define FUSE_SATA_CALIB_MASK 0x3
147
148struct sata_pad_calibration {
149 u8 gen1_tx_amp;
150 u8 gen1_tx_peak;
151 u8 gen2_tx_amp;
152 u8 gen2_tx_peak;
153};
154
155static const struct sata_pad_calibration tegra124_pad_calibration[] = {
156 {0x18, 0x04, 0x18, 0x0a},
157 {0x0e, 0x04, 0x14, 0x0a},
158 {0x0e, 0x07, 0x1a, 0x0e},
159 {0x14, 0x0e, 0x1a, 0x0e},
160};
161
162struct tegra_ahci_ops {
163 int (*init)(struct ahci_host_priv *hpriv);
164};
165
166struct tegra_ahci_soc {
167 const char *const *supply_names;
168 u32 num_supplies;
169 bool supports_devslp;
170 const struct tegra_ahci_ops *ops;
171};
172
173struct tegra_ahci_priv {
174 struct platform_device *pdev;
175 void __iomem *sata_regs;
176 void __iomem *sata_aux_regs;
177 struct reset_control *sata_rst;
178 struct reset_control *sata_oob_rst;
179 struct reset_control *sata_cold_rst;
180 /* Needs special handling, cannot use ahci_platform */
181 struct clk *sata_clk;
182 struct regulator_bulk_data *supplies;
183 const struct tegra_ahci_soc *soc;
184};
185
186static void tegra_ahci_handle_quirks(struct ahci_host_priv *hpriv)
187{
188 struct tegra_ahci_priv *tegra = hpriv->plat_data;
189 u32 val;
190
191 if (tegra->sata_aux_regs && !tegra->soc->supports_devslp) {
192 val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
193 val &= ~SATA_AUX_MISC_CNTL_1_0_SDS_SUPPORT;
194 writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
195 }
196}
197
198static int tegra124_ahci_init(struct ahci_host_priv *hpriv)
199{
200 struct tegra_ahci_priv *tegra = hpriv->plat_data;
201 struct sata_pad_calibration calib;
202 int ret;
203 u32 val;
204
205 /* Pad calibration */
206 ret = tegra_fuse_readl(FUSE_SATA_CALIB, &val);
207 if (ret)
208 return ret;
209
210 calib = tegra124_pad_calibration[val & FUSE_SATA_CALIB_MASK];
211
212 writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
213
214 val = readl(tegra->sata_regs +
215 SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1);
216 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK;
217 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
218 val |= calib.gen1_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
219 val |= calib.gen1_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
220 writel(val, tegra->sata_regs + SCFG_OFFSET +
221 T_SATA0_CHX_PHY_CTRL1_GEN1);
222
223 val = readl(tegra->sata_regs +
224 SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2);
225 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK;
226 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
227 val |= calib.gen2_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
228 val |= calib.gen2_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
229 writel(val, tegra->sata_regs + SCFG_OFFSET +
230 T_SATA0_CHX_PHY_CTRL1_GEN2);
231
232 writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ,
233 tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11);
234 writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1,
235 tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2);
236
237 writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
238
239 return 0;
240}
241
242static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
243{
244 struct tegra_ahci_priv *tegra = hpriv->plat_data;
245 int ret;
246
247 ret = regulator_bulk_enable(tegra->soc->num_supplies,
248 tegra->supplies);
249 if (ret)
250 return ret;
251
252 ret = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SATA,
253 tegra->sata_clk,
254 tegra->sata_rst);
255 if (ret)
256 goto disable_regulators;
257
258 reset_control_assert(tegra->sata_oob_rst);
259 reset_control_assert(tegra->sata_cold_rst);
260
261 ret = ahci_platform_enable_resources(hpriv);
262 if (ret)
263 goto disable_power;
264
265 reset_control_deassert(tegra->sata_cold_rst);
266 reset_control_deassert(tegra->sata_oob_rst);
267
268 return 0;
269
270disable_power:
271 clk_disable_unprepare(tegra->sata_clk);
272
273 tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
274
275disable_regulators:
276 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
277
278 return ret;
279}
280
281static void tegra_ahci_power_off(struct ahci_host_priv *hpriv)
282{
283 struct tegra_ahci_priv *tegra = hpriv->plat_data;
284
285 ahci_platform_disable_resources(hpriv);
286
287 reset_control_assert(tegra->sata_rst);
288 reset_control_assert(tegra->sata_oob_rst);
289 reset_control_assert(tegra->sata_cold_rst);
290
291 clk_disable_unprepare(tegra->sata_clk);
292 tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
293
294 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
295}
296
297static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv)
298{
299 struct tegra_ahci_priv *tegra = hpriv->plat_data;
300 int ret;
301 u32 val;
302
303 ret = tegra_ahci_power_on(hpriv);
304 if (ret) {
305 dev_err(&tegra->pdev->dev,
306 "failed to power on AHCI controller: %d\n", ret);
307 return ret;
308 }
309
310 /*
311 * Program the following SATA IPFS registers to allow SW accesses to
312 * SATA's MMIO register range.
313 */
314 val = readl(tegra->sata_regs + SATA_FPCI_BAR5);
315 val &= ~(SATA_FPCI_BAR5_START_MASK | SATA_FPCI_BAR5_ACCESS_TYPE);
316 val |= SATA_FPCI_BAR5_START | SATA_FPCI_BAR5_ACCESS_TYPE;
317 writel(val, tegra->sata_regs + SATA_FPCI_BAR5);
318
319 /* Program the following SATA IPFS register to enable the SATA */
320 val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
321 val |= SATA_CONFIGURATION_0_EN_FPCI;
322 writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
323
324 /* Electrical settings for better link stability */
325 val = T_SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1;
326 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL17_0);
327 val = T_SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2;
328 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL18_0);
329 val = T_SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1;
330 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL20_0);
331 val = T_SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2;
332 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL21_0);
333
334 /* For SQUELCH Filter & Gen3 drive getting detected as Gen1 drive */
335
336 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);
337 val |= T_SATA_CFG_PHY_0_MASK_SQUELCH;
338 val &= ~T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD;
339 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);
340
341 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);
342 val &= ~(T_SATA0_NVOOB_COMMA_CNT_MASK |
343 T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK |
344 T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK);
345 val |= (T_SATA0_NVOOB_COMMA_CNT |
346 T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH |
347 T_SATA0_NVOOB_SQUELCH_FILTER_MODE);
348 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);
349
350 /*
351 * Change CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW from 83.3 ns to 58.8ns
352 */
353 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);
354 val &= ~T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK;
355 val |= T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW;
356 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);
357
358 if (tegra->soc->ops && tegra->soc->ops->init)
359 tegra->soc->ops->init(hpriv);
360
361 /*
362 * Program the following SATA configuration registers to
363 * initialize SATA
364 */
365 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
366 val |= (T_SATA0_CFG_1_IO_SPACE | T_SATA0_CFG_1_MEMORY_SPACE |
367 T_SATA0_CFG_1_BUS_MASTER | T_SATA0_CFG_1_SERR);
368 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
369 val = T_SATA0_CFG_9_BASE_ADDRESS;
370 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);
371
372 /* Program Class Code and Programming interface for SATA */
373 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
374 val |= T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
375 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
376
377 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
378 val &=
379 ~(T_SATA0_BKDOOR_CC_CLASS_CODE_MASK |
380 T_SATA0_BKDOOR_CC_PROG_IF_MASK);
381 val |= T_SATA0_BKDOOR_CC_CLASS_CODE | T_SATA0_BKDOOR_CC_PROG_IF;
382 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
383
384 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
385 val &= ~T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
386 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
387
388 /* Enabling LPM capabilities through Backdoor Programming */
389 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR);
390 val |= (T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP |
391 T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP |
392 T_SATA0_AHCI_HBA_CAP_BKDR_SALP |
393 T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM);
394 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR);
395
396 /* SATA Second Level Clock Gating configuration
397 * Enabling Gating of Tx/Rx clocks and driving Pad IDDQ and Lane
398 * IDDQ Signals
399 */
400 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35);
401 val &= ~T_SATA0_CFG_35_IDP_INDEX_MASK;
402 val |= T_SATA0_CFG_35_IDP_INDEX;
403 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35);
404
405 val = T_SATA0_AHCI_IDP1_DATA;
406 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_IDP1);
407
408 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1);
409 val |= (T_SATA0_CFG_PHY_1_PADS_IDDQ_EN |
410 T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN);
411 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1);
412
413 /* Enabling IPFS Clock Gating */
414 val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
415 val &= ~SATA_CONFIGURATION_0_CLK_OVERRIDE;
416 writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
417
418 tegra_ahci_handle_quirks(hpriv);
419
420 /* Unmask SATA interrupts */
421
422 val = readl(tegra->sata_regs + SATA_INTR_MASK);
423 val |= SATA_INTR_MASK_IP_INT_MASK;
424 writel(val, tegra->sata_regs + SATA_INTR_MASK);
425
426 return 0;
427}
428
429static void tegra_ahci_controller_deinit(struct ahci_host_priv *hpriv)
430{
431 tegra_ahci_power_off(hpriv);
432}
433
434static void tegra_ahci_host_stop(struct ata_host *host)
435{
436 struct ahci_host_priv *hpriv = host->private_data;
437
438 tegra_ahci_controller_deinit(hpriv);
439}
440
441static struct ata_port_operations ahci_tegra_port_ops = {
442 .inherits = &ahci_ops,
443 .host_stop = tegra_ahci_host_stop,
444};
445
446static const struct ata_port_info ahci_tegra_port_info = {
447 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
448 .pio_mask = ATA_PIO4,
449 .udma_mask = ATA_UDMA6,
450 .port_ops = &ahci_tegra_port_ops,
451};
452
453static const char *const tegra124_supply_names[] = {
454 "avdd", "hvdd", "vddio", "target-5v", "target-12v"
455};
456
457static const struct tegra_ahci_ops tegra124_ahci_ops = {
458 .init = tegra124_ahci_init,
459};
460
461static const struct tegra_ahci_soc tegra124_ahci_soc = {
462 .supply_names = tegra124_supply_names,
463 .num_supplies = ARRAY_SIZE(tegra124_supply_names),
464 .supports_devslp = false,
465 .ops = &tegra124_ahci_ops,
466};
467
468static const struct tegra_ahci_soc tegra210_ahci_soc = {
469 .supports_devslp = false,
470};
471
472static const struct of_device_id tegra_ahci_of_match[] = {
473 {
474 .compatible = "nvidia,tegra124-ahci",
475 .data = &tegra124_ahci_soc
476 },
477 {
478 .compatible = "nvidia,tegra210-ahci",
479 .data = &tegra210_ahci_soc
480 },
481 {}
482};
483MODULE_DEVICE_TABLE(of, tegra_ahci_of_match);
484
485static struct scsi_host_template ahci_platform_sht = {
486 AHCI_SHT(DRV_NAME),
487};
488
489static int tegra_ahci_probe(struct platform_device *pdev)
490{
491 struct ahci_host_priv *hpriv;
492 struct tegra_ahci_priv *tegra;
493 struct resource *res;
494 int ret;
495 unsigned int i;
496
497 hpriv = ahci_platform_get_resources(pdev, 0);
498 if (IS_ERR(hpriv))
499 return PTR_ERR(hpriv);
500
501 tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
502 if (!tegra)
503 return -ENOMEM;
504
505 hpriv->plat_data = tegra;
506
507 tegra->pdev = pdev;
508 tegra->soc = of_device_get_match_data(&pdev->dev);
509
510 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
511 tegra->sata_regs = devm_ioremap_resource(&pdev->dev, res);
512 if (IS_ERR(tegra->sata_regs))
513 return PTR_ERR(tegra->sata_regs);
514
515 /*
516 * AUX registers is optional.
517 */
518 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
519 if (res) {
520 tegra->sata_aux_regs = devm_ioremap_resource(&pdev->dev, res);
521 if (IS_ERR(tegra->sata_aux_regs))
522 return PTR_ERR(tegra->sata_aux_regs);
523 }
524
525 tegra->sata_rst = devm_reset_control_get(&pdev->dev, "sata");
526 if (IS_ERR(tegra->sata_rst)) {
527 dev_err(&pdev->dev, "Failed to get sata reset\n");
528 return PTR_ERR(tegra->sata_rst);
529 }
530
531 tegra->sata_oob_rst = devm_reset_control_get(&pdev->dev, "sata-oob");
532 if (IS_ERR(tegra->sata_oob_rst)) {
533 dev_err(&pdev->dev, "Failed to get sata-oob reset\n");
534 return PTR_ERR(tegra->sata_oob_rst);
535 }
536
537 tegra->sata_cold_rst = devm_reset_control_get(&pdev->dev, "sata-cold");
538 if (IS_ERR(tegra->sata_cold_rst)) {
539 dev_err(&pdev->dev, "Failed to get sata-cold reset\n");
540 return PTR_ERR(tegra->sata_cold_rst);
541 }
542
543 tegra->sata_clk = devm_clk_get(&pdev->dev, "sata");
544 if (IS_ERR(tegra->sata_clk)) {
545 dev_err(&pdev->dev, "Failed to get sata clock\n");
546 return PTR_ERR(tegra->sata_clk);
547 }
548
549 tegra->supplies = devm_kcalloc(&pdev->dev,
550 tegra->soc->num_supplies,
551 sizeof(*tegra->supplies), GFP_KERNEL);
552 if (!tegra->supplies)
553 return -ENOMEM;
554
555 for (i = 0; i < tegra->soc->num_supplies; i++)
556 tegra->supplies[i].supply = tegra->soc->supply_names[i];
557
558 ret = devm_regulator_bulk_get(&pdev->dev,
559 tegra->soc->num_supplies,
560 tegra->supplies);
561 if (ret) {
562 dev_err(&pdev->dev, "Failed to get regulators\n");
563 return ret;
564 }
565
566 ret = tegra_ahci_controller_init(hpriv);
567 if (ret)
568 return ret;
569
570 ret = ahci_platform_init_host(pdev, hpriv, &ahci_tegra_port_info,
571 &ahci_platform_sht);
572 if (ret)
573 goto deinit_controller;
574
575 return 0;
576
577deinit_controller:
578 tegra_ahci_controller_deinit(hpriv);
579
580 return ret;
581};
582
583static struct platform_driver tegra_ahci_driver = {
584 .probe = tegra_ahci_probe,
585 .remove = ata_platform_remove_one,
586 .driver = {
587 .name = DRV_NAME,
588 .of_match_table = tegra_ahci_of_match,
589 },
590 /* LP0 suspend support not implemented */
591};
592module_platform_driver(tegra_ahci_driver);
593
594MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
595MODULE_DESCRIPTION("Tegra AHCI SATA driver");
596MODULE_LICENSE("GPL v2");
597

Warning: That file was not part of the compilation database. It may have many parsing errors.