1/*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/driver-api/libata.rst
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/gfp.h>
37#include <linux/module.h>
38#include <linux/nospec.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/dma-mapping.h>
43#include <linux/device.h>
44#include <scsi/scsi_host.h>
45#include <scsi/scsi_cmnd.h>
46#include <linux/libata.h>
47#include <linux/pci.h>
48#include "ahci.h"
49#include "libata.h"
50
51static int ahci_skip_host_reset;
52int ahci_ignore_sss;
53EXPORT_SYMBOL_GPL(ahci_ignore_sss);
54
55module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
56MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
57
58module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
59MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
60
61static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
62 unsigned hints);
63static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
64static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
65 size_t size);
66static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
67 ssize_t size);
68
69
70
71static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
72static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
73static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
74static int ahci_port_start(struct ata_port *ap);
75static void ahci_port_stop(struct ata_port *ap);
76static void ahci_qc_prep(struct ata_queued_cmd *qc);
77static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
78static void ahci_freeze(struct ata_port *ap);
79static void ahci_thaw(struct ata_port *ap);
80static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
81static void ahci_enable_fbs(struct ata_port *ap);
82static void ahci_disable_fbs(struct ata_port *ap);
83static void ahci_pmp_attach(struct ata_port *ap);
84static void ahci_pmp_detach(struct ata_port *ap);
85static int ahci_softreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
89static int ahci_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
91static void ahci_postreset(struct ata_link *link, unsigned int *class);
92static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
93static void ahci_dev_config(struct ata_device *dev);
94#ifdef CONFIG_PM
95static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
96#endif
97static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
98static ssize_t ahci_activity_store(struct ata_device *dev,
99 enum sw_activity val);
100static void ahci_init_sw_activity(struct ata_link *link);
101
102static ssize_t ahci_show_host_caps(struct device *dev,
103 struct device_attribute *attr, char *buf);
104static ssize_t ahci_show_host_cap2(struct device *dev,
105 struct device_attribute *attr, char *buf);
106static ssize_t ahci_show_host_version(struct device *dev,
107 struct device_attribute *attr, char *buf);
108static ssize_t ahci_show_port_cmd(struct device *dev,
109 struct device_attribute *attr, char *buf);
110static ssize_t ahci_read_em_buffer(struct device *dev,
111 struct device_attribute *attr, char *buf);
112static ssize_t ahci_store_em_buffer(struct device *dev,
113 struct device_attribute *attr,
114 const char *buf, size_t size);
115static ssize_t ahci_show_em_supported(struct device *dev,
116 struct device_attribute *attr, char *buf);
117static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance);
118
119static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
120static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
121static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
122static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
123static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
124 ahci_read_em_buffer, ahci_store_em_buffer);
125static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
126
127struct device_attribute *ahci_shost_attrs[] = {
128 &dev_attr_link_power_management_policy,
129 &dev_attr_em_message_type,
130 &dev_attr_em_message,
131 &dev_attr_ahci_host_caps,
132 &dev_attr_ahci_host_cap2,
133 &dev_attr_ahci_host_version,
134 &dev_attr_ahci_port_cmd,
135 &dev_attr_em_buffer,
136 &dev_attr_em_message_supported,
137 NULL
138};
139EXPORT_SYMBOL_GPL(ahci_shost_attrs);
140
141struct device_attribute *ahci_sdev_attrs[] = {
142 &dev_attr_sw_activity,
143 &dev_attr_unload_heads,
144 &dev_attr_ncq_prio_enable,
145 NULL
146};
147EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
148
149struct ata_port_operations ahci_ops = {
150 .inherits = &sata_pmp_port_ops,
151
152 .qc_defer = ahci_pmp_qc_defer,
153 .qc_prep = ahci_qc_prep,
154 .qc_issue = ahci_qc_issue,
155 .qc_fill_rtf = ahci_qc_fill_rtf,
156
157 .freeze = ahci_freeze,
158 .thaw = ahci_thaw,
159 .softreset = ahci_softreset,
160 .hardreset = ahci_hardreset,
161 .postreset = ahci_postreset,
162 .pmp_softreset = ahci_softreset,
163 .error_handler = ahci_error_handler,
164 .post_internal_cmd = ahci_post_internal_cmd,
165 .dev_config = ahci_dev_config,
166
167 .scr_read = ahci_scr_read,
168 .scr_write = ahci_scr_write,
169 .pmp_attach = ahci_pmp_attach,
170 .pmp_detach = ahci_pmp_detach,
171
172 .set_lpm = ahci_set_lpm,
173 .em_show = ahci_led_show,
174 .em_store = ahci_led_store,
175 .sw_activity_show = ahci_activity_show,
176 .sw_activity_store = ahci_activity_store,
177 .transmit_led_message = ahci_transmit_led_message,
178#ifdef CONFIG_PM
179 .port_suspend = ahci_port_suspend,
180 .port_resume = ahci_port_resume,
181#endif
182 .port_start = ahci_port_start,
183 .port_stop = ahci_port_stop,
184};
185EXPORT_SYMBOL_GPL(ahci_ops);
186
187struct ata_port_operations ahci_pmp_retry_srst_ops = {
188 .inherits = &ahci_ops,
189 .softreset = ahci_pmp_retry_softreset,
190};
191EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
192
193static bool ahci_em_messages __read_mostly = true;
194EXPORT_SYMBOL_GPL(ahci_em_messages);
195module_param(ahci_em_messages, bool, 0444);
196/* add other LED protocol types when they become supported */
197MODULE_PARM_DESC(ahci_em_messages,
198 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
199
200/* device sleep idle timeout in ms */
201static int devslp_idle_timeout __read_mostly = 1000;
202module_param(devslp_idle_timeout, int, 0644);
203MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
204
205static void ahci_enable_ahci(void __iomem *mmio)
206{
207 int i;
208 u32 tmp;
209
210 /* turn on AHCI_EN */
211 tmp = readl(mmio + HOST_CTL);
212 if (tmp & HOST_AHCI_EN)
213 return;
214
215 /* Some controllers need AHCI_EN to be written multiple times.
216 * Try a few times before giving up.
217 */
218 for (i = 0; i < 5; i++) {
219 tmp |= HOST_AHCI_EN;
220 writel(tmp, mmio + HOST_CTL);
221 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
222 if (tmp & HOST_AHCI_EN)
223 return;
224 msleep(10);
225 }
226
227 WARN_ON(1);
228}
229
230/**
231 * ahci_rpm_get_port - Make sure the port is powered on
232 * @ap: Port to power on
233 *
234 * Whenever there is need to access the AHCI host registers outside of
235 * normal execution paths, call this function to make sure the host is
236 * actually powered on.
237 */
238static int ahci_rpm_get_port(struct ata_port *ap)
239{
240 return pm_runtime_get_sync(ap->dev);
241}
242
243/**
244 * ahci_rpm_put_port - Undoes ahci_rpm_get_port()
245 * @ap: Port to power down
246 *
247 * Undoes ahci_rpm_get_port() and possibly powers down the AHCI host
248 * if it has no more active users.
249 */
250static void ahci_rpm_put_port(struct ata_port *ap)
251{
252 pm_runtime_put(ap->dev);
253}
254
255static ssize_t ahci_show_host_caps(struct device *dev,
256 struct device_attribute *attr, char *buf)
257{
258 struct Scsi_Host *shost = class_to_shost(dev);
259 struct ata_port *ap = ata_shost_to_port(shost);
260 struct ahci_host_priv *hpriv = ap->host->private_data;
261
262 return sprintf(buf, "%x\n", hpriv->cap);
263}
264
265static ssize_t ahci_show_host_cap2(struct device *dev,
266 struct device_attribute *attr, char *buf)
267{
268 struct Scsi_Host *shost = class_to_shost(dev);
269 struct ata_port *ap = ata_shost_to_port(shost);
270 struct ahci_host_priv *hpriv = ap->host->private_data;
271
272 return sprintf(buf, "%x\n", hpriv->cap2);
273}
274
275static ssize_t ahci_show_host_version(struct device *dev,
276 struct device_attribute *attr, char *buf)
277{
278 struct Scsi_Host *shost = class_to_shost(dev);
279 struct ata_port *ap = ata_shost_to_port(shost);
280 struct ahci_host_priv *hpriv = ap->host->private_data;
281
282 return sprintf(buf, "%x\n", hpriv->version);
283}
284
285static ssize_t ahci_show_port_cmd(struct device *dev,
286 struct device_attribute *attr, char *buf)
287{
288 struct Scsi_Host *shost = class_to_shost(dev);
289 struct ata_port *ap = ata_shost_to_port(shost);
290 void __iomem *port_mmio = ahci_port_base(ap);
291 ssize_t ret;
292
293 ahci_rpm_get_port(ap);
294 ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
295 ahci_rpm_put_port(ap);
296
297 return ret;
298}
299
300static ssize_t ahci_read_em_buffer(struct device *dev,
301 struct device_attribute *attr, char *buf)
302{
303 struct Scsi_Host *shost = class_to_shost(dev);
304 struct ata_port *ap = ata_shost_to_port(shost);
305 struct ahci_host_priv *hpriv = ap->host->private_data;
306 void __iomem *mmio = hpriv->mmio;
307 void __iomem *em_mmio = mmio + hpriv->em_loc;
308 u32 em_ctl, msg;
309 unsigned long flags;
310 size_t count;
311 int i;
312
313 ahci_rpm_get_port(ap);
314 spin_lock_irqsave(ap->lock, flags);
315
316 em_ctl = readl(mmio + HOST_EM_CTL);
317 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
318 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
319 spin_unlock_irqrestore(ap->lock, flags);
320 ahci_rpm_put_port(ap);
321 return -EINVAL;
322 }
323
324 if (!(em_ctl & EM_CTL_MR)) {
325 spin_unlock_irqrestore(ap->lock, flags);
326 ahci_rpm_put_port(ap);
327 return -EAGAIN;
328 }
329
330 if (!(em_ctl & EM_CTL_SMB))
331 em_mmio += hpriv->em_buf_sz;
332
333 count = hpriv->em_buf_sz;
334
335 /* the count should not be larger than PAGE_SIZE */
336 if (count > PAGE_SIZE) {
337 if (printk_ratelimit())
338 ata_port_warn(ap,
339 "EM read buffer size too large: "
340 "buffer size %u, page size %lu\n",
341 hpriv->em_buf_sz, PAGE_SIZE);
342 count = PAGE_SIZE;
343 }
344
345 for (i = 0; i < count; i += 4) {
346 msg = readl(em_mmio + i);
347 buf[i] = msg & 0xff;
348 buf[i + 1] = (msg >> 8) & 0xff;
349 buf[i + 2] = (msg >> 16) & 0xff;
350 buf[i + 3] = (msg >> 24) & 0xff;
351 }
352
353 spin_unlock_irqrestore(ap->lock, flags);
354 ahci_rpm_put_port(ap);
355
356 return i;
357}
358
359static ssize_t ahci_store_em_buffer(struct device *dev,
360 struct device_attribute *attr,
361 const char *buf, size_t size)
362{
363 struct Scsi_Host *shost = class_to_shost(dev);
364 struct ata_port *ap = ata_shost_to_port(shost);
365 struct ahci_host_priv *hpriv = ap->host->private_data;
366 void __iomem *mmio = hpriv->mmio;
367 void __iomem *em_mmio = mmio + hpriv->em_loc;
368 const unsigned char *msg_buf = buf;
369 u32 em_ctl, msg;
370 unsigned long flags;
371 int i;
372
373 /* check size validity */
374 if (!(ap->flags & ATA_FLAG_EM) ||
375 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
376 size % 4 || size > hpriv->em_buf_sz)
377 return -EINVAL;
378
379 ahci_rpm_get_port(ap);
380 spin_lock_irqsave(ap->lock, flags);
381
382 em_ctl = readl(mmio + HOST_EM_CTL);
383 if (em_ctl & EM_CTL_TM) {
384 spin_unlock_irqrestore(ap->lock, flags);
385 ahci_rpm_put_port(ap);
386 return -EBUSY;
387 }
388
389 for (i = 0; i < size; i += 4) {
390 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
391 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
392 writel(msg, em_mmio + i);
393 }
394
395 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
396
397 spin_unlock_irqrestore(ap->lock, flags);
398 ahci_rpm_put_port(ap);
399
400 return size;
401}
402
403static ssize_t ahci_show_em_supported(struct device *dev,
404 struct device_attribute *attr, char *buf)
405{
406 struct Scsi_Host *shost = class_to_shost(dev);
407 struct ata_port *ap = ata_shost_to_port(shost);
408 struct ahci_host_priv *hpriv = ap->host->private_data;
409 void __iomem *mmio = hpriv->mmio;
410 u32 em_ctl;
411
412 ahci_rpm_get_port(ap);
413 em_ctl = readl(mmio + HOST_EM_CTL);
414 ahci_rpm_put_port(ap);
415
416 return sprintf(buf, "%s%s%s%s\n",
417 em_ctl & EM_CTL_LED ? "led " : "",
418 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
419 em_ctl & EM_CTL_SES ? "ses-2 " : "",
420 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
421}
422
423/**
424 * ahci_save_initial_config - Save and fixup initial config values
425 * @dev: target AHCI device
426 * @hpriv: host private area to store config values
427 *
428 * Some registers containing configuration info might be setup by
429 * BIOS and might be cleared on reset. This function saves the
430 * initial values of those registers into @hpriv such that they
431 * can be restored after controller reset.
432 *
433 * If inconsistent, config values are fixed up by this function.
434 *
435 * If it is not set already this function sets hpriv->start_engine to
436 * ahci_start_engine.
437 *
438 * LOCKING:
439 * None.
440 */
441void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
442{
443 void __iomem *mmio = hpriv->mmio;
444 u32 cap, cap2, vers, port_map;
445 int i;
446
447 /* make sure AHCI mode is enabled before accessing CAP */
448 ahci_enable_ahci(mmio);
449
450 /* Values prefixed with saved_ are written back to host after
451 * reset. Values without are used for driver operation.
452 */
453 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
454 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
455
456 /* CAP2 register is only defined for AHCI 1.2 and later */
457 vers = readl(mmio + HOST_VERSION);
458 if ((vers >> 16) > 1 ||
459 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
460 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
461 else
462 hpriv->saved_cap2 = cap2 = 0;
463
464 /* some chips have errata preventing 64bit use */
465 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
466 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
467 cap &= ~HOST_CAP_64;
468 }
469
470 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
471 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
472 cap &= ~HOST_CAP_NCQ;
473 }
474
475 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
476 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
477 cap |= HOST_CAP_NCQ;
478 }
479
480 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
481 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
482 cap &= ~HOST_CAP_PMP;
483 }
484
485 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
486 dev_info(dev,
487 "controller can't do SNTF, turning off CAP_SNTF\n");
488 cap &= ~HOST_CAP_SNTF;
489 }
490
491 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
492 dev_info(dev,
493 "controller can't do DEVSLP, turning off\n");
494 cap2 &= ~HOST_CAP2_SDS;
495 cap2 &= ~HOST_CAP2_SADM;
496 }
497
498 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
499 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
500 cap |= HOST_CAP_FBS;
501 }
502
503 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
504 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
505 cap &= ~HOST_CAP_FBS;
506 }
507
508 if (!(cap & HOST_CAP_ALPM) && (hpriv->flags & AHCI_HFLAG_YES_ALPM)) {
509 dev_info(dev, "controller can do ALPM, turning on CAP_ALPM\n");
510 cap |= HOST_CAP_ALPM;
511 }
512
513 if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
514 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
515 port_map, hpriv->force_port_map);
516 port_map = hpriv->force_port_map;
517 hpriv->saved_port_map = port_map;
518 }
519
520 if (hpriv->mask_port_map) {
521 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
522 port_map,
523 port_map & hpriv->mask_port_map);
524 port_map &= hpriv->mask_port_map;
525 }
526
527 /* cross check port_map and cap.n_ports */
528 if (port_map) {
529 int map_ports = 0;
530
531 for (i = 0; i < AHCI_MAX_PORTS; i++)
532 if (port_map & (1 << i))
533 map_ports++;
534
535 /* If PI has more ports than n_ports, whine, clear
536 * port_map and let it be generated from n_ports.
537 */
538 if (map_ports > ahci_nr_ports(cap)) {
539 dev_warn(dev,
540 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
541 port_map, ahci_nr_ports(cap));
542 port_map = 0;
543 }
544 }
545
546 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
547 if (!port_map && vers < 0x10300) {
548 port_map = (1 << ahci_nr_ports(cap)) - 1;
549 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
550
551 /* write the fixed up value to the PI register */
552 hpriv->saved_port_map = port_map;
553 }
554
555 /* record values to use during operation */
556 hpriv->cap = cap;
557 hpriv->cap2 = cap2;
558 hpriv->version = readl(mmio + HOST_VERSION);
559 hpriv->port_map = port_map;
560
561 if (!hpriv->start_engine)
562 hpriv->start_engine = ahci_start_engine;
563
564 if (!hpriv->stop_engine)
565 hpriv->stop_engine = ahci_stop_engine;
566
567 if (!hpriv->irq_handler)
568 hpriv->irq_handler = ahci_single_level_irq_intr;
569}
570EXPORT_SYMBOL_GPL(ahci_save_initial_config);
571
572/**
573 * ahci_restore_initial_config - Restore initial config
574 * @host: target ATA host
575 *
576 * Restore initial config stored by ahci_save_initial_config().
577 *
578 * LOCKING:
579 * None.
580 */
581static void ahci_restore_initial_config(struct ata_host *host)
582{
583 struct ahci_host_priv *hpriv = host->private_data;
584 void __iomem *mmio = hpriv->mmio;
585
586 writel(hpriv->saved_cap, mmio + HOST_CAP);
587 if (hpriv->saved_cap2)
588 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
589 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
590 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
591}
592
593static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
594{
595 static const int offset[] = {
596 [SCR_STATUS] = PORT_SCR_STAT,
597 [SCR_CONTROL] = PORT_SCR_CTL,
598 [SCR_ERROR] = PORT_SCR_ERR,
599 [SCR_ACTIVE] = PORT_SCR_ACT,
600 [SCR_NOTIFICATION] = PORT_SCR_NTF,
601 };
602 struct ahci_host_priv *hpriv = ap->host->private_data;
603
604 if (sc_reg < ARRAY_SIZE(offset) &&
605 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
606 return offset[sc_reg];
607 return 0;
608}
609
610static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
611{
612 void __iomem *port_mmio = ahci_port_base(link->ap);
613 int offset = ahci_scr_offset(link->ap, sc_reg);
614
615 if (offset) {
616 *val = readl(port_mmio + offset);
617 return 0;
618 }
619 return -EINVAL;
620}
621
622static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
623{
624 void __iomem *port_mmio = ahci_port_base(link->ap);
625 int offset = ahci_scr_offset(link->ap, sc_reg);
626
627 if (offset) {
628 writel(val, port_mmio + offset);
629 return 0;
630 }
631 return -EINVAL;
632}
633
634void ahci_start_engine(struct ata_port *ap)
635{
636 void __iomem *port_mmio = ahci_port_base(ap);
637 u32 tmp;
638
639 /* start DMA */
640 tmp = readl(port_mmio + PORT_CMD);
641 tmp |= PORT_CMD_START;
642 writel(tmp, port_mmio + PORT_CMD);
643 readl(port_mmio + PORT_CMD); /* flush */
644}
645EXPORT_SYMBOL_GPL(ahci_start_engine);
646
647int ahci_stop_engine(struct ata_port *ap)
648{
649 void __iomem *port_mmio = ahci_port_base(ap);
650 struct ahci_host_priv *hpriv = ap->host->private_data;
651 u32 tmp;
652
653 /*
654 * On some controllers, stopping a port's DMA engine while the port
655 * is in ALPM state (partial or slumber) results in failures on
656 * subsequent DMA engine starts. For those controllers, put the
657 * port back in active state before stopping its DMA engine.
658 */
659 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) &&
660 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) &&
661 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) {
662 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n");
663 return -EIO;
664 }
665
666 tmp = readl(port_mmio + PORT_CMD);
667
668 /* check if the HBA is idle */
669 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
670 return 0;
671
672 /*
673 * Don't try to issue commands but return with ENODEV if the
674 * AHCI controller not available anymore (e.g. due to PCIe hot
675 * unplugging). Otherwise a 500ms delay for each port is added.
676 */
677 if (tmp == 0xffffffff) {
678 dev_err(ap->host->dev, "AHCI controller unavailable!\n");
679 return -ENODEV;
680 }
681
682 /* setting HBA to idle */
683 tmp &= ~PORT_CMD_START;
684 writel(tmp, port_mmio + PORT_CMD);
685
686 /* wait for engine to stop. This could be as long as 500 msec */
687 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
688 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
689 if (tmp & PORT_CMD_LIST_ON)
690 return -EIO;
691
692 return 0;
693}
694EXPORT_SYMBOL_GPL(ahci_stop_engine);
695
696void ahci_start_fis_rx(struct ata_port *ap)
697{
698 void __iomem *port_mmio = ahci_port_base(ap);
699 struct ahci_host_priv *hpriv = ap->host->private_data;
700 struct ahci_port_priv *pp = ap->private_data;
701 u32 tmp;
702
703 /* set FIS registers */
704 if (hpriv->cap & HOST_CAP_64)
705 writel((pp->cmd_slot_dma >> 16) >> 16,
706 port_mmio + PORT_LST_ADDR_HI);
707 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
708
709 if (hpriv->cap & HOST_CAP_64)
710 writel((pp->rx_fis_dma >> 16) >> 16,
711 port_mmio + PORT_FIS_ADDR_HI);
712 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
713
714 /* enable FIS reception */
715 tmp = readl(port_mmio + PORT_CMD);
716 tmp |= PORT_CMD_FIS_RX;
717 writel(tmp, port_mmio + PORT_CMD);
718
719 /* flush */
720 readl(port_mmio + PORT_CMD);
721}
722EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
723
724static int ahci_stop_fis_rx(struct ata_port *ap)
725{
726 void __iomem *port_mmio = ahci_port_base(ap);
727 u32 tmp;
728
729 /* disable FIS reception */
730 tmp = readl(port_mmio + PORT_CMD);
731 tmp &= ~PORT_CMD_FIS_RX;
732 writel(tmp, port_mmio + PORT_CMD);
733
734 /* wait for completion, spec says 500ms, give it 1000 */
735 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
736 PORT_CMD_FIS_ON, 10, 1000);
737 if (tmp & PORT_CMD_FIS_ON)
738 return -EBUSY;
739
740 return 0;
741}
742
743static void ahci_power_up(struct ata_port *ap)
744{
745 struct ahci_host_priv *hpriv = ap->host->private_data;
746 void __iomem *port_mmio = ahci_port_base(ap);
747 u32 cmd;
748
749 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
750
751 /* spin up device */
752 if (hpriv->cap & HOST_CAP_SSS) {
753 cmd |= PORT_CMD_SPIN_UP;
754 writel(cmd, port_mmio + PORT_CMD);
755 }
756
757 /* wake up link */
758 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
759}
760
761static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
762 unsigned int hints)
763{
764 struct ata_port *ap = link->ap;
765 struct ahci_host_priv *hpriv = ap->host->private_data;
766 struct ahci_port_priv *pp = ap->private_data;
767 void __iomem *port_mmio = ahci_port_base(ap);
768
769 if (policy != ATA_LPM_MAX_POWER) {
770 /* wakeup flag only applies to the max power policy */
771 hints &= ~ATA_LPM_WAKE_ONLY;
772
773 /*
774 * Disable interrupts on Phy Ready. This keeps us from
775 * getting woken up due to spurious phy ready
776 * interrupts.
777 */
778 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
779 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
780
781 sata_link_scr_lpm(link, policy, false);
782 }
783
784 if (hpriv->cap & HOST_CAP_ALPM) {
785 u32 cmd = readl(port_mmio + PORT_CMD);
786
787 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
788 if (!(hints & ATA_LPM_WAKE_ONLY))
789 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
790 cmd |= PORT_CMD_ICC_ACTIVE;
791
792 writel(cmd, port_mmio + PORT_CMD);
793 readl(port_mmio + PORT_CMD);
794
795 /* wait 10ms to be sure we've come out of LPM state */
796 ata_msleep(ap, 10);
797
798 if (hints & ATA_LPM_WAKE_ONLY)
799 return 0;
800 } else {
801 cmd |= PORT_CMD_ALPE;
802 if (policy == ATA_LPM_MIN_POWER)
803 cmd |= PORT_CMD_ASP;
804 else if (policy == ATA_LPM_MIN_POWER_WITH_PARTIAL)
805 cmd &= ~PORT_CMD_ASP;
806
807 /* write out new cmd value */
808 writel(cmd, port_mmio + PORT_CMD);
809 }
810 }
811
812 /* set aggressive device sleep */
813 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
814 (hpriv->cap2 & HOST_CAP2_SADM) &&
815 (link->device->flags & ATA_DFLAG_DEVSLP)) {
816 if (policy == ATA_LPM_MIN_POWER ||
817 policy == ATA_LPM_MIN_POWER_WITH_PARTIAL)
818 ahci_set_aggressive_devslp(ap, true);
819 else
820 ahci_set_aggressive_devslp(ap, false);
821 }
822
823 if (policy == ATA_LPM_MAX_POWER) {
824 sata_link_scr_lpm(link, policy, false);
825
826 /* turn PHYRDY IRQ back on */
827 pp->intr_mask |= PORT_IRQ_PHYRDY;
828 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
829 }
830
831 return 0;
832}
833
834#ifdef CONFIG_PM
835static void ahci_power_down(struct ata_port *ap)
836{
837 struct ahci_host_priv *hpriv = ap->host->private_data;
838 void __iomem *port_mmio = ahci_port_base(ap);
839 u32 cmd, scontrol;
840
841 if (!(hpriv->cap & HOST_CAP_SSS))
842 return;
843
844 /* put device into listen mode, first set PxSCTL.DET to 0 */
845 scontrol = readl(port_mmio + PORT_SCR_CTL);
846 scontrol &= ~0xf;
847 writel(scontrol, port_mmio + PORT_SCR_CTL);
848
849 /* then set PxCMD.SUD to 0 */
850 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
851 cmd &= ~PORT_CMD_SPIN_UP;
852 writel(cmd, port_mmio + PORT_CMD);
853}
854#endif
855
856static void ahci_start_port(struct ata_port *ap)
857{
858 struct ahci_host_priv *hpriv = ap->host->private_data;
859 struct ahci_port_priv *pp = ap->private_data;
860 struct ata_link *link;
861 struct ahci_em_priv *emp;
862 ssize_t rc;
863 int i;
864
865 /* enable FIS reception */
866 ahci_start_fis_rx(ap);
867
868 /* enable DMA */
869 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
870 hpriv->start_engine(ap);
871
872 /* turn on LEDs */
873 if (ap->flags & ATA_FLAG_EM) {
874 ata_for_each_link(link, ap, EDGE) {
875 emp = &pp->em_priv[link->pmp];
876
877 /* EM Transmit bit maybe busy during init */
878 for (i = 0; i < EM_MAX_RETRY; i++) {
879 rc = ap->ops->transmit_led_message(ap,
880 emp->led_state,
881 4);
882 /*
883 * If busy, give a breather but do not
884 * release EH ownership by using msleep()
885 * instead of ata_msleep(). EM Transmit
886 * bit is busy for the whole host and
887 * releasing ownership will cause other
888 * ports to fail the same way.
889 */
890 if (rc == -EBUSY)
891 msleep(1);
892 else
893 break;
894 }
895 }
896 }
897
898 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
899 ata_for_each_link(link, ap, EDGE)
900 ahci_init_sw_activity(link);
901
902}
903
904static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
905{
906 int rc;
907 struct ahci_host_priv *hpriv = ap->host->private_data;
908
909 /* disable DMA */
910 rc = hpriv->stop_engine(ap);
911 if (rc) {
912 *emsg = "failed to stop engine";
913 return rc;
914 }
915
916 /* disable FIS reception */
917 rc = ahci_stop_fis_rx(ap);
918 if (rc) {
919 *emsg = "failed stop FIS RX";
920 return rc;
921 }
922
923 return 0;
924}
925
926int ahci_reset_controller(struct ata_host *host)
927{
928 struct ahci_host_priv *hpriv = host->private_data;
929 void __iomem *mmio = hpriv->mmio;
930 u32 tmp;
931
932 /* we must be in AHCI mode, before using anything
933 * AHCI-specific, such as HOST_RESET.
934 */
935 ahci_enable_ahci(mmio);
936
937 /* global controller reset */
938 if (!ahci_skip_host_reset) {
939 tmp = readl(mmio + HOST_CTL);
940 if ((tmp & HOST_RESET) == 0) {
941 writel(tmp | HOST_RESET, mmio + HOST_CTL);
942 readl(mmio + HOST_CTL); /* flush */
943 }
944
945 /*
946 * to perform host reset, OS should set HOST_RESET
947 * and poll until this bit is read to be "0".
948 * reset must complete within 1 second, or
949 * the hardware should be considered fried.
950 */
951 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
952 HOST_RESET, 10, 1000);
953
954 if (tmp & HOST_RESET) {
955 dev_err(host->dev, "controller reset failed (0x%x)\n",
956 tmp);
957 return -EIO;
958 }
959
960 /* turn on AHCI mode */
961 ahci_enable_ahci(mmio);
962
963 /* Some registers might be cleared on reset. Restore
964 * initial values.
965 */
966 if (!(hpriv->flags & AHCI_HFLAG_NO_WRITE_TO_RO))
967 ahci_restore_initial_config(host);
968 } else
969 dev_info(host->dev, "skipping global host reset\n");
970
971 return 0;
972}
973EXPORT_SYMBOL_GPL(ahci_reset_controller);
974
975static void ahci_sw_activity(struct ata_link *link)
976{
977 struct ata_port *ap = link->ap;
978 struct ahci_port_priv *pp = ap->private_data;
979 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
980
981 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
982 return;
983
984 emp->activity++;
985 if (!timer_pending(&emp->timer))
986 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
987}
988
989static void ahci_sw_activity_blink(struct timer_list *t)
990{
991 struct ahci_em_priv *emp = from_timer(emp, t, timer);
992 struct ata_link *link = emp->link;
993 struct ata_port *ap = link->ap;
994
995 unsigned long led_message = emp->led_state;
996 u32 activity_led_state;
997 unsigned long flags;
998
999 led_message &= EM_MSG_LED_VALUE;
1000 led_message |= ap->port_no | (link->pmp << 8);
1001
1002 /* check to see if we've had activity. If so,
1003 * toggle state of LED and reset timer. If not,
1004 * turn LED to desired idle state.
1005 */
1006 spin_lock_irqsave(ap->lock, flags);
1007 if (emp->saved_activity != emp->activity) {
1008 emp->saved_activity = emp->activity;
1009 /* get the current LED state */
1010 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
1011
1012 if (activity_led_state)
1013 activity_led_state = 0;
1014 else
1015 activity_led_state = 1;
1016
1017 /* clear old state */
1018 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1019
1020 /* toggle state */
1021 led_message |= (activity_led_state << 16);
1022 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1023 } else {
1024 /* switch to idle */
1025 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1026 if (emp->blink_policy == BLINK_OFF)
1027 led_message |= (1 << 16);
1028 }
1029 spin_unlock_irqrestore(ap->lock, flags);
1030 ap->ops->transmit_led_message(ap, led_message, 4);
1031}
1032
1033static void ahci_init_sw_activity(struct ata_link *link)
1034{
1035 struct ata_port *ap = link->ap;
1036 struct ahci_port_priv *pp = ap->private_data;
1037 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1038
1039 /* init activity stats, setup timer */
1040 emp->saved_activity = emp->activity = 0;
1041 emp->link = link;
1042 timer_setup(&emp->timer, ahci_sw_activity_blink, 0);
1043
1044 /* check our blink policy and set flag for link if it's enabled */
1045 if (emp->blink_policy)
1046 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1047}
1048
1049int ahci_reset_em(struct ata_host *host)
1050{
1051 struct ahci_host_priv *hpriv = host->private_data;
1052 void __iomem *mmio = hpriv->mmio;
1053 u32 em_ctl;
1054
1055 em_ctl = readl(mmio + HOST_EM_CTL);
1056 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1057 return -EINVAL;
1058
1059 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1060 return 0;
1061}
1062EXPORT_SYMBOL_GPL(ahci_reset_em);
1063
1064static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1065 ssize_t size)
1066{
1067 struct ahci_host_priv *hpriv = ap->host->private_data;
1068 struct ahci_port_priv *pp = ap->private_data;
1069 void __iomem *mmio = hpriv->mmio;
1070 u32 em_ctl;
1071 u32 message[] = {0, 0};
1072 unsigned long flags;
1073 int pmp;
1074 struct ahci_em_priv *emp;
1075
1076 /* get the slot number from the message */
1077 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1078 if (pmp < EM_MAX_SLOTS)
1079 emp = &pp->em_priv[pmp];
1080 else
1081 return -EINVAL;
1082
1083 ahci_rpm_get_port(ap);
1084 spin_lock_irqsave(ap->lock, flags);
1085
1086 /*
1087 * if we are still busy transmitting a previous message,
1088 * do not allow
1089 */
1090 em_ctl = readl(mmio + HOST_EM_CTL);
1091 if (em_ctl & EM_CTL_TM) {
1092 spin_unlock_irqrestore(ap->lock, flags);
1093 ahci_rpm_put_port(ap);
1094 return -EBUSY;
1095 }
1096
1097 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1098 /*
1099 * create message header - this is all zero except for
1100 * the message size, which is 4 bytes.
1101 */
1102 message[0] |= (4 << 8);
1103
1104 /* ignore 0:4 of byte zero, fill in port info yourself */
1105 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1106
1107 /* write message to EM_LOC */
1108 writel(message[0], mmio + hpriv->em_loc);
1109 writel(message[1], mmio + hpriv->em_loc+4);
1110
1111 /*
1112 * tell hardware to transmit the message
1113 */
1114 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1115 }
1116
1117 /* save off new led state for port/slot */
1118 emp->led_state = state;
1119
1120 spin_unlock_irqrestore(ap->lock, flags);
1121 ahci_rpm_put_port(ap);
1122
1123 return size;
1124}
1125
1126static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1127{
1128 struct ahci_port_priv *pp = ap->private_data;
1129 struct ata_link *link;
1130 struct ahci_em_priv *emp;
1131 int rc = 0;
1132
1133 ata_for_each_link(link, ap, EDGE) {
1134 emp = &pp->em_priv[link->pmp];
1135 rc += sprintf(buf, "%lx\n", emp->led_state);
1136 }
1137 return rc;
1138}
1139
1140static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1141 size_t size)
1142{
1143 unsigned int state;
1144 int pmp;
1145 struct ahci_port_priv *pp = ap->private_data;
1146 struct ahci_em_priv *emp;
1147
1148 if (kstrtouint(buf, 0, &state) < 0)
1149 return -EINVAL;
1150
1151 /* get the slot number from the message */
1152 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1153 if (pmp < EM_MAX_SLOTS) {
1154 pmp = array_index_nospec(pmp, EM_MAX_SLOTS);
1155 emp = &pp->em_priv[pmp];
1156 } else {
1157 return -EINVAL;
1158 }
1159
1160 /* mask off the activity bits if we are in sw_activity
1161 * mode, user should turn off sw_activity before setting
1162 * activity led through em_message
1163 */
1164 if (emp->blink_policy)
1165 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1166
1167 return ap->ops->transmit_led_message(ap, state, size);
1168}
1169
1170static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1171{
1172 struct ata_link *link = dev->link;
1173 struct ata_port *ap = link->ap;
1174 struct ahci_port_priv *pp = ap->private_data;
1175 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1176 u32 port_led_state = emp->led_state;
1177
1178 /* save the desired Activity LED behavior */
1179 if (val == OFF) {
1180 /* clear LFLAG */
1181 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1182
1183 /* set the LED to OFF */
1184 port_led_state &= EM_MSG_LED_VALUE_OFF;
1185 port_led_state |= (ap->port_no | (link->pmp << 8));
1186 ap->ops->transmit_led_message(ap, port_led_state, 4);
1187 } else {
1188 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1189 if (val == BLINK_OFF) {
1190 /* set LED to ON for idle */
1191 port_led_state &= EM_MSG_LED_VALUE_OFF;
1192 port_led_state |= (ap->port_no | (link->pmp << 8));
1193 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1194 ap->ops->transmit_led_message(ap, port_led_state, 4);
1195 }
1196 }
1197 emp->blink_policy = val;
1198 return 0;
1199}
1200
1201static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1202{
1203 struct ata_link *link = dev->link;
1204 struct ata_port *ap = link->ap;
1205 struct ahci_port_priv *pp = ap->private_data;
1206 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1207
1208 /* display the saved value of activity behavior for this
1209 * disk.
1210 */
1211 return sprintf(buf, "%d\n", emp->blink_policy);
1212}
1213
1214static void ahci_port_init(struct device *dev, struct ata_port *ap,
1215 int port_no, void __iomem *mmio,
1216 void __iomem *port_mmio)
1217{
1218 struct ahci_host_priv *hpriv = ap->host->private_data;
1219 const char *emsg = NULL;
1220 int rc;
1221 u32 tmp;
1222
1223 /* make sure port is not active */
1224 rc = ahci_deinit_port(ap, &emsg);
1225 if (rc)
1226 dev_warn(dev, "%s (%d)\n", emsg, rc);
1227
1228 /* clear SError */
1229 tmp = readl(port_mmio + PORT_SCR_ERR);
1230 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1231 writel(tmp, port_mmio + PORT_SCR_ERR);
1232
1233 /* clear port IRQ */
1234 tmp = readl(port_mmio + PORT_IRQ_STAT);
1235 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1236 if (tmp)
1237 writel(tmp, port_mmio + PORT_IRQ_STAT);
1238
1239 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1240
1241 /* mark esata ports */
1242 tmp = readl(port_mmio + PORT_CMD);
1243 if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS))
1244 ap->pflags |= ATA_PFLAG_EXTERNAL;
1245}
1246
1247void ahci_init_controller(struct ata_host *host)
1248{
1249 struct ahci_host_priv *hpriv = host->private_data;
1250 void __iomem *mmio = hpriv->mmio;
1251 int i;
1252 void __iomem *port_mmio;
1253 u32 tmp;
1254
1255 for (i = 0; i < host->n_ports; i++) {
1256 struct ata_port *ap = host->ports[i];
1257
1258 port_mmio = ahci_port_base(ap);
1259 if (ata_port_is_dummy(ap))
1260 continue;
1261
1262 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1263 }
1264
1265 tmp = readl(mmio + HOST_CTL);
1266 VPRINTK("HOST_CTL 0x%x\n", tmp);
1267 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1268 tmp = readl(mmio + HOST_CTL);
1269 VPRINTK("HOST_CTL 0x%x\n", tmp);
1270}
1271EXPORT_SYMBOL_GPL(ahci_init_controller);
1272
1273static void ahci_dev_config(struct ata_device *dev)
1274{
1275 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1276
1277 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1278 dev->max_sectors = 255;
1279 ata_dev_info(dev,
1280 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1281 }
1282}
1283
1284unsigned int ahci_dev_classify(struct ata_port *ap)
1285{
1286 void __iomem *port_mmio = ahci_port_base(ap);
1287 struct ata_taskfile tf;
1288 u32 tmp;
1289
1290 tmp = readl(port_mmio + PORT_SIG);
1291 tf.lbah = (tmp >> 24) & 0xff;
1292 tf.lbam = (tmp >> 16) & 0xff;
1293 tf.lbal = (tmp >> 8) & 0xff;
1294 tf.nsect = (tmp) & 0xff;
1295
1296 return ata_dev_classify(&tf);
1297}
1298EXPORT_SYMBOL_GPL(ahci_dev_classify);
1299
1300void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1301 u32 opts)
1302{
1303 dma_addr_t cmd_tbl_dma;
1304
1305 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1306
1307 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1308 pp->cmd_slot[tag].status = 0;
1309 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1310 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1311}
1312EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
1313
1314int ahci_kick_engine(struct ata_port *ap)
1315{
1316 void __iomem *port_mmio = ahci_port_base(ap);
1317 struct ahci_host_priv *hpriv = ap->host->private_data;
1318 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1319 u32 tmp;
1320 int busy, rc;
1321
1322 /* stop engine */
1323 rc = hpriv->stop_engine(ap);
1324 if (rc)
1325 goto out_restart;
1326
1327 /* need to do CLO?
1328 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1329 */
1330 busy = status & (ATA_BUSY | ATA_DRQ);
1331 if (!busy && !sata_pmp_attached(ap)) {
1332 rc = 0;
1333 goto out_restart;
1334 }
1335
1336 if (!(hpriv->cap & HOST_CAP_CLO)) {
1337 rc = -EOPNOTSUPP;
1338 goto out_restart;
1339 }
1340
1341 /* perform CLO */
1342 tmp = readl(port_mmio + PORT_CMD);
1343 tmp |= PORT_CMD_CLO;
1344 writel(tmp, port_mmio + PORT_CMD);
1345
1346 rc = 0;
1347 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1348 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1349 if (tmp & PORT_CMD_CLO)
1350 rc = -EIO;
1351
1352 /* restart engine */
1353 out_restart:
1354 hpriv->start_engine(ap);
1355 return rc;
1356}
1357EXPORT_SYMBOL_GPL(ahci_kick_engine);
1358
1359static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1360 struct ata_taskfile *tf, int is_cmd, u16 flags,
1361 unsigned long timeout_msec)
1362{
1363 const u32 cmd_fis_len = 5; /* five dwords */
1364 struct ahci_port_priv *pp = ap->private_data;
1365 void __iomem *port_mmio = ahci_port_base(ap);
1366 u8 *fis = pp->cmd_tbl;
1367 u32 tmp;
1368
1369 /* prep the command */
1370 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1371 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1372
1373 /* set port value for softreset of Port Multiplier */
1374 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) {
1375 tmp = readl(port_mmio + PORT_FBS);
1376 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1377 tmp |= pmp << PORT_FBS_DEV_OFFSET;
1378 writel(tmp, port_mmio + PORT_FBS);
1379 pp->fbs_last_dev = pmp;
1380 }
1381
1382 /* issue & wait */
1383 writel(1, port_mmio + PORT_CMD_ISSUE);
1384
1385 if (timeout_msec) {
1386 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1387 0x1, 0x1, 1, timeout_msec);
1388 if (tmp & 0x1) {
1389 ahci_kick_engine(ap);
1390 return -EBUSY;
1391 }
1392 } else
1393 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1394
1395 return 0;
1396}
1397
1398int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1399 int pmp, unsigned long deadline,
1400 int (*check_ready)(struct ata_link *link))
1401{
1402 struct ata_port *ap = link->ap;
1403 struct ahci_host_priv *hpriv = ap->host->private_data;
1404 struct ahci_port_priv *pp = ap->private_data;
1405 const char *reason = NULL;
1406 unsigned long now, msecs;
1407 struct ata_taskfile tf;
1408 bool fbs_disabled = false;
1409 int rc;
1410
1411 DPRINTK("ENTER\n");
1412
1413 /* prepare for SRST (AHCI-1.1 10.4.1) */
1414 rc = ahci_kick_engine(ap);
1415 if (rc && rc != -EOPNOTSUPP)
1416 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
1417
1418 /*
1419 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1420 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1421 * that is attached to port multiplier.
1422 */
1423 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1424 ahci_disable_fbs(ap);
1425 fbs_disabled = true;
1426 }
1427
1428 ata_tf_init(link->device, &tf);
1429
1430 /* issue the first H2D Register FIS */
1431 msecs = 0;
1432 now = jiffies;
1433 if (time_after(deadline, now))
1434 msecs = jiffies_to_msecs(deadline - now);
1435
1436 tf.ctl |= ATA_SRST;
1437 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1438 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1439 rc = -EIO;
1440 reason = "1st FIS failed";
1441 goto fail;
1442 }
1443
1444 /* spec says at least 5us, but be generous and sleep for 1ms */
1445 ata_msleep(ap, 1);
1446
1447 /* issue the second H2D Register FIS */
1448 tf.ctl &= ~ATA_SRST;
1449 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1450
1451 /* wait for link to become ready */
1452 rc = ata_wait_after_reset(link, deadline, check_ready);
1453 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1454 /*
1455 * Workaround for cases where link online status can't
1456 * be trusted. Treat device readiness timeout as link
1457 * offline.
1458 */
1459 ata_link_info(link, "device not ready, treating as offline\n");
1460 *class = ATA_DEV_NONE;
1461 } else if (rc) {
1462 /* link occupied, -ENODEV too is an error */
1463 reason = "device not ready";
1464 goto fail;
1465 } else
1466 *class = ahci_dev_classify(ap);
1467
1468 /* re-enable FBS if disabled before */
1469 if (fbs_disabled)
1470 ahci_enable_fbs(ap);
1471
1472 DPRINTK("EXIT, class=%u\n", *class);
1473 return 0;
1474
1475 fail:
1476 ata_link_err(link, "softreset failed (%s)\n", reason);
1477 return rc;
1478}
1479
1480int ahci_check_ready(struct ata_link *link)
1481{
1482 void __iomem *port_mmio = ahci_port_base(link->ap);
1483 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1484
1485 return ata_check_ready(status);
1486}
1487EXPORT_SYMBOL_GPL(ahci_check_ready);
1488
1489static int ahci_softreset(struct ata_link *link, unsigned int *class,
1490 unsigned long deadline)
1491{
1492 int pmp = sata_srst_pmp(link);
1493
1494 DPRINTK("ENTER\n");
1495
1496 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1497}
1498EXPORT_SYMBOL_GPL(ahci_do_softreset);
1499
1500static int ahci_bad_pmp_check_ready(struct ata_link *link)
1501{
1502 void __iomem *port_mmio = ahci_port_base(link->ap);
1503 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1504 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1505
1506 /*
1507 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1508 * which can save timeout delay.
1509 */
1510 if (irq_status & PORT_IRQ_BAD_PMP)
1511 return -EIO;
1512
1513 return ata_check_ready(status);
1514}
1515
1516static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1517 unsigned long deadline)
1518{
1519 struct ata_port *ap = link->ap;
1520 void __iomem *port_mmio = ahci_port_base(ap);
1521 int pmp = sata_srst_pmp(link);
1522 int rc;
1523 u32 irq_sts;
1524
1525 DPRINTK("ENTER\n");
1526
1527 rc = ahci_do_softreset(link, class, pmp, deadline,
1528 ahci_bad_pmp_check_ready);
1529
1530 /*
1531 * Soft reset fails with IPMS set when PMP is enabled but
1532 * SATA HDD/ODD is connected to SATA port, do soft reset
1533 * again to port 0.
1534 */
1535 if (rc == -EIO) {
1536 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1537 if (irq_sts & PORT_IRQ_BAD_PMP) {
1538 ata_link_warn(link,
1539 "applying PMP SRST workaround "
1540 "and retrying\n");
1541 rc = ahci_do_softreset(link, class, 0, deadline,
1542 ahci_check_ready);
1543 }
1544 }
1545
1546 return rc;
1547}
1548
1549int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
1550 unsigned long deadline, bool *online)
1551{
1552 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1553 struct ata_port *ap = link->ap;
1554 struct ahci_port_priv *pp = ap->private_data;
1555 struct ahci_host_priv *hpriv = ap->host->private_data;
1556 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1557 struct ata_taskfile tf;
1558 int rc;
1559
1560 DPRINTK("ENTER\n");
1561
1562 hpriv->stop_engine(ap);
1563
1564 /* clear D2H reception area to properly wait for D2H FIS */
1565 ata_tf_init(link->device, &tf);
1566 tf.command = ATA_BUSY;
1567 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1568
1569 rc = sata_link_hardreset(link, timing, deadline, online,
1570 ahci_check_ready);
1571
1572 hpriv->start_engine(ap);
1573
1574 if (*online)
1575 *class = ahci_dev_classify(ap);
1576
1577 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1578 return rc;
1579}
1580EXPORT_SYMBOL_GPL(ahci_do_hardreset);
1581
1582static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1583 unsigned long deadline)
1584{
1585 bool online;
1586
1587 return ahci_do_hardreset(link, class, deadline, &online);
1588}
1589
1590static void ahci_postreset(struct ata_link *link, unsigned int *class)
1591{
1592 struct ata_port *ap = link->ap;
1593 void __iomem *port_mmio = ahci_port_base(ap);
1594 u32 new_tmp, tmp;
1595
1596 ata_std_postreset(link, class);
1597
1598 /* Make sure port's ATAPI bit is set appropriately */
1599 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1600 if (*class == ATA_DEV_ATAPI)
1601 new_tmp |= PORT_CMD_ATAPI;
1602 else
1603 new_tmp &= ~PORT_CMD_ATAPI;
1604 if (new_tmp != tmp) {
1605 writel(new_tmp, port_mmio + PORT_CMD);
1606 readl(port_mmio + PORT_CMD); /* flush */
1607 }
1608}
1609
1610static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1611{
1612 struct scatterlist *sg;
1613 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1614 unsigned int si;
1615
1616 VPRINTK("ENTER\n");
1617
1618 /*
1619 * Next, the S/G list.
1620 */
1621 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1622 dma_addr_t addr = sg_dma_address(sg);
1623 u32 sg_len = sg_dma_len(sg);
1624
1625 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1626 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1627 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1628 }
1629
1630 return si;
1631}
1632
1633static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1634{
1635 struct ata_port *ap = qc->ap;
1636 struct ahci_port_priv *pp = ap->private_data;
1637
1638 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1639 return ata_std_qc_defer(qc);
1640 else
1641 return sata_pmp_qc_defer_cmd_switch(qc);
1642}
1643
1644static void ahci_qc_prep(struct ata_queued_cmd *qc)
1645{
1646 struct ata_port *ap = qc->ap;
1647 struct ahci_port_priv *pp = ap->private_data;
1648 int is_atapi = ata_is_atapi(qc->tf.protocol);
1649 void *cmd_tbl;
1650 u32 opts;
1651 const u32 cmd_fis_len = 5; /* five dwords */
1652 unsigned int n_elem;
1653
1654 /*
1655 * Fill in command table information. First, the header,
1656 * a SATA Register - Host to Device command FIS.
1657 */
1658 cmd_tbl = pp->cmd_tbl + qc->hw_tag * AHCI_CMD_TBL_SZ;
1659
1660 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1661 if (is_atapi) {
1662 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1663 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1664 }
1665
1666 n_elem = 0;
1667 if (qc->flags & ATA_QCFLAG_DMAMAP)
1668 n_elem = ahci_fill_sg(qc, cmd_tbl);
1669
1670 /*
1671 * Fill in command slot information.
1672 */
1673 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1674 if (qc->tf.flags & ATA_TFLAG_WRITE)
1675 opts |= AHCI_CMD_WRITE;
1676 if (is_atapi)
1677 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1678
1679 ahci_fill_cmd_slot(pp, qc->hw_tag, opts);
1680}
1681
1682static void ahci_fbs_dec_intr(struct ata_port *ap)
1683{
1684 struct ahci_port_priv *pp = ap->private_data;
1685 void __iomem *port_mmio = ahci_port_base(ap);
1686 u32 fbs = readl(port_mmio + PORT_FBS);
1687 int retries = 3;
1688
1689 DPRINTK("ENTER\n");
1690 BUG_ON(!pp->fbs_enabled);
1691
1692 /* time to wait for DEC is not specified by AHCI spec,
1693 * add a retry loop for safety.
1694 */
1695 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1696 fbs = readl(port_mmio + PORT_FBS);
1697 while ((fbs & PORT_FBS_DEC) && retries--) {
1698 udelay(1);
1699 fbs = readl(port_mmio + PORT_FBS);
1700 }
1701
1702 if (fbs & PORT_FBS_DEC)
1703 dev_err(ap->host->dev, "failed to clear device error\n");
1704}
1705
1706static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1707{
1708 struct ahci_host_priv *hpriv = ap->host->private_data;
1709 struct ahci_port_priv *pp = ap->private_data;
1710 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1711 struct ata_link *link = NULL;
1712 struct ata_queued_cmd *active_qc;
1713 struct ata_eh_info *active_ehi;
1714 bool fbs_need_dec = false;
1715 u32 serror;
1716
1717 /* determine active link with error */
1718 if (pp->fbs_enabled) {
1719 void __iomem *port_mmio = ahci_port_base(ap);
1720 u32 fbs = readl(port_mmio + PORT_FBS);
1721 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1722
1723 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
1724 link = &ap->pmp_link[pmp];
1725 fbs_need_dec = true;
1726 }
1727
1728 } else
1729 ata_for_each_link(link, ap, EDGE)
1730 if (ata_link_active(link))
1731 break;
1732
1733 if (!link)
1734 link = &ap->link;
1735
1736 active_qc = ata_qc_from_tag(ap, link->active_tag);
1737 active_ehi = &link->eh_info;
1738
1739 /* record irq stat */
1740 ata_ehi_clear_desc(host_ehi);
1741 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1742
1743 /* AHCI needs SError cleared; otherwise, it might lock up */
1744 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1745 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1746 host_ehi->serror |= serror;
1747
1748 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1749 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1750 irq_stat &= ~PORT_IRQ_IF_ERR;
1751
1752 if (irq_stat & PORT_IRQ_TF_ERR) {
1753 /* If qc is active, charge it; otherwise, the active
1754 * link. There's no active qc on NCQ errors. It will
1755 * be determined by EH by reading log page 10h.
1756 */
1757 if (active_qc)
1758 active_qc->err_mask |= AC_ERR_DEV;
1759 else
1760 active_ehi->err_mask |= AC_ERR_DEV;
1761
1762 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1763 host_ehi->serror &= ~SERR_INTERNAL;
1764 }
1765
1766 if (irq_stat & PORT_IRQ_UNK_FIS) {
1767 u32 *unk = pp->rx_fis + RX_FIS_UNK;
1768
1769 active_ehi->err_mask |= AC_ERR_HSM;
1770 active_ehi->action |= ATA_EH_RESET;
1771 ata_ehi_push_desc(active_ehi,
1772 "unknown FIS %08x %08x %08x %08x" ,
1773 unk[0], unk[1], unk[2], unk[3]);
1774 }
1775
1776 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1777 active_ehi->err_mask |= AC_ERR_HSM;
1778 active_ehi->action |= ATA_EH_RESET;
1779 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1780 }
1781
1782 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1783 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1784 host_ehi->action |= ATA_EH_RESET;
1785 ata_ehi_push_desc(host_ehi, "host bus error");
1786 }
1787
1788 if (irq_stat & PORT_IRQ_IF_ERR) {
1789 if (fbs_need_dec)
1790 active_ehi->err_mask |= AC_ERR_DEV;
1791 else {
1792 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1793 host_ehi->action |= ATA_EH_RESET;
1794 }
1795
1796 ata_ehi_push_desc(host_ehi, "interface fatal error");
1797 }
1798
1799 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1800 ata_ehi_hotplugged(host_ehi);
1801 ata_ehi_push_desc(host_ehi, "%s",
1802 irq_stat & PORT_IRQ_CONNECT ?
1803 "connection status changed" : "PHY RDY changed");
1804 }
1805
1806 /* okay, let's hand over to EH */
1807
1808 if (irq_stat & PORT_IRQ_FREEZE)
1809 ata_port_freeze(ap);
1810 else if (fbs_need_dec) {
1811 ata_link_abort(link);
1812 ahci_fbs_dec_intr(ap);
1813 } else
1814 ata_port_abort(ap);
1815}
1816
1817static void ahci_handle_port_interrupt(struct ata_port *ap,
1818 void __iomem *port_mmio, u32 status)
1819{
1820 struct ata_eh_info *ehi = &ap->link.eh_info;
1821 struct ahci_port_priv *pp = ap->private_data;
1822 struct ahci_host_priv *hpriv = ap->host->private_data;
1823 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1824 u32 qc_active = 0;
1825 int rc;
1826
1827 /* ignore BAD_PMP while resetting */
1828 if (unlikely(resetting))
1829 status &= ~PORT_IRQ_BAD_PMP;
1830
1831 if (sata_lpm_ignore_phy_events(&ap->link)) {
1832 status &= ~PORT_IRQ_PHYRDY;
1833 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
1834 }
1835
1836 if (unlikely(status & PORT_IRQ_ERROR)) {
1837 ahci_error_intr(ap, status);
1838 return;
1839 }
1840
1841 if (status & PORT_IRQ_SDB_FIS) {
1842 /* If SNotification is available, leave notification
1843 * handling to sata_async_notification(). If not,
1844 * emulate it by snooping SDB FIS RX area.
1845 *
1846 * Snooping FIS RX area is probably cheaper than
1847 * poking SNotification but some constrollers which
1848 * implement SNotification, ICH9 for example, don't
1849 * store AN SDB FIS into receive area.
1850 */
1851 if (hpriv->cap & HOST_CAP_SNTF)
1852 sata_async_notification(ap);
1853 else {
1854 /* If the 'N' bit in word 0 of the FIS is set,
1855 * we just received asynchronous notification.
1856 * Tell libata about it.
1857 *
1858 * Lack of SNotification should not appear in
1859 * ahci 1.2, so the workaround is unnecessary
1860 * when FBS is enabled.
1861 */
1862 if (pp->fbs_enabled)
1863 WARN_ON_ONCE(1);
1864 else {
1865 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1866 u32 f0 = le32_to_cpu(f[0]);
1867 if (f0 & (1 << 15))
1868 sata_async_notification(ap);
1869 }
1870 }
1871 }
1872
1873 /* pp->active_link is not reliable once FBS is enabled, both
1874 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1875 * NCQ and non-NCQ commands may be in flight at the same time.
1876 */
1877 if (pp->fbs_enabled) {
1878 if (ap->qc_active) {
1879 qc_active = readl(port_mmio + PORT_SCR_ACT);
1880 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1881 }
1882 } else {
1883 /* pp->active_link is valid iff any command is in flight */
1884 if (ap->qc_active && pp->active_link->sactive)
1885 qc_active = readl(port_mmio + PORT_SCR_ACT);
1886 else
1887 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1888 }
1889
1890
1891 rc = ata_qc_complete_multiple(ap, qc_active);
1892
1893 /* while resetting, invalid completions are expected */
1894 if (unlikely(rc < 0 && !resetting)) {
1895 ehi->err_mask |= AC_ERR_HSM;
1896 ehi->action |= ATA_EH_RESET;
1897 ata_port_freeze(ap);
1898 }
1899}
1900
1901static void ahci_port_intr(struct ata_port *ap)
1902{
1903 void __iomem *port_mmio = ahci_port_base(ap);
1904 u32 status;
1905
1906 status = readl(port_mmio + PORT_IRQ_STAT);
1907 writel(status, port_mmio + PORT_IRQ_STAT);
1908
1909 ahci_handle_port_interrupt(ap, port_mmio, status);
1910}
1911
1912static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
1913{
1914 struct ata_port *ap = dev_instance;
1915 void __iomem *port_mmio = ahci_port_base(ap);
1916 u32 status;
1917
1918 VPRINTK("ENTER\n");
1919
1920 status = readl(port_mmio + PORT_IRQ_STAT);
1921 writel(status, port_mmio + PORT_IRQ_STAT);
1922
1923 spin_lock(ap->lock);
1924 ahci_handle_port_interrupt(ap, port_mmio, status);
1925 spin_unlock(ap->lock);
1926
1927 VPRINTK("EXIT\n");
1928
1929 return IRQ_HANDLED;
1930}
1931
1932u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
1933{
1934 unsigned int i, handled = 0;
1935
1936 for (i = 0; i < host->n_ports; i++) {
1937 struct ata_port *ap;
1938
1939 if (!(irq_masked & (1 << i)))
1940 continue;
1941
1942 ap = host->ports[i];
1943 if (ap) {
1944 ahci_port_intr(ap);
1945 VPRINTK("port %u\n", i);
1946 } else {
1947 VPRINTK("port %u (no irq)\n", i);
1948 if (ata_ratelimit())
1949 dev_warn(host->dev,
1950 "interrupt on disabled port %u\n", i);
1951 }
1952
1953 handled = 1;
1954 }
1955
1956 return handled;
1957}
1958EXPORT_SYMBOL_GPL(ahci_handle_port_intr);
1959
1960static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
1961{
1962 struct ata_host *host = dev_instance;
1963 struct ahci_host_priv *hpriv;
1964 unsigned int rc = 0;
1965 void __iomem *mmio;
1966 u32 irq_stat, irq_masked;
1967
1968 VPRINTK("ENTER\n");
1969
1970 hpriv = host->private_data;
1971 mmio = hpriv->mmio;
1972
1973 /* sigh. 0xffffffff is a valid return from h/w */
1974 irq_stat = readl(mmio + HOST_IRQ_STAT);
1975 if (!irq_stat)
1976 return IRQ_NONE;
1977
1978 irq_masked = irq_stat & hpriv->port_map;
1979
1980 spin_lock(&host->lock);
1981
1982 rc = ahci_handle_port_intr(host, irq_masked);
1983
1984 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1985 * it should be cleared after all the port events are cleared;
1986 * otherwise, it will raise a spurious interrupt after each
1987 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1988 * information.
1989 *
1990 * Also, use the unmasked value to clear interrupt as spurious
1991 * pending event on a dummy port might cause screaming IRQ.
1992 */
1993 writel(irq_stat, mmio + HOST_IRQ_STAT);
1994
1995 spin_unlock(&host->lock);
1996
1997 VPRINTK("EXIT\n");
1998
1999 return IRQ_RETVAL(rc);
2000}
2001
2002unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
2003{
2004 struct ata_port *ap = qc->ap;
2005 void __iomem *port_mmio = ahci_port_base(ap);
2006 struct ahci_port_priv *pp = ap->private_data;
2007
2008 /* Keep track of the currently active link. It will be used
2009 * in completion path to determine whether NCQ phase is in
2010 * progress.
2011 */
2012 pp->active_link = qc->dev->link;
2013
2014 if (ata_is_ncq(qc->tf.protocol))
2015 writel(1 << qc->hw_tag, port_mmio + PORT_SCR_ACT);
2016
2017 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
2018 u32 fbs = readl(port_mmio + PORT_FBS);
2019 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
2020 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
2021 writel(fbs, port_mmio + PORT_FBS);
2022 pp->fbs_last_dev = qc->dev->link->pmp;
2023 }
2024
2025 writel(1 << qc->hw_tag, port_mmio + PORT_CMD_ISSUE);
2026
2027 ahci_sw_activity(qc->dev->link);
2028
2029 return 0;
2030}
2031EXPORT_SYMBOL_GPL(ahci_qc_issue);
2032
2033static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2034{
2035 struct ahci_port_priv *pp = qc->ap->private_data;
2036 u8 *rx_fis = pp->rx_fis;
2037
2038 if (pp->fbs_enabled)
2039 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
2040
2041 /*
2042 * After a successful execution of an ATA PIO data-in command,
2043 * the device doesn't send D2H Reg FIS to update the TF and
2044 * the host should take TF and E_Status from the preceding PIO
2045 * Setup FIS.
2046 */
2047 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
2048 !(qc->flags & ATA_QCFLAG_FAILED)) {
2049 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
2050 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
2051 } else
2052 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
2053
2054 return true;
2055}
2056
2057static void ahci_freeze(struct ata_port *ap)
2058{
2059 void __iomem *port_mmio = ahci_port_base(ap);
2060
2061 /* turn IRQ off */
2062 writel(0, port_mmio + PORT_IRQ_MASK);
2063}
2064
2065static void ahci_thaw(struct ata_port *ap)
2066{
2067 struct ahci_host_priv *hpriv = ap->host->private_data;
2068 void __iomem *mmio = hpriv->mmio;
2069 void __iomem *port_mmio = ahci_port_base(ap);
2070 u32 tmp;
2071 struct ahci_port_priv *pp = ap->private_data;
2072
2073 /* clear IRQ */
2074 tmp = readl(port_mmio + PORT_IRQ_STAT);
2075 writel(tmp, port_mmio + PORT_IRQ_STAT);
2076 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2077
2078 /* turn IRQ back on */
2079 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2080}
2081
2082void ahci_error_handler(struct ata_port *ap)
2083{
2084 struct ahci_host_priv *hpriv = ap->host->private_data;
2085
2086 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2087 /* restart engine */
2088 hpriv->stop_engine(ap);
2089 hpriv->start_engine(ap);
2090 }
2091
2092 sata_pmp_error_handler(ap);
2093
2094 if (!ata_dev_enabled(ap->link.device))
2095 hpriv->stop_engine(ap);
2096}
2097EXPORT_SYMBOL_GPL(ahci_error_handler);
2098
2099static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2100{
2101 struct ata_port *ap = qc->ap;
2102
2103 /* make DMA engine forget about the failed command */
2104 if (qc->flags & ATA_QCFLAG_FAILED)
2105 ahci_kick_engine(ap);
2106}
2107
2108static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2109{
2110 struct ahci_host_priv *hpriv = ap->host->private_data;
2111 void __iomem *port_mmio = ahci_port_base(ap);
2112 struct ata_device *dev = ap->link.device;
2113 u32 devslp, dm, dito, mdat, deto, dito_conf;
2114 int rc;
2115 unsigned int err_mask;
2116
2117 devslp = readl(port_mmio + PORT_DEVSLP);
2118 if (!(devslp & PORT_DEVSLP_DSP)) {
2119 dev_info(ap->host->dev, "port does not support device sleep\n");
2120 return;
2121 }
2122
2123 /* disable device sleep */
2124 if (!sleep) {
2125 if (devslp & PORT_DEVSLP_ADSE) {
2126 writel(devslp & ~PORT_DEVSLP_ADSE,
2127 port_mmio + PORT_DEVSLP);
2128 err_mask = ata_dev_set_feature(dev,
2129 SETFEATURES_SATA_DISABLE,
2130 SATA_DEVSLP);
2131 if (err_mask && err_mask != AC_ERR_DEV)
2132 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2133 }
2134 return;
2135 }
2136
2137 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2138 dito = devslp_idle_timeout / (dm + 1);
2139 if (dito > 0x3ff)
2140 dito = 0x3ff;
2141
2142 dito_conf = (devslp >> PORT_DEVSLP_DITO_OFFSET) & 0x3FF;
2143
2144 /* device sleep was already enabled and same dito */
2145 if ((devslp & PORT_DEVSLP_ADSE) && (dito_conf == dito))
2146 return;
2147
2148 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2149 rc = hpriv->stop_engine(ap);
2150 if (rc)
2151 return;
2152
2153 /* Use the nominal value 10 ms if the read MDAT is zero,
2154 * the nominal value of DETO is 20 ms.
2155 */
2156 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
2157 ATA_LOG_DEVSLP_VALID_MASK) {
2158 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
2159 ATA_LOG_DEVSLP_MDAT_MASK;
2160 if (!mdat)
2161 mdat = 10;
2162 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
2163 if (!deto)
2164 deto = 20;
2165 } else {
2166 mdat = 10;
2167 deto = 20;
2168 }
2169
2170 /* Make dito, mdat, deto bits to 0s */
2171 devslp &= ~GENMASK_ULL(24, 2);
2172 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2173 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2174 (deto << PORT_DEVSLP_DETO_OFFSET) |
2175 PORT_DEVSLP_ADSE);
2176 writel(devslp, port_mmio + PORT_DEVSLP);
2177
2178 hpriv->start_engine(ap);
2179
2180 /* enable device sleep feature for the drive */
2181 err_mask = ata_dev_set_feature(dev,
2182 SETFEATURES_SATA_ENABLE,
2183 SATA_DEVSLP);
2184 if (err_mask && err_mask != AC_ERR_DEV)
2185 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2186}
2187
2188static void ahci_enable_fbs(struct ata_port *ap)
2189{
2190 struct ahci_host_priv *hpriv = ap->host->private_data;
2191 struct ahci_port_priv *pp = ap->private_data;
2192 void __iomem *port_mmio = ahci_port_base(ap);
2193 u32 fbs;
2194 int rc;
2195
2196 if (!pp->fbs_supported)
2197 return;
2198
2199 fbs = readl(port_mmio + PORT_FBS);
2200 if (fbs & PORT_FBS_EN) {
2201 pp->fbs_enabled = true;
2202 pp->fbs_last_dev = -1; /* initialization */
2203 return;
2204 }
2205
2206 rc = hpriv->stop_engine(ap);
2207 if (rc)
2208 return;
2209
2210 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2211 fbs = readl(port_mmio + PORT_FBS);
2212 if (fbs & PORT_FBS_EN) {
2213 dev_info(ap->host->dev, "FBS is enabled\n");
2214 pp->fbs_enabled = true;
2215 pp->fbs_last_dev = -1; /* initialization */
2216 } else
2217 dev_err(ap->host->dev, "Failed to enable FBS\n");
2218
2219 hpriv->start_engine(ap);
2220}
2221
2222static void ahci_disable_fbs(struct ata_port *ap)
2223{
2224 struct ahci_host_priv *hpriv = ap->host->private_data;
2225 struct ahci_port_priv *pp = ap->private_data;
2226 void __iomem *port_mmio = ahci_port_base(ap);
2227 u32 fbs;
2228 int rc;
2229
2230 if (!pp->fbs_supported)
2231 return;
2232
2233 fbs = readl(port_mmio + PORT_FBS);
2234 if ((fbs & PORT_FBS_EN) == 0) {
2235 pp->fbs_enabled = false;
2236 return;
2237 }
2238
2239 rc = hpriv->stop_engine(ap);
2240 if (rc)
2241 return;
2242
2243 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2244 fbs = readl(port_mmio + PORT_FBS);
2245 if (fbs & PORT_FBS_EN)
2246 dev_err(ap->host->dev, "Failed to disable FBS\n");
2247 else {
2248 dev_info(ap->host->dev, "FBS is disabled\n");
2249 pp->fbs_enabled = false;
2250 }
2251
2252 hpriv->start_engine(ap);
2253}
2254
2255static void ahci_pmp_attach(struct ata_port *ap)
2256{
2257 void __iomem *port_mmio = ahci_port_base(ap);
2258 struct ahci_port_priv *pp = ap->private_data;
2259 u32 cmd;
2260
2261 cmd = readl(port_mmio + PORT_CMD);
2262 cmd |= PORT_CMD_PMP;
2263 writel(cmd, port_mmio + PORT_CMD);
2264
2265 ahci_enable_fbs(ap);
2266
2267 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2268
2269 /*
2270 * We must not change the port interrupt mask register if the
2271 * port is marked frozen, the value in pp->intr_mask will be
2272 * restored later when the port is thawed.
2273 *
2274 * Note that during initialization, the port is marked as
2275 * frozen since the irq handler is not yet registered.
2276 */
2277 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2278 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2279}
2280
2281static void ahci_pmp_detach(struct ata_port *ap)
2282{
2283 void __iomem *port_mmio = ahci_port_base(ap);
2284 struct ahci_port_priv *pp = ap->private_data;
2285 u32 cmd;
2286
2287 ahci_disable_fbs(ap);
2288
2289 cmd = readl(port_mmio + PORT_CMD);
2290 cmd &= ~PORT_CMD_PMP;
2291 writel(cmd, port_mmio + PORT_CMD);
2292
2293 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2294
2295 /* see comment above in ahci_pmp_attach() */
2296 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2297 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2298}
2299
2300int ahci_port_resume(struct ata_port *ap)
2301{
2302 ahci_rpm_get_port(ap);
2303
2304 ahci_power_up(ap);
2305 ahci_start_port(ap);
2306
2307 if (sata_pmp_attached(ap))
2308 ahci_pmp_attach(ap);
2309 else
2310 ahci_pmp_detach(ap);
2311
2312 return 0;
2313}
2314EXPORT_SYMBOL_GPL(ahci_port_resume);
2315
2316#ifdef CONFIG_PM
2317static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2318{
2319 const char *emsg = NULL;
2320 int rc;
2321
2322 rc = ahci_deinit_port(ap, &emsg);
2323 if (rc == 0)
2324 ahci_power_down(ap);
2325 else {
2326 ata_port_err(ap, "%s (%d)\n", emsg, rc);
2327 ata_port_freeze(ap);
2328 }
2329
2330 ahci_rpm_put_port(ap);
2331 return rc;
2332}
2333#endif
2334
2335static int ahci_port_start(struct ata_port *ap)
2336{
2337 struct ahci_host_priv *hpriv = ap->host->private_data;
2338 struct device *dev = ap->host->dev;
2339 struct ahci_port_priv *pp;
2340 void *mem;
2341 dma_addr_t mem_dma;
2342 size_t dma_sz, rx_fis_sz;
2343
2344 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2345 if (!pp)
2346 return -ENOMEM;
2347
2348 if (ap->host->n_ports > 1) {
2349 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2350 if (!pp->irq_desc) {
2351 devm_kfree(dev, pp);
2352 return -ENOMEM;
2353 }
2354 snprintf(pp->irq_desc, 8,
2355 "%s%d", dev_driver_string(dev), ap->port_no);
2356 }
2357
2358 /* check FBS capability */
2359 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2360 void __iomem *port_mmio = ahci_port_base(ap);
2361 u32 cmd = readl(port_mmio + PORT_CMD);
2362 if (cmd & PORT_CMD_FBSCP)
2363 pp->fbs_supported = true;
2364 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2365 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2366 ap->port_no);
2367 pp->fbs_supported = true;
2368 } else
2369 dev_warn(dev, "port %d is not capable of FBS\n",
2370 ap->port_no);
2371 }
2372
2373 if (pp->fbs_supported) {
2374 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2375 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2376 } else {
2377 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2378 rx_fis_sz = AHCI_RX_FIS_SZ;
2379 }
2380
2381 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2382 if (!mem)
2383 return -ENOMEM;
2384 memset(mem, 0, dma_sz);
2385
2386 /*
2387 * First item in chunk of DMA memory: 32-slot command table,
2388 * 32 bytes each in size
2389 */
2390 pp->cmd_slot = mem;
2391 pp->cmd_slot_dma = mem_dma;
2392
2393 mem += AHCI_CMD_SLOT_SZ;
2394 mem_dma += AHCI_CMD_SLOT_SZ;
2395
2396 /*
2397 * Second item: Received-FIS area
2398 */
2399 pp->rx_fis = mem;
2400 pp->rx_fis_dma = mem_dma;
2401
2402 mem += rx_fis_sz;
2403 mem_dma += rx_fis_sz;
2404
2405 /*
2406 * Third item: data area for storing a single command
2407 * and its scatter-gather table
2408 */
2409 pp->cmd_tbl = mem;
2410 pp->cmd_tbl_dma = mem_dma;
2411
2412 /*
2413 * Save off initial list of interrupts to be enabled.
2414 * This could be changed later
2415 */
2416 pp->intr_mask = DEF_PORT_IRQ;
2417
2418 /*
2419 * Switch to per-port locking in case each port has its own MSI vector.
2420 */
2421 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2422 spin_lock_init(&pp->lock);
2423 ap->lock = &pp->lock;
2424 }
2425
2426 ap->private_data = pp;
2427
2428 /* engage engines, captain */
2429 return ahci_port_resume(ap);
2430}
2431
2432static void ahci_port_stop(struct ata_port *ap)
2433{
2434 const char *emsg = NULL;
2435 struct ahci_host_priv *hpriv = ap->host->private_data;
2436 void __iomem *host_mmio = hpriv->mmio;
2437 int rc;
2438
2439 /* de-initialize port */
2440 rc = ahci_deinit_port(ap, &emsg);
2441 if (rc)
2442 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
2443
2444 /*
2445 * Clear GHC.IS to prevent stuck INTx after disabling MSI and
2446 * re-enabling INTx.
2447 */
2448 writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT);
2449
2450 ahci_rpm_put_port(ap);
2451}
2452
2453void ahci_print_info(struct ata_host *host, const char *scc_s)
2454{
2455 struct ahci_host_priv *hpriv = host->private_data;
2456 u32 vers, cap, cap2, impl, speed;
2457 const char *speed_s;
2458
2459 vers = hpriv->version;
2460 cap = hpriv->cap;
2461 cap2 = hpriv->cap2;
2462 impl = hpriv->port_map;
2463
2464 speed = (cap >> 20) & 0xf;
2465 if (speed == 1)
2466 speed_s = "1.5";
2467 else if (speed == 2)
2468 speed_s = "3";
2469 else if (speed == 3)
2470 speed_s = "6";
2471 else
2472 speed_s = "?";
2473
2474 dev_info(host->dev,
2475 "AHCI %02x%02x.%02x%02x "
2476 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2477 ,
2478
2479 (vers >> 24) & 0xff,
2480 (vers >> 16) & 0xff,
2481 (vers >> 8) & 0xff,
2482 vers & 0xff,
2483
2484 ((cap >> 8) & 0x1f) + 1,
2485 (cap & 0x1f) + 1,
2486 speed_s,
2487 impl,
2488 scc_s);
2489
2490 dev_info(host->dev,
2491 "flags: "
2492 "%s%s%s%s%s%s%s"
2493 "%s%s%s%s%s%s%s"
2494 "%s%s%s%s%s%s%s"
2495 "%s%s\n"
2496 ,
2497
2498 cap & HOST_CAP_64 ? "64bit " : "",
2499 cap & HOST_CAP_NCQ ? "ncq " : "",
2500 cap & HOST_CAP_SNTF ? "sntf " : "",
2501 cap & HOST_CAP_MPS ? "ilck " : "",
2502 cap & HOST_CAP_SSS ? "stag " : "",
2503 cap & HOST_CAP_ALPM ? "pm " : "",
2504 cap & HOST_CAP_LED ? "led " : "",
2505 cap & HOST_CAP_CLO ? "clo " : "",
2506 cap & HOST_CAP_ONLY ? "only " : "",
2507 cap & HOST_CAP_PMP ? "pmp " : "",
2508 cap & HOST_CAP_FBS ? "fbs " : "",
2509 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2510 cap & HOST_CAP_SSC ? "slum " : "",
2511 cap & HOST_CAP_PART ? "part " : "",
2512 cap & HOST_CAP_CCC ? "ccc " : "",
2513 cap & HOST_CAP_EMS ? "ems " : "",
2514 cap & HOST_CAP_SXS ? "sxs " : "",
2515 cap2 & HOST_CAP2_DESO ? "deso " : "",
2516 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2517 cap2 & HOST_CAP2_SDS ? "sds " : "",
2518 cap2 & HOST_CAP2_APST ? "apst " : "",
2519 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2520 cap2 & HOST_CAP2_BOH ? "boh " : ""
2521 );
2522}
2523EXPORT_SYMBOL_GPL(ahci_print_info);
2524
2525void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2526 struct ata_port_info *pi)
2527{
2528 u8 messages;
2529 void __iomem *mmio = hpriv->mmio;
2530 u32 em_loc = readl(mmio + HOST_EM_LOC);
2531 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2532
2533 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2534 return;
2535
2536 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2537
2538 if (messages) {
2539 /* store em_loc */
2540 hpriv->em_loc = ((em_loc >> 16) * 4);
2541 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2542 hpriv->em_msg_type = messages;
2543 pi->flags |= ATA_FLAG_EM;
2544 if (!(em_ctl & EM_CTL_ALHD))
2545 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2546 }
2547}
2548EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2549
2550static int ahci_host_activate_multi_irqs(struct ata_host *host,
2551 struct scsi_host_template *sht)
2552{
2553 struct ahci_host_priv *hpriv = host->private_data;
2554 int i, rc;
2555
2556 rc = ata_host_start(host);
2557 if (rc)
2558 return rc;
2559 /*
2560 * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2561 * allocated. That is one MSI per port, starting from @irq.
2562 */
2563 for (i = 0; i < host->n_ports; i++) {
2564 struct ahci_port_priv *pp = host->ports[i]->private_data;
2565 int irq = hpriv->get_irq_vector(host, i);
2566
2567 /* Do not receive interrupts sent by dummy ports */
2568 if (!pp) {
2569 disable_irq(irq);
2570 continue;
2571 }
2572
2573 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard,
2574 0, pp->irq_desc, host->ports[i]);
2575
2576 if (rc)
2577 return rc;
2578 ata_port_desc(host->ports[i], "irq %d", irq);
2579 }
2580
2581 return ata_host_register(host, sht);
2582}
2583
2584/**
2585 * ahci_host_activate - start AHCI host, request IRQs and register it
2586 * @host: target ATA host
2587 * @sht: scsi_host_template to use when registering the host
2588 *
2589 * LOCKING:
2590 * Inherited from calling layer (may sleep).
2591 *
2592 * RETURNS:
2593 * 0 on success, -errno otherwise.
2594 */
2595int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht)
2596{
2597 struct ahci_host_priv *hpriv = host->private_data;
2598 int irq = hpriv->irq;
2599 int rc;
2600
2601 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2602 if (hpriv->irq_handler &&
2603 hpriv->irq_handler != ahci_single_level_irq_intr)
2604 dev_warn(host->dev,
2605 "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n");
2606 if (!hpriv->get_irq_vector) {
2607 dev_err(host->dev,
2608 "AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n");
2609 return -EIO;
2610 }
2611
2612 rc = ahci_host_activate_multi_irqs(host, sht);
2613 } else {
2614 rc = ata_host_activate(host, irq, hpriv->irq_handler,
2615 IRQF_SHARED, sht);
2616 }
2617
2618
2619 return rc;
2620}
2621EXPORT_SYMBOL_GPL(ahci_host_activate);
2622
2623MODULE_AUTHOR("Jeff Garzik");
2624MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2625MODULE_LICENSE("GPL");
2626