1/*
2 * pata_it821x.c - IT821x PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@lxorguk.ukuu.org.uk>
5 * (C) 2007 Bartlomiej Zolnierkiewicz
6 *
7 * based upon
8 *
9 * it821x.c
10 *
11 * linux/drivers/ide/pci/it821x.c Version 0.09 December 2004
12 *
13 * Copyright (C) 2004 Red Hat
14 *
15 * May be copied or modified under the terms of the GNU General Public License
16 * Based in part on the ITE vendor provided SCSI driver.
17 *
18 * Documentation available from IT8212F_V04.pdf
19 * http://www.ite.com.tw/EN/products_more.aspx?CategoryID=3&ID=5,91
20 * Some other documents are NDA.
21 *
22 * The ITE8212 isn't exactly a standard IDE controller. It has two
23 * modes. In pass through mode then it is an IDE controller. In its smart
24 * mode its actually quite a capable hardware raid controller disguised
25 * as an IDE controller. Smart mode only understands DMA read/write and
26 * identify, none of the fancier commands apply. The IT8211 is identical
27 * in other respects but lacks the raid mode.
28 *
29 * Errata:
30 * o Rev 0x10 also requires master/slave hold the same DMA timings and
31 * cannot do ATAPI MWDMA.
32 * o The identify data for raid volumes lacks CHS info (technically ok)
33 * but also fails to set the LBA28 and other bits. We fix these in
34 * the IDE probe quirk code.
35 * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode
36 * raid then the controller firmware dies
37 * o Smart mode without RAID doesn't clear all the necessary identify
38 * bits to reduce the command set to the one used
39 *
40 * This has a few impacts on the driver
41 * - In pass through mode we do all the work you would expect
42 * - In smart mode the clocking set up is done by the controller generally
43 * but we must watch the other limits and filter.
44 * - There are a few extra vendor commands that actually talk to the
45 * controller but only work PIO with no IRQ.
46 *
47 * Vendor areas of the identify block in smart mode are used for the
48 * timing and policy set up. Each HDD in raid mode also has a serial
49 * block on the disk. The hardware extra commands are get/set chip status,
50 * rebuild, get rebuild status.
51 *
52 * In Linux the driver supports pass through mode as if the device was
53 * just another IDE controller. If the smart mode is running then
54 * volumes are managed by the controller firmware and each IDE "disk"
55 * is a raid volume. Even more cute - the controller can do automated
56 * hotplug and rebuild.
57 *
58 * The pass through controller itself is a little demented. It has a
59 * flaw that it has a single set of PIO/MWDMA timings per channel so
60 * non UDMA devices restrict each others performance. It also has a
61 * single clock source per channel so mixed UDMA100/133 performance
62 * isn't perfect and we have to pick a clock. Thankfully none of this
63 * matters in smart mode. ATAPI DMA is not currently supported.
64 *
65 * It seems the smart mode is a win for RAID1/RAID10 but otherwise not.
66 *
67 * TODO
68 * - ATAPI and other speed filtering
69 * - RAID configuration ioctls
70 */
71
72#include <linux/kernel.h>
73#include <linux/module.h>
74#include <linux/pci.h>
75#include <linux/blkdev.h>
76#include <linux/delay.h>
77#include <linux/slab.h>
78#include <scsi/scsi_host.h>
79#include <linux/libata.h>
80
81
82#define DRV_NAME "pata_it821x"
83#define DRV_VERSION "0.4.2"
84
85struct it821x_dev
86{
87 unsigned int smart:1, /* Are we in smart raid mode */
88 timing10:1; /* Rev 0x10 */
89 u8 clock_mode; /* 0, ATA_50 or ATA_66 */
90 u8 want[2][2]; /* Mode/Pri log for master slave */
91 /* We need these for switching the clock when DMA goes on/off
92 The high byte is the 66Mhz timing */
93 u16 pio[2]; /* Cached PIO values */
94 u16 mwdma[2]; /* Cached MWDMA values */
95 u16 udma[2]; /* Cached UDMA values (per drive) */
96 u16 last_device; /* Master or slave loaded ? */
97};
98
99#define ATA_66 0
100#define ATA_50 1
101#define ATA_ANY 2
102
103#define UDMA_OFF 0
104#define MWDMA_OFF 0
105
106/*
107 * We allow users to force the card into non raid mode without
108 * flashing the alternative BIOS. This is also necessary right now
109 * for embedded platforms that cannot run a PC BIOS but are using this
110 * device.
111 */
112
113static int it8212_noraid;
114
115/**
116 * it821x_program - program the PIO/MWDMA registers
117 * @ap: ATA port
118 * @adev: Device to program
119 * @timing: Timing value (66Mhz in top 8bits, 50 in the low 8)
120 *
121 * Program the PIO/MWDMA timing for this channel according to the
122 * current clock. These share the same register so are managed by
123 * the DMA start/stop sequence as with the old driver.
124 */
125
126static void it821x_program(struct ata_port *ap, struct ata_device *adev, u16 timing)
127{
128 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
129 struct it821x_dev *itdev = ap->private_data;
130 int channel = ap->port_no;
131 u8 conf;
132
133 /* Program PIO/MWDMA timing bits */
134 if (itdev->clock_mode == ATA_66)
135 conf = timing >> 8;
136 else
137 conf = timing & 0xFF;
138 pci_write_config_byte(dev: pdev, where: 0x54 + 4 * channel, val: conf);
139}
140
141
142/**
143 * it821x_program_udma - program the UDMA registers
144 * @ap: ATA port
145 * @adev: ATA device to update
146 * @timing: Timing bits. Top 8 are for 66Mhz bottom for 50Mhz
147 *
148 * Program the UDMA timing for this drive according to the
149 * current clock. Handles the dual clocks and also knows about
150 * the errata on the 0x10 revision. The UDMA errata is partly handled
151 * here and partly in start_dma.
152 */
153
154static void it821x_program_udma(struct ata_port *ap, struct ata_device *adev, u16 timing)
155{
156 struct it821x_dev *itdev = ap->private_data;
157 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
158 int channel = ap->port_no;
159 int unit = adev->devno;
160 u8 conf;
161
162 /* Program UDMA timing bits */
163 if (itdev->clock_mode == ATA_66)
164 conf = timing >> 8;
165 else
166 conf = timing & 0xFF;
167 if (itdev->timing10 == 0)
168 pci_write_config_byte(dev: pdev, where: 0x56 + 4 * channel + unit, val: conf);
169 else {
170 /* Early revision must be programmed for both together */
171 pci_write_config_byte(dev: pdev, where: 0x56 + 4 * channel, val: conf);
172 pci_write_config_byte(dev: pdev, where: 0x56 + 4 * channel + 1, val: conf);
173 }
174}
175
176/**
177 * it821x_clock_strategy
178 * @ap: ATA interface
179 * @adev: ATA device being updated
180 *
181 * Select between the 50 and 66Mhz base clocks to get the best
182 * results for this interface.
183 */
184
185static void it821x_clock_strategy(struct ata_port *ap, struct ata_device *adev)
186{
187 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
188 struct it821x_dev *itdev = ap->private_data;
189 u8 unit = adev->devno;
190 struct ata_device *pair = ata_dev_pair(adev);
191
192 int clock, altclock;
193 u8 v;
194 int sel = 0;
195
196 /* Look for the most wanted clocking */
197 if (itdev->want[0][0] > itdev->want[1][0]) {
198 clock = itdev->want[0][1];
199 altclock = itdev->want[1][1];
200 } else {
201 clock = itdev->want[1][1];
202 altclock = itdev->want[0][1];
203 }
204
205 /* Master doesn't care does the slave ? */
206 if (clock == ATA_ANY)
207 clock = altclock;
208
209 /* Nobody cares - keep the same clock */
210 if (clock == ATA_ANY)
211 return;
212 /* No change */
213 if (clock == itdev->clock_mode)
214 return;
215
216 /* Load this into the controller */
217 if (clock == ATA_66)
218 itdev->clock_mode = ATA_66;
219 else {
220 itdev->clock_mode = ATA_50;
221 sel = 1;
222 }
223 pci_read_config_byte(dev: pdev, where: 0x50, val: &v);
224 v &= ~(1 << (1 + ap->port_no));
225 v |= sel << (1 + ap->port_no);
226 pci_write_config_byte(dev: pdev, where: 0x50, val: v);
227
228 /*
229 * Reprogram the UDMA/PIO of the pair drive for the switch
230 * MWDMA will be dealt with by the dma switcher
231 */
232 if (pair && itdev->udma[1-unit] != UDMA_OFF) {
233 it821x_program_udma(ap, adev: pair, timing: itdev->udma[1-unit]);
234 it821x_program(ap, adev: pair, timing: itdev->pio[1-unit]);
235 }
236 /*
237 * Reprogram the UDMA/PIO of our drive for the switch.
238 * MWDMA will be dealt with by the dma switcher
239 */
240 if (itdev->udma[unit] != UDMA_OFF) {
241 it821x_program_udma(ap, adev, timing: itdev->udma[unit]);
242 it821x_program(ap, adev, timing: itdev->pio[unit]);
243 }
244}
245
246/**
247 * it821x_passthru_set_piomode - set PIO mode data
248 * @ap: ATA interface
249 * @adev: ATA device
250 *
251 * Configure for PIO mode. This is complicated as the register is
252 * shared by PIO and MWDMA and for both channels.
253 */
254
255static void it821x_passthru_set_piomode(struct ata_port *ap, struct ata_device *adev)
256{
257 /* Spec says 89 ref driver uses 88 */
258 static const u16 pio[] = { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 };
259 static const u8 pio_want[] = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY };
260
261 struct it821x_dev *itdev = ap->private_data;
262 int unit = adev->devno;
263 int mode_wanted = adev->pio_mode - XFER_PIO_0;
264
265 /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */
266 itdev->want[unit][1] = pio_want[mode_wanted];
267 itdev->want[unit][0] = 1; /* PIO is lowest priority */
268 itdev->pio[unit] = pio[mode_wanted];
269 it821x_clock_strategy(ap, adev);
270 it821x_program(ap, adev, timing: itdev->pio[unit]);
271}
272
273/**
274 * it821x_passthru_set_dmamode - set initial DMA mode data
275 * @ap: ATA interface
276 * @adev: ATA device
277 *
278 * Set up the DMA modes. The actions taken depend heavily on the mode
279 * to use. If UDMA is used as is hopefully the usual case then the
280 * timing register is private and we need only consider the clock. If
281 * we are using MWDMA then we have to manage the setting ourself as
282 * we switch devices and mode.
283 */
284
285static void it821x_passthru_set_dmamode(struct ata_port *ap, struct ata_device *adev)
286{
287 static const u16 dma[] = { 0x8866, 0x3222, 0x3121 };
288 static const u8 mwdma_want[] = { ATA_ANY, ATA_66, ATA_ANY };
289 static const u16 udma[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 };
290 static const u8 udma_want[] = { ATA_ANY, ATA_50, ATA_ANY, ATA_66, ATA_66, ATA_50, ATA_66 };
291
292 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
293 struct it821x_dev *itdev = ap->private_data;
294 int channel = ap->port_no;
295 int unit = adev->devno;
296 u8 conf;
297
298 if (adev->dma_mode >= XFER_UDMA_0) {
299 int mode_wanted = adev->dma_mode - XFER_UDMA_0;
300
301 itdev->want[unit][1] = udma_want[mode_wanted];
302 itdev->want[unit][0] = 3; /* UDMA is high priority */
303 itdev->mwdma[unit] = MWDMA_OFF;
304 itdev->udma[unit] = udma[mode_wanted];
305 if (mode_wanted >= 5)
306 itdev->udma[unit] |= 0x8080; /* UDMA 5/6 select on */
307
308 /* UDMA on. Again revision 0x10 must do the pair */
309 pci_read_config_byte(dev: pdev, where: 0x50, val: &conf);
310 if (itdev->timing10)
311 conf &= channel ? 0x9F: 0xE7;
312 else
313 conf &= ~ (1 << (3 + 2 * channel + unit));
314 pci_write_config_byte(dev: pdev, where: 0x50, val: conf);
315 it821x_clock_strategy(ap, adev);
316 it821x_program_udma(ap, adev, timing: itdev->udma[unit]);
317 } else {
318 int mode_wanted = adev->dma_mode - XFER_MW_DMA_0;
319
320 itdev->want[unit][1] = mwdma_want[mode_wanted];
321 itdev->want[unit][0] = 2; /* MWDMA is low priority */
322 itdev->mwdma[unit] = dma[mode_wanted];
323 itdev->udma[unit] = UDMA_OFF;
324
325 /* UDMA bits off - Revision 0x10 do them in pairs */
326 pci_read_config_byte(dev: pdev, where: 0x50, val: &conf);
327 if (itdev->timing10)
328 conf |= channel ? 0x60: 0x18;
329 else
330 conf |= 1 << (3 + 2 * channel + unit);
331 pci_write_config_byte(dev: pdev, where: 0x50, val: conf);
332 it821x_clock_strategy(ap, adev);
333 }
334}
335
336/**
337 * it821x_passthru_bmdma_start - DMA start callback
338 * @qc: Command in progress
339 *
340 * Usually drivers set the DMA timing at the point the set_dmamode call
341 * is made. IT821x however requires we load new timings on the
342 * transitions in some cases.
343 */
344
345static void it821x_passthru_bmdma_start(struct ata_queued_cmd *qc)
346{
347 struct ata_port *ap = qc->ap;
348 struct ata_device *adev = qc->dev;
349 struct it821x_dev *itdev = ap->private_data;
350 int unit = adev->devno;
351
352 if (itdev->mwdma[unit] != MWDMA_OFF)
353 it821x_program(ap, adev, timing: itdev->mwdma[unit]);
354 else if (itdev->udma[unit] != UDMA_OFF && itdev->timing10)
355 it821x_program_udma(ap, adev, timing: itdev->udma[unit]);
356 ata_bmdma_start(qc);
357}
358
359/**
360 * it821x_passthru_bmdma_stop - DMA stop callback
361 * @qc: ATA command
362 *
363 * We loaded new timings in dma_start, as a result we need to restore
364 * the PIO timings in dma_stop so that the next command issue gets the
365 * right clock values.
366 */
367
368static void it821x_passthru_bmdma_stop(struct ata_queued_cmd *qc)
369{
370 struct ata_port *ap = qc->ap;
371 struct ata_device *adev = qc->dev;
372 struct it821x_dev *itdev = ap->private_data;
373 int unit = adev->devno;
374
375 ata_bmdma_stop(qc);
376 if (itdev->mwdma[unit] != MWDMA_OFF)
377 it821x_program(ap, adev, timing: itdev->pio[unit]);
378}
379
380
381/**
382 * it821x_passthru_dev_select - Select master/slave
383 * @ap: ATA port
384 * @device: Device number (not pointer)
385 *
386 * Device selection hook. If necessary perform clock switching
387 */
388
389static void it821x_passthru_dev_select(struct ata_port *ap,
390 unsigned int device)
391{
392 struct it821x_dev *itdev = ap->private_data;
393 if (itdev && device != itdev->last_device) {
394 struct ata_device *adev = &ap->link.device[device];
395 it821x_program(ap, adev, timing: itdev->pio[adev->devno]);
396 itdev->last_device = device;
397 }
398 ata_sff_dev_select(ap, device);
399}
400
401/**
402 * it821x_smart_qc_issue - wrap qc issue prot
403 * @qc: command
404 *
405 * Wrap the command issue sequence for the IT821x. We need to
406 * perform out own device selection timing loads before the
407 * usual happenings kick off
408 */
409
410static unsigned int it821x_smart_qc_issue(struct ata_queued_cmd *qc)
411{
412 switch(qc->tf.command)
413 {
414 /* Commands the firmware supports */
415 case ATA_CMD_READ:
416 case ATA_CMD_READ_EXT:
417 case ATA_CMD_WRITE:
418 case ATA_CMD_WRITE_EXT:
419 case ATA_CMD_PIO_READ:
420 case ATA_CMD_PIO_READ_EXT:
421 case ATA_CMD_PIO_WRITE:
422 case ATA_CMD_PIO_WRITE_EXT:
423 case ATA_CMD_READ_MULTI:
424 case ATA_CMD_READ_MULTI_EXT:
425 case ATA_CMD_WRITE_MULTI:
426 case ATA_CMD_WRITE_MULTI_EXT:
427 case ATA_CMD_ID_ATA:
428 case ATA_CMD_INIT_DEV_PARAMS:
429 case 0xFC: /* Internal 'report rebuild state' */
430 /* Arguably should just no-op this one */
431 case ATA_CMD_SET_FEATURES:
432 return ata_bmdma_qc_issue(qc);
433 }
434 ata_dev_dbg(qc->dev, "it821x: can't process command 0x%02X\n",
435 qc->tf.command);
436 return AC_ERR_DEV;
437}
438
439/**
440 * it821x_passthru_qc_issue - wrap qc issue prot
441 * @qc: command
442 *
443 * Wrap the command issue sequence for the IT821x. We need to
444 * perform out own device selection timing loads before the
445 * usual happenings kick off
446 */
447
448static unsigned int it821x_passthru_qc_issue(struct ata_queued_cmd *qc)
449{
450 it821x_passthru_dev_select(ap: qc->ap, device: qc->dev->devno);
451 return ata_bmdma_qc_issue(qc);
452}
453
454/**
455 * it821x_smart_set_mode - mode setting
456 * @link: interface to set up
457 * @unused: device that failed (error only)
458 *
459 * Use a non standard set_mode function. We don't want to be tuned.
460 * The BIOS configured everything. Our job is not to fiddle. We
461 * read the dma enabled bits from the PCI configuration of the device
462 * and respect them.
463 */
464
465static int it821x_smart_set_mode(struct ata_link *link, struct ata_device **unused)
466{
467 struct ata_device *dev;
468
469 ata_for_each_dev(dev, link, ENABLED) {
470 /* We don't really care */
471 dev->pio_mode = XFER_PIO_0;
472 dev->dma_mode = XFER_MW_DMA_0;
473 /* We do need the right mode information for DMA or PIO
474 and this comes from the current configuration flags */
475 if (ata_id_has_dma(dev->id)) {
476 ata_dev_info(dev, "configured for DMA\n");
477 dev->xfer_mode = XFER_MW_DMA_0;
478 dev->xfer_shift = ATA_SHIFT_MWDMA;
479 dev->flags &= ~ATA_DFLAG_PIO;
480 } else {
481 ata_dev_info(dev, "configured for PIO\n");
482 dev->xfer_mode = XFER_PIO_0;
483 dev->xfer_shift = ATA_SHIFT_PIO;
484 dev->flags |= ATA_DFLAG_PIO;
485 }
486 }
487 return 0;
488}
489
490/**
491 * it821x_dev_config - Called each device identify
492 * @adev: Device that has just been identified
493 *
494 * Perform the initial setup needed for each device that is chip
495 * special. In our case we need to lock the sector count to avoid
496 * blowing the brains out of the firmware with large LBA48 requests
497 *
498 */
499
500static void it821x_dev_config(struct ata_device *adev)
501{
502 unsigned char model_num[ATA_ID_PROD_LEN + 1];
503
504 ata_id_c_string(id: adev->id, s: model_num, ofs: ATA_ID_PROD, len: sizeof(model_num));
505
506 if (adev->max_sectors > 255)
507 adev->max_sectors = 255;
508
509 if (strstr(model_num, "Integrated Technology Express")) {
510 /* RAID mode */
511 if (adev->id[129] == 1)
512 ata_dev_info(adev, "%sRAID%d volume\n",
513 adev->id[147] ? "Bootable " : "",
514 adev->id[129]);
515 else
516 ata_dev_info(adev, "%sRAID%d volume (%dK stripe)\n",
517 adev->id[147] ? "Bootable " : "",
518 adev->id[129], adev->id[146]);
519 }
520 /* This is a controller firmware triggered funny, don't
521 report the drive faulty! */
522 adev->horkage &= ~ATA_HORKAGE_DIAGNOSTIC;
523 /* No HPA in 'smart' mode */
524 adev->horkage |= ATA_HORKAGE_BROKEN_HPA;
525}
526
527/**
528 * it821x_read_id - Hack identify data up
529 * @adev: device to read
530 * @tf: proposed taskfile
531 * @id: buffer for returned ident data
532 *
533 * Query the devices on this firmware driven port and slightly
534 * mash the identify data to stop us and common tools trying to
535 * use features not firmware supported. The firmware itself does
536 * some masking (eg SMART) but not enough.
537 */
538
539static unsigned int it821x_read_id(struct ata_device *adev,
540 struct ata_taskfile *tf, __le16 *id)
541{
542 unsigned int err_mask;
543 unsigned char model_num[ATA_ID_PROD_LEN + 1];
544
545 err_mask = ata_do_dev_read_id(dev: adev, tf, id);
546 if (err_mask)
547 return err_mask;
548 ata_id_c_string(id: (u16 *)id, s: model_num, ofs: ATA_ID_PROD, len: sizeof(model_num));
549
550 id[83] &= cpu_to_le16(~(1 << 12)); /* Cache flush is firmware handled */
551 id[84] &= cpu_to_le16(~(1 << 6)); /* No FUA */
552 id[85] &= cpu_to_le16(~(1 << 10)); /* No HPA */
553 id[76] = 0; /* No NCQ/AN etc */
554
555 if (strstr(model_num, "Integrated Technology Express")) {
556 /* Set feature bits the firmware neglects */
557 id[49] |= cpu_to_le16(0x0300); /* LBA, DMA */
558 id[83] &= cpu_to_le16(0x7FFF);
559 id[83] |= cpu_to_le16(0x4400); /* Word 83 is valid and LBA48 */
560 id[86] |= cpu_to_le16(0x0400); /* LBA48 on */
561 id[ATA_ID_MAJOR_VER] |= cpu_to_le16(0x1F);
562 /* Clear the serial number because it's different each boot
563 which breaks validation on resume */
564 memset(&id[ATA_ID_SERNO], 0x20, ATA_ID_SERNO_LEN);
565 }
566 return err_mask;
567}
568
569/**
570 * it821x_check_atapi_dma - ATAPI DMA handler
571 * @qc: Command we are about to issue
572 *
573 * Decide if this ATAPI command can be issued by DMA on this
574 * controller. Return 0 if it can be.
575 */
576
577static int it821x_check_atapi_dma(struct ata_queued_cmd *qc)
578{
579 struct ata_port *ap = qc->ap;
580 struct it821x_dev *itdev = ap->private_data;
581
582 /* Only use dma for transfers to/from the media. */
583 if (ata_qc_raw_nbytes(qc) < 2048)
584 return -EOPNOTSUPP;
585
586 /* No ATAPI DMA in smart mode */
587 if (itdev->smart)
588 return -EOPNOTSUPP;
589 /* No ATAPI DMA on rev 10 */
590 if (itdev->timing10)
591 return -EOPNOTSUPP;
592 /* Cool */
593 return 0;
594}
595
596/**
597 * it821x_display_disk - display disk setup
598 * @ap: ATA port
599 * @n: Device number
600 * @buf: Buffer block from firmware
601 *
602 * Produce a nice informative display of the device setup as provided
603 * by the firmware.
604 */
605
606static void it821x_display_disk(struct ata_port *ap, int n, u8 *buf)
607{
608 unsigned char id[41];
609 int mode = 0;
610 const char *mtype = "";
611 char mbuf[8];
612 const char *cbl = "(40 wire cable)";
613
614 static const char *types[5] = {
615 "RAID0", "RAID1", "RAID 0+1", "JBOD", "DISK"
616 };
617
618 if (buf[52] > 4) /* No Disk */
619 return;
620
621 ata_id_c_string(id: (u16 *)buf, s: id, ofs: 0, len: 41);
622
623 if (buf[51]) {
624 mode = ffs(buf[51]);
625 mtype = "UDMA";
626 } else if (buf[49]) {
627 mode = ffs(buf[49]);
628 mtype = "MWDMA";
629 }
630
631 if (buf[76])
632 cbl = "";
633
634 if (mode)
635 snprintf(buf: mbuf, size: 8, fmt: "%5s%d", mtype, mode - 1);
636 else
637 strcpy(p: mbuf, q: "PIO");
638 if (buf[52] == 4)
639 ata_port_info(ap, "%d: %-6s %-8s %s %s\n",
640 n, mbuf, types[buf[52]], id, cbl);
641 else
642 ata_port_info(ap, "%d: %-6s %-8s Volume: %1d %s %s\n",
643 n, mbuf, types[buf[52]], buf[53], id, cbl);
644 if (buf[125] < 100)
645 ata_port_info(ap, "%d: Rebuilding: %d%%\n", n, buf[125]);
646}
647
648/**
649 * it821x_firmware_command - issue firmware command
650 * @ap: IT821x port to interrogate
651 * @cmd: command
652 * @len: length
653 *
654 * Issue firmware commands expecting data back from the controller. We
655 * use this to issue commands that do not go via the normal paths. Other
656 * commands such as 0xFC can be issued normally.
657 */
658
659static u8 *it821x_firmware_command(struct ata_port *ap, u8 cmd, int len)
660{
661 u8 status;
662 int n = 0;
663 u16 *buf = kmalloc(size: len, GFP_KERNEL);
664
665 if (!buf)
666 return NULL;
667
668 /* This isn't quite a normal ATA command as we are talking to the
669 firmware not the drives */
670 ap->ctl |= ATA_NIEN;
671 iowrite8(ap->ctl, ap->ioaddr.ctl_addr);
672 ata_wait_idle(ap);
673 iowrite8(ATA_DEVICE_OBS, ap->ioaddr.device_addr);
674 iowrite8(cmd, ap->ioaddr.command_addr);
675 udelay(1);
676 /* This should be almost immediate but a little paranoia goes a long
677 way. */
678 while(n++ < 10) {
679 status = ioread8(ap->ioaddr.status_addr);
680 if (status & ATA_ERR) {
681 kfree(objp: buf);
682 ata_port_err(ap, "%s: rejected\n", __func__);
683 return NULL;
684 }
685 if (status & ATA_DRQ) {
686 ioread16_rep(port: ap->ioaddr.data_addr, buf, count: len/2);
687 return (u8 *)buf;
688 }
689 usleep_range(min: 500, max: 1000);
690 }
691 kfree(objp: buf);
692 ata_port_err(ap, "%s: timeout\n", __func__);
693 return NULL;
694}
695
696/**
697 * it821x_probe_firmware - firmware reporting/setup
698 * @ap: IT821x port being probed
699 *
700 * Probe the firmware of the controller by issuing firmware command
701 * 0xFA and analysing the returned data.
702 */
703
704static void it821x_probe_firmware(struct ata_port *ap)
705{
706 u8 *buf;
707 int i;
708
709 /* This is a bit ugly as we can't just issue a task file to a device
710 as this is controller magic */
711
712 buf = it821x_firmware_command(ap, cmd: 0xFA, len: 512);
713
714 if (buf != NULL) {
715 ata_port_info(ap, "pata_it821x: Firmware %02X/%02X/%02X%02X\n",
716 buf[505],
717 buf[506],
718 buf[507],
719 buf[508]);
720 for (i = 0; i < 4; i++)
721 it821x_display_disk(ap, n: i, buf: buf + 128 * i);
722 kfree(objp: buf);
723 }
724}
725
726
727
728/**
729 * it821x_port_start - port setup
730 * @ap: ATA port being set up
731 *
732 * The it821x needs to maintain private data structures and also to
733 * use the standard PCI interface which lacks support for this
734 * functionality. We instead set up the private data on the port
735 * start hook, and tear it down on port stop
736 */
737
738static int it821x_port_start(struct ata_port *ap)
739{
740 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
741 struct it821x_dev *itdev;
742 u8 conf;
743
744 int ret = ata_bmdma_port_start(ap);
745 if (ret < 0)
746 return ret;
747
748 itdev = devm_kzalloc(dev: &pdev->dev, size: sizeof(struct it821x_dev), GFP_KERNEL);
749 if (itdev == NULL)
750 return -ENOMEM;
751 ap->private_data = itdev;
752
753 pci_read_config_byte(dev: pdev, where: 0x50, val: &conf);
754
755 if (conf & 1) {
756 itdev->smart = 1;
757 /* Long I/O's although allowed in LBA48 space cause the
758 onboard firmware to enter the twighlight zone */
759 /* No ATAPI DMA in this mode either */
760 if (ap->port_no == 0)
761 it821x_probe_firmware(ap);
762 }
763 /* Pull the current clocks from 0x50 */
764 if (conf & (1 << (1 + ap->port_no)))
765 itdev->clock_mode = ATA_50;
766 else
767 itdev->clock_mode = ATA_66;
768
769 itdev->want[0][1] = ATA_ANY;
770 itdev->want[1][1] = ATA_ANY;
771 itdev->last_device = -1;
772
773 if (pdev->revision == 0x10) {
774 itdev->timing10 = 1;
775 /* Need to disable ATAPI DMA for this case */
776 if (!itdev->smart)
777 dev_warn(&pdev->dev,
778 "Revision 0x10, workarounds activated.\n");
779 }
780
781 return 0;
782}
783
784/**
785 * it821x_rdc_cable - Cable detect for RDC1010
786 * @ap: port we are checking
787 *
788 * Return the RDC1010 cable type. Unlike the IT821x we know how to do
789 * this and can do host side cable detect
790 */
791
792static int it821x_rdc_cable(struct ata_port *ap)
793{
794 u16 r40;
795 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
796
797 pci_read_config_word(dev: pdev, where: 0x40, val: &r40);
798 if (r40 & (1 << (2 + ap->port_no)))
799 return ATA_CBL_PATA40;
800 return ATA_CBL_PATA80;
801}
802
803static const struct scsi_host_template it821x_sht = {
804 ATA_BMDMA_SHT(DRV_NAME),
805};
806
807static struct ata_port_operations it821x_smart_port_ops = {
808 .inherits = &ata_bmdma_port_ops,
809
810 .check_atapi_dma= it821x_check_atapi_dma,
811 .qc_issue = it821x_smart_qc_issue,
812
813 .cable_detect = ata_cable_80wire,
814 .set_mode = it821x_smart_set_mode,
815 .dev_config = it821x_dev_config,
816 .read_id = it821x_read_id,
817
818 .port_start = it821x_port_start,
819};
820
821static struct ata_port_operations it821x_passthru_port_ops = {
822 .inherits = &ata_bmdma_port_ops,
823
824 .check_atapi_dma= it821x_check_atapi_dma,
825 .sff_dev_select = it821x_passthru_dev_select,
826 .bmdma_start = it821x_passthru_bmdma_start,
827 .bmdma_stop = it821x_passthru_bmdma_stop,
828 .qc_issue = it821x_passthru_qc_issue,
829
830 .cable_detect = ata_cable_unknown,
831 .set_piomode = it821x_passthru_set_piomode,
832 .set_dmamode = it821x_passthru_set_dmamode,
833
834 .port_start = it821x_port_start,
835};
836
837static struct ata_port_operations it821x_rdc_port_ops = {
838 .inherits = &ata_bmdma_port_ops,
839
840 .check_atapi_dma= it821x_check_atapi_dma,
841 .sff_dev_select = it821x_passthru_dev_select,
842 .bmdma_start = it821x_passthru_bmdma_start,
843 .bmdma_stop = it821x_passthru_bmdma_stop,
844 .qc_issue = it821x_passthru_qc_issue,
845
846 .cable_detect = it821x_rdc_cable,
847 .set_piomode = it821x_passthru_set_piomode,
848 .set_dmamode = it821x_passthru_set_dmamode,
849
850 .port_start = it821x_port_start,
851};
852
853static void it821x_disable_raid(struct pci_dev *pdev)
854{
855 /* Neither the RDC nor the IT8211 */
856 if (pdev->vendor != PCI_VENDOR_ID_ITE ||
857 pdev->device != PCI_DEVICE_ID_ITE_8212)
858 return;
859
860 /* Reset local CPU, and set BIOS not ready */
861 pci_write_config_byte(dev: pdev, where: 0x5E, val: 0x01);
862
863 /* Set to bypass mode, and reset PCI bus */
864 pci_write_config_byte(dev: pdev, where: 0x50, val: 0x00);
865 pci_write_config_word(dev: pdev, PCI_COMMAND,
866 PCI_COMMAND_PARITY | PCI_COMMAND_IO |
867 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
868 pci_write_config_word(dev: pdev, where: 0x40, val: 0xA0F3);
869
870 pci_write_config_dword(dev: pdev,where: 0x4C, val: 0x02040204);
871 pci_write_config_byte(dev: pdev, where: 0x42, val: 0x36);
872 pci_write_config_byte(dev: pdev, PCI_LATENCY_TIMER, val: 0x20);
873}
874
875
876static int it821x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
877{
878 u8 conf;
879
880 static const struct ata_port_info info_smart = {
881 .flags = ATA_FLAG_SLAVE_POSS,
882 .pio_mask = ATA_PIO4,
883 .mwdma_mask = ATA_MWDMA2,
884 .udma_mask = ATA_UDMA6,
885 .port_ops = &it821x_smart_port_ops
886 };
887 static const struct ata_port_info info_passthru = {
888 .flags = ATA_FLAG_SLAVE_POSS,
889 .pio_mask = ATA_PIO4,
890 .mwdma_mask = ATA_MWDMA2,
891 .udma_mask = ATA_UDMA6,
892 .port_ops = &it821x_passthru_port_ops
893 };
894 static const struct ata_port_info info_rdc = {
895 .flags = ATA_FLAG_SLAVE_POSS,
896 .pio_mask = ATA_PIO4,
897 .mwdma_mask = ATA_MWDMA2,
898 .udma_mask = ATA_UDMA6,
899 .port_ops = &it821x_rdc_port_ops
900 };
901 static const struct ata_port_info info_rdc_11 = {
902 .flags = ATA_FLAG_SLAVE_POSS,
903 .pio_mask = ATA_PIO4,
904 .mwdma_mask = ATA_MWDMA2,
905 /* No UDMA */
906 .port_ops = &it821x_rdc_port_ops
907 };
908
909 const struct ata_port_info *ppi[] = { NULL, NULL };
910 static const char *mode[2] = { "pass through", "smart" };
911 int rc;
912
913 rc = pcim_enable_device(pdev);
914 if (rc)
915 return rc;
916
917 if (pdev->vendor == PCI_VENDOR_ID_RDC) {
918 /* Deal with Vortex86SX */
919 if (pdev->revision == 0x11)
920 ppi[0] = &info_rdc_11;
921 else
922 ppi[0] = &info_rdc;
923 } else {
924 /* Force the card into bypass mode if so requested */
925 if (it8212_noraid) {
926 dev_info(&pdev->dev, "forcing bypass mode.\n");
927 it821x_disable_raid(pdev);
928 }
929 pci_read_config_byte(dev: pdev, where: 0x50, val: &conf);
930 conf &= 1;
931
932 dev_info(&pdev->dev, "controller in %s mode.\n", mode[conf]);
933
934 if (conf == 0)
935 ppi[0] = &info_passthru;
936 else
937 ppi[0] = &info_smart;
938 }
939 return ata_pci_bmdma_init_one(pdev, ppi, sht: &it821x_sht, NULL, hflags: 0);
940}
941
942#ifdef CONFIG_PM_SLEEP
943static int it821x_reinit_one(struct pci_dev *pdev)
944{
945 struct ata_host *host = pci_get_drvdata(pdev);
946 int rc;
947
948 rc = ata_pci_device_do_resume(pdev);
949 if (rc)
950 return rc;
951 /* Resume - turn raid back off if need be */
952 if (it8212_noraid)
953 it821x_disable_raid(pdev);
954 ata_host_resume(host);
955 return rc;
956}
957#endif
958
959static const struct pci_device_id it821x[] = {
960 { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8211), },
961 { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8212), },
962 { PCI_VDEVICE(RDC, PCI_DEVICE_ID_RDC_D1010), },
963
964 { },
965};
966
967static struct pci_driver it821x_pci_driver = {
968 .name = DRV_NAME,
969 .id_table = it821x,
970 .probe = it821x_init_one,
971 .remove = ata_pci_remove_one,
972#ifdef CONFIG_PM_SLEEP
973 .suspend = ata_pci_device_suspend,
974 .resume = it821x_reinit_one,
975#endif
976};
977
978module_pci_driver(it821x_pci_driver);
979
980MODULE_AUTHOR("Alan Cox");
981MODULE_DESCRIPTION("low-level driver for the IT8211/IT8212 IDE RAID controller");
982MODULE_LICENSE("GPL");
983MODULE_DEVICE_TABLE(pci, it821x);
984MODULE_VERSION(DRV_VERSION);
985
986module_param_named(noraid, it8212_noraid, int, S_IRUGO);
987MODULE_PARM_DESC(noraid, "Force card into bypass mode");
988

source code of linux/drivers/ata/pata_it821x.c